mmc: controller register update as per SD4.0 specs
Sachin Nikam [Thu, 10 Nov 2011 10:52:42 +0000 (15:52 +0530)]
Updating the header for sdmmc controller registers so that
it is compatible with SD4.0 specifications.

Bug 896249

Change-Id: I35e383441c216af8877af3015eb079337c324152
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/84782
Reviewed-by: Mark Stadler <mastadler@nvidia.com>

drivers/mmc/host/sdhci.c
drivers/mmc/host/sdhci.h

index ad63193..64ac94e 100644 (file)
@@ -863,7 +863,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
                ctrl &= ~SDHCI_CTRL_DMA_MASK;
                if ((host->flags & SDHCI_REQ_USE_DMA) &&
                        (host->flags & SDHCI_USE_ADMA))
-                       ctrl |= SDHCI_CTRL_ADMA32;
+                       ctrl |= SDHCI_CTRL_ADMA2;
                else
                        ctrl |= SDHCI_CTRL_SDMA;
                sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
index f405dac..3142578 100644 (file)
@@ -4,6 +4,7 @@
  * Header file for Host Controller registers and I/O accessors.
  *
  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
+ *  Copyright (C) 2011-2012 NVIDIA Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -64,6 +65,7 @@
 #define SDHCI_PRESENT_STATE    0x24
 #define  SDHCI_CMD_INHIBIT     0x00000001
 #define  SDHCI_DATA_INHIBIT    0x00000002
+#define  SDHCI_RETUNING_REQUIRED       0x00000008
 #define  SDHCI_DOING_WRITE     0x00000100
 #define  SDHCI_DOING_READ      0x00000200
 #define  SDHCI_SPACE_AVAILABLE 0x00000400
 #define  SDHCI_WRITE_PROTECT   0x00080000
 #define  SDHCI_DATA_LVL_MASK   0x00F00000
 #define   SDHCI_DATA_LVL_SHIFT 20
+#define  SDHCI_IN_DORMANT_STATE        0x20000000
+#define  SDHCI_UHS2_LANE_SYNC_PHY_INITIALIZED  0x40000000
+#define  SDHCI_UHS2_IF_DETECTED        0x80000000
+
 
 #define SDHCI_HOST_CONTROL     0x28
 #define  SDHCI_CTRL_LED                0x01
 #define  SDHCI_CTRL_HISPD      0x04
 #define  SDHCI_CTRL_DMA_MASK   0x18
 #define   SDHCI_CTRL_SDMA      0x00
-#define   SDHCI_CTRL_ADMA1     0x08
-#define   SDHCI_CTRL_ADMA32    0x10
-#define   SDHCI_CTRL_ADMA64    0x18
+#define   SDHCI_CTRL_RSVD      0x08
+#define   SDHCI_CTRL_ADMA2     0x10
+#define   SDHCI_CTRL_ADMA3     0x18
 #define   SDHCI_CTRL_8BITBUS   0x20
+#define   SDHCI_CTRL_SD_BUS_POWER_ON   0x00000100
+#define   SDHCI_CTRL_SD_BUS_VOLTAGE_SELECT_SHIFT       9
+#define   SDHCI_CTRL_SD_BUS_VOLTAGE_SELECT_MASK        0x00000E00
+#define   SDHCI_CTRL_SD_BUS_POWER_ON_VDD2      0x00001000
+#define   SDHCI_CTRL_SD_BUS_VOLTAGE_SELECT_VDD2_SHIFT  13
+#define   SDHCI_CTRL_SD_BUS_VOLTAGE_SELECT_VDD2_MASK   0x0000E000
+#define   SDHCI_CTRL_SD_BUS_VOLTAGE_V1_8       5
+#define   SDHCI_CTRL_SD_BUS_VOLTAGE_V3_0       6
+#define   SDHCI_CTRL_SD_BUS_VOLTAGE_V3_3       7
 
 #define SDHCI_POWER_CONTROL    0x29
 #define  SDHCI_POWER_ON                0x01
 #define  SDHCI_DIV_MASK        0xFF
 #define  SDHCI_DIV_MASK_LEN    8
 #define  SDHCI_DIV_HI_MASK     0x300
+#define  SDHCI_UPPER_SDCLK_FREQUENCYSELECT_MASK        0x00C0
 #define  SDHCI_PROG_CLOCK_MODE 0x0020
 #define  SDHCI_CLOCK_CARD_EN   0x0004
 #define  SDHCI_CLOCK_INT_STABLE        0x0002
 #define  SDHCI_INT_DATA_AVAIL  0x00000020
 #define  SDHCI_INT_CARD_INSERT 0x00000040
 #define  SDHCI_INT_CARD_REMOVE 0x00000080
+#define  SDHCI_INT_RETUNING_EVENT      0x00001000
 #define  SDHCI_INT_CARD_INT    0x00000100
 #define  SDHCI_INT_ERROR       0x00008000
 #define  SDHCI_INT_TIMEOUT     0x00010000
 #define  SDHCI_INT_BUS_POWER   0x00800000
 #define  SDHCI_INT_ACMD12ERR   0x01000000
 #define  SDHCI_INT_ADMA_ERROR  0x02000000
+#define  SDHCI_INT_TUNING_ERROR        0x04000000
+#define  SDHCI_INT_RESP_ERROR  0x08000000
+#define  SDHCI_INT_SPI_ERROR   0x20000000
 
 #define  SDHCI_INT_NORMAL_MASK 0x00007FFF
 #define  SDHCI_INT_ERROR_MASK  0xFFFF8000
 #define SDHCI_INT_ALL_MASK     ((unsigned int)-1)
 
 #define SDHCI_ACMD12_ERR       0x3C
+#define  SDHCI_NOT_EXECUTED    0x00000001
+#define  SDHCI_TIMEOUT_ERR     0x00000002
+#define  SDHCI_CRC_ERR 0x00000004
+#define  SDHCI_END_BIT_ERR     0x00000008
+#define  SDHCI_INDEX_ERR       0x00000010
+#define  SDHCI_COMMAND_NOT_ISSUED      0x0080
+#define  SDHCI_UHS_MODE_SEL_SHIFT      16
+#define  SDHCI_UHS_MODE_SEL_MASK       000x0700
+#define  SDHCI_UHS_SDR12       0
+#define  SDHCI_UHS_SDR25       1
+#define  SDHCI_UHS_SDR50       2
+#define  SDHCI_UHS_SDR104      3
+#define  SDHCI_UHS_DDR50       4
+#define  SDHCI_UHS2    7
+#define  SDHCI_VOLT_18_EN      0x00080000
+#define  SDHCI_EXECUTE_TUNING  0x00400000
+#define  SDHCI_SAMPLING_CLK_TUNED      0x00800000
+#define  SDHCI_UHS2_IF_EN      0x01000000
+#define  SDHCI_HOST_VERSION_4_EN       0x10000000
+#define  SDHCI_ADDRESSING_64BIT_EN     0x20000000
+#define  SDHCI_ASYNC_INTR_EN   0x40000000
+#define  SDHCI_PRESET_VALUE_SW_SEL     0x80000000
 
 #define SDHCI_HOST_CONTROL2            0x3E
 #define  SDHCI_CTRL_UHS_MASK           0x0007
 #define  SDHCI_TIMEOUT_CLK_MASK        0x0000003F
 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 #define  SDHCI_TIMEOUT_CLK_UNIT        0x00000080
-#define  SDHCI_CLOCK_BASE_MASK 0x00003F00
+#define  SDHCI_CLOCK_BASE_MASK 0x0000FF00
 #define  SDHCI_CLOCK_V3_BASE_MASK      0x0000FF00
 #define  SDHCI_CLOCK_BASE_SHIFT        8
 #define  SDHCI_MAX_BLOCK_MASK  0x00030000
 #define  SDHCI_MAX_BLOCK_SHIFT  16
 #define  SDHCI_CAN_DO_8BIT     0x00040000
 #define  SDHCI_CAN_DO_ADMA2    0x00080000
-#define  SDHCI_CAN_DO_ADMA1    0x00100000
 #define  SDHCI_CAN_DO_HISPD    0x00200000
 #define  SDHCI_CAN_DO_SDMA     0x00400000
 #define  SDHCI_CAN_VDD_330     0x01000000
 #define  SDHCI_CAN_VDD_300     0x02000000
 #define  SDHCI_CAN_VDD_180     0x04000000
 #define  SDHCI_CAN_64BIT       0x10000000
+#define  SDHCI_CAN_ASYNC_INTR  0x20000000
+#define  SDHCI_CAN_SLOT_TYPE   0x40000000
 
+#define SDHCI_CAPABILITIES_1   0x44
 #define  SDHCI_SUPPORT_SDR50   0x00000001
 #define  SDHCI_SUPPORT_SDR104  0x00000002
 #define  SDHCI_SUPPORT_DDR50   0x00000004
+#define  SDHCI_SUPPORT_UHS2    0x00000008
 #define  SDHCI_DRIVER_TYPE_A   0x00000010
 #define  SDHCI_DRIVER_TYPE_C   0x00000020
 #define  SDHCI_DRIVER_TYPE_D   0x00000040
 #define  SDHCI_RETUNING_MODE_SHIFT             14
 #define  SDHCI_CLOCK_MUL_MASK  0x00FF0000
 #define  SDHCI_CLOCK_MUL_SHIFT 16
-
-#define SDHCI_CAPABILITIES_1   0x44
+#define  SDHCI_SUPPORT_ADMA3   0x08000000
+#define  SDHCI_SUPPORT_VDD2_1_8V       0x10000000
 
 #define SDHCI_MAX_CURRENT              0x48
 #define  SDHCI_MAX_CURRENT_LIMIT       0xFF
 /* 55-57 reserved */
 
 #define SDHCI_ADMA_ADDRESS     0x58
-
-/* 60-FB reserved */
+#define SDHCI_UPPER_ADMA_ADDRESS       0x5C
+
+#define SDHCI_PRESET_DEFAULT_AND_INIT  0x60
+#define SDHCI_PRESET_SDR12_AND_HIGH    0x64
+#define SDHCI_PRESET_SDR50_AND_SDR25   0x68
+#define SDHCI_PRESET_DDR50_AND_SDR104  0x6C
+#define SDHCI_PRESET_DDR50_AND_SDR104  0x6C
+#define  SDHCI_SDCLK_FREQ_VAL_LOW_SHIFT        0
+#define  SDHCI_SDCLK_FREQ_VAL_LOW_MASK 0x000003FF
+#define  SDHCI_SDCLK_FREQ_VAL_HIGH_SHIFT       16
+#define  SDHCI_SDCLK_FREQ_VAL_HIGH_MASK        0x03FF0000
+#define  SDHCI_CLK_GEN_VAL_LOW_SHIFT   10
+#define  SDHCI_CLK_GEN_VAL_LOW_MASK    0x00000400
+#define  SDHCI_CLK_GEN_VAL_HIGH_SHIFT  26
+#define  SDHCI_CLK_GEN_VAL_HIGH_MASK   0x04000000
+#define  SDHCI_DRIVE_STRENGTH_VAL_LOW_SHIFT    14
+#define  SDHCI_DRIVE_STRENGTH_VAL_LOW_MASK     0x0000C000
+#define  SDHCI_DRIVE_STRENGTH_VAL_HIGH_SHIFT   30
+#define  SDHCI_DRIVE_STRENGTH_VAL_HIGH_MASK    0xC0000000
 
 #define SDHCI_PRESET_FOR_SDR12 0x66
 #define SDHCI_PRESET_FOR_SDR25 0x68
 #define   SDHCI_SPEC_100       0
 #define   SDHCI_SPEC_200       1
 #define   SDHCI_SPEC_300       2
+#define   SDHCI_SPEC_400       3
 
 /*
  * End of controller registers.