arm: tegra: timer: New Tegra3 IRQ mapping
Scott Williams [Mon, 14 Mar 2011 22:24:46 +0000 (15:24 -0700)]
Rename timer.c to timer-t2.c for consistency with other
chip-specific implementations.

Bug 790458
Bug 790448
Bug 738259

Original-Change-Id: I7e0fceb716590cd92b64ba00c0bebe659e9beb21
Reviewed-on: http://git-master/r/22885
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I322324c2177d57657a63e9428f8e49d5df2b828e

Rebase-Id: R7312866cdc8044a71cc2f83ad4bc7aa66b07416d

arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/include/mach/irqs.h
arch/arm/mach-tegra/timer-t2.c [moved from arch/arm/mach-tegra/timer.c with 100% similarity]
arch/arm/mach-tegra/timer-t3.c

index 778f969..bfad23a 100644 (file)
@@ -9,7 +9,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += common-t3.o
 obj-y                                   += io.o
 obj-y                                   += irq.o
 obj-y                                   += clock.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += timer.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += timer-t2.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += timer-t3.o
 obj-y                                   += pinmux.o
 obj-y                                   += delay.o
index 24015fa..c8fbfde 100644 (file)
 #define INT_APB_DMA_CH15               (INT_QUAD_BASE + 23)
 #define INT_I2C4                       (INT_QUAD_BASE + 24)
 #define INT_TMR5                       (INT_QUAD_BASE + 25)
-#define INT_TMR_SHARED                 (INT_QUAD_BASE + 26)
+#define INT_TMR_SHARED                 (INT_QUAD_BASE + 26) /* Deprecated */
 #define INT_WDT_CPU                    (INT_QUAD_BASE + 27)
 #define INT_WDT_AVP                    (INT_QUAD_BASE + 28)
 #define INT_GPIO8                      (INT_QUAD_BASE + 29)
 #define INT_CPU5_PMU_INTR              (INT_QUINT_BASE + 21)
 #define INT_CPU6_PMU_INTR              (INT_QUINT_BASE + 22)
 #define INT_CPU7_PMU_INTR              (INT_QUINT_BASE + 23)
-#define INT_QUINT_RES_24               (INT_QUINT_BASE + 24)
-#define INT_QUINT_RES_25               (INT_QUINT_BASE + 25)
-#define INT_QUINT_RES_26               (INT_QUINT_BASE + 26)
-#define INT_QUINT_RES_27               (INT_QUINT_BASE + 27)
-#define INT_QUINT_RES_28               (INT_QUINT_BASE + 28)
+#define INT_TMR6                       (INT_QUINT_BASE + 24)
+#define INT_TMR7                       (INT_QUINT_BASE + 25)
+#define INT_TMR8                       (INT_QUINT_BASE + 26)
+#define INT_TMR9                       (INT_QUINT_BASE + 27)
+#define INT_TMR10                      (INT_QUINT_BASE + 28)
 #define INT_QUINT_RES_29               (INT_QUINT_BASE + 29)
 #define INT_QUINT_RES_30               (INT_QUINT_BASE + 30)
 #define INT_QUINT_RES_31               (INT_QUINT_BASE + 31)
index c41b73e..c2badf2 100644 (file)
 #define TIMERUS_USEC_CFG 0x14
 #define TIMERUS_CNTR_FREEZE 0x4c
 
-#define TIMER1_BASE 0x0
-#define TIMER2_BASE 0x8
-#define TIMER3_BASE 0x50
-#define TIMER4_BASE 0x58
-#define TIMER5_BASE 0x60
-#define TIMER6_BASE 0x68
+#define TIMER1_OFFSET (TEGRA_TMR1_BASE-TEGRA_TMR1_BASE)
+#define TIMER2_OFFSET (TEGRA_TMR2_BASE-TEGRA_TMR1_BASE)
+#define TIMER3_OFFSET (TEGRA_TMR3_BASE-TEGRA_TMR1_BASE)
+#define TIMER4_OFFSET (TEGRA_TMR4_BASE-TEGRA_TMR1_BASE)
+#define TIMER5_OFFSET (TEGRA_TMR5_BASE-TEGRA_TMR1_BASE)
+#define TIMER6_OFFSET (TEGRA_TMR6_BASE-TEGRA_TMR1_BASE)
 
 #define TIMER_PTV 0x0
 #define TIMER_PCR 0x4
@@ -91,7 +91,7 @@ static int tegra_timer_set_next_event(unsigned long cycles,
        u32 reg;
 
        reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
-       timer_writel(reg, TIMER1_BASE + TIMER_PTV);
+       timer_writel(reg, TIMER1_OFFSET + TIMER_PTV);
 
        return 0;
 }
@@ -101,12 +101,12 @@ static void tegra_timer_set_mode(enum clock_event_mode mode,
 {
        u32 reg;
 
-       timer_writel(0, TIMER1_BASE + TIMER_PTV);
+       timer_writel(0, TIMER1_OFFSET + TIMER_PTV);
 
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
                reg = 0xC0000000 | ((1000000/HZ)-1);
-               timer_writel(reg, TIMER1_BASE + TIMER_PTV);
+               timer_writel(reg, TIMER1_OFFSET + TIMER_PTV);
                break;
        case CLOCK_EVT_MODE_ONESHOT:
                break;
@@ -199,7 +199,7 @@ void read_persistent_clock(struct timespec *ts)
 static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
 {
        struct clock_event_device *evt = (struct clock_event_device *)dev_id;
-       timer_writel(1<<30, TIMER1_BASE + TIMER_PCR);
+       timer_writel(1<<30, TIMER1_OFFSET + TIMER_PCR);
        evt->event_handler(evt);
        return IRQ_HANDLED;
 }
@@ -213,10 +213,10 @@ static struct irqaction tegra_timer_irq = {
 };
 
 static int lp2_wake_timers[] = {
-       TIMER3_BASE,
-       TIMER4_BASE,
-       TIMER5_BASE,
-       TIMER6_BASE,
+       TIMER3_OFFSET,
+       TIMER4_OFFSET,
+       TIMER5_OFFSET,
+       TIMER6_OFFSET,
 };
 
 static irqreturn_t tegra_lp2wake_interrupt(int irq, void *dev_id)
@@ -242,7 +242,7 @@ static struct irqaction tegra_lp2wake_irq_cpu##n = { \
        LP2_TIMER_IRQ_ACTION(0, INT_TMR3); \
        LP2_TIMER_IRQ_ACTION(1, INT_TMR4); \
        LP2_TIMER_IRQ_ACTION(2, INT_TMR5); \
-       LP2_TIMER_IRQ_ACTION(3, INT_TMR_SHARED);
+       LP2_TIMER_IRQ_ACTION(3, INT_TMR6);
 
 LP2_TIMER_IRQ_ACTIONS();
 
@@ -297,6 +297,8 @@ static void test_lp2_wake_timers(void){}
 static void __init tegra_init_timer(void)
 {
        unsigned long rate = clk_measure_input_freq();
+       void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
+       unsigned long id;
        int ret;
 
 #ifdef CONFIG_HAVE_ARM_TWD
@@ -340,6 +342,24 @@ static void __init tegra_init_timer(void)
                BUG();
        }
 
+       /* For T30.A01 use INT_TMR_SHARED instead of INT_TMR6. */
+       id = readl(chip_id);
+       if (((id & 0xFF00) >> 8) == 0x30) {
+#ifndef CONFIG_TEGRA_FPGA_PLATFORM
+               if (((id >> 16) & 0xf) == 1) {
+                       tegra_lp2wake_irq_cpu3.irq = INT_TMR_SHARED;
+               }
+#else
+               void __iomem *emu_rev = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x860;
+               unsigned long reg = readl(emu_rev);
+               unsigned long netlist = reg & 0xFFFF;
+               unsigned long patch = (reg >> 16) & 0xFF;
+               if ((netlist == 12) && (patch < 14)) {
+                       tegra_lp2wake_irq_cpu3.irq = INT_TMR_SHARED;
+               }
+#endif
+       }
+
        REGISTER_LP2_WAKE_IRQS();
 
        clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);