ARM: tegra: power: Don't lower clocks on LP0 entry
Alex Frid [Sun, 12 Feb 2012 04:19:42 +0000 (20:19 -0800)]
Do not change (lower) CPU and system clocks, and do not disable PLLs
on entry to LP0, since all clocks and PLLs are stopped in h/w, anyway.

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 0142197cf7b1828fa7935c9d8715f37313864db1)

Change-Id: I2f175882d4d3dcfe5aee9c460f873a5e907e4ece
Reviewed-on: http://git-master/r/84714
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: R5213db4e83e16fe448a0a494af25ab9f340cce0b

arch/arm/mach-tegra/pm.c
arch/arm/mach-tegra/sleep-t30.S

index 43c66f1..55311f8 100644 (file)
@@ -691,6 +691,7 @@ static void tegra_pm_set(enum tegra_suspend_mode mode)
 
        switch (mode) {
        case TEGRA_SUSPEND_LP0:
+               rate = clk_get_rate_all_locked(tegra_pclk);
                if (pdata->combined_req) {
                        reg |= TEGRA_POWER_PWRREQ_OE;
                        reg &= ~TEGRA_POWER_CPU_PWRREQ_OE;
index 0fc1879..a2a88ae 100644 (file)
@@ -511,8 +511,19 @@ tegra3_tear_down_core:
  * r7 = TEGRA_TMRUS_BASE
  */
 tegra3_cpu_clk32k:
+       ldr     r0, [r4, #PMC_CTRL]
+       tst     r0, #PMC_CTRL_SIDE_EFFECT_LP0
+       beq     lp1_clocks_prepare
+
+       /* enable PLLM via PMC in LP0 */
+       ldr     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
+       orr     r0, r0, #((1<<12) | (1 << 11))
+       str     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
+       mov     pc, lr
+
        /* start by jumping to clkm to safely disable PLLs, then jump
         * to clks */
+lp1_clocks_prepare:
        mov     r0, #(1 << 28)
        str     r0, [r5, #CLK_RESET_SCLK_BURST]
        str     r0, [r5, #CLK_RESET_CCLK_BURST]
@@ -537,21 +548,11 @@ tegra3_cpu_clk32k:
 #endif
 
        /* disable PLLM via PMC in LP1 */
-       ldr     r0, [r4, #PMC_CTRL]
-       tst     r0, #PMC_CTRL_SIDE_EFFECT_LP0
-       bne     enable_pllm_lp0
-       /* disable PLLM via PMC in LP0 and LP1 states */
        ldr     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
        bic     r0, r0, #(1<<12)
        str     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
        b       powerdown_pll_pcx
 
-enable_pllm_lp0:
-       /* enable PLLM via PMC in LP0 */
-       ldr     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
-       orr     r0, r0, #((1<<12) | (1 << 11))
-       str     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
-
 powerdown_pll_pcx:
        /* disable PLLP, PLLA, PLLC, and PLLX in LP0 and LP1 states */
        ldr     r0, [r4, #PMC_CTRL]