ARM: tegra: pinmux: Fix GMA,SDIO1,SDIO3 pad config
Pavan Kunapuli [Wed, 3 Jul 2013 14:16:05 +0000 (07:16 -0700)]
Fixed the offsets for different fields for the SDIO1, SDIO3, GMA
pad groups in T124 pinmux tables

Change-Id: Ia4d9fd13bcf913d8375eea6fa34588edc0cd1952
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/244771
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

arch/arm/mach-tegra/pinmux-t12-tables.c

index 4c4cbb4..e6deb6d 100644 (file)
@@ -90,16 +90,19 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
        DEFAULT_DRIVE_PINGROUP(DAP3,            0x898),
        DEFAULT_DRIVE_PINGROUP(DAP4,            0x89c),
        DEFAULT_DRIVE_PINGROUP(DBG,             0x8a0),
-       DEFAULT_DRIVE_PINGROUP(SDIO3,           0x8b0),
+       SET_DRIVE_PINGROUP(SDIO3,               0x8b0,  12,     0x7F,   20,
+               0x7F,   28,     0x3,    30,     0x3),
        DEFAULT_DRIVE_PINGROUP(SPI,             0x8b4),
        DEFAULT_DRIVE_PINGROUP(UAA,             0x8b8),
        DEFAULT_DRIVE_PINGROUP(UAB,             0x8bc),
        DEFAULT_DRIVE_PINGROUP(UART2,           0x8c0),
        DEFAULT_DRIVE_PINGROUP(UART3,           0x8c4),
-       DEFAULT_DRIVE_PINGROUP(SDIO1,           0x8ec),
+       SET_DRIVE_PINGROUP(SDIO1,               0x8ec,  12,     0x7F,   20,
+               0x7F,   28,     0x3,    30,     0x3),
        DEFAULT_DRIVE_PINGROUP(CRT,             0x8f8),
        DEFAULT_DRIVE_PINGROUP(DDC,             0x8fc),
-       DEFAULT_DRIVE_PINGROUP(GMA,             0x900),
+       SET_DRIVE_PINGROUP(GMA,                 0x900,  14,     0x1F,   20,
+               0x1F,   28,     0x3,    30,     0x3),
        DEFAULT_DRIVE_PINGROUP(GME,             0x910),
        DEFAULT_DRIVE_PINGROUP(GMF,             0x914),
        DEFAULT_DRIVE_PINGROUP(GMG,             0x918),