ARM: tegra: Add Tegra11x power partitions
Scott Williams [Wed, 25 Jan 2012 20:17:45 +0000 (12:17 -0800)]
Change-Id: I156890916b0cd6d1483368cb004f56fc807cd605
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/77171
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
Tested-by: Mark Stadler <mastadler@nvidia.com>

Rebase-Id: Rc4074ec06c9dd48d2affe4a364c28c0f65f5d3b9

arch/arm/mach-tegra/include/mach/powergate.h
arch/arm/mach-tegra/powergate.c

index 8d0db3c..6cd7f69 100644 (file)
 #ifndef _MACH_TEGRA_POWERGATE_H_
 #define _MACH_TEGRA_POWERGATE_H_
 
-#define TEGRA_POWERGATE_CPU    0
-#define TEGRA_POWERGATE_CPU0   TEGRA_POWERGATE_CPU
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
+#define TEGRA_POWERGATE_CPU0   0
+#else
+#define TEGRA_POWERGATE_CRAIL  0
+#endif
 #define TEGRA_POWERGATE_3D     1
 #define TEGRA_POWERGATE_3D0    TEGRA_POWERGATE_3D
 #define TEGRA_POWERGATE_VENC   2
 #define TEGRA_POWERGATE_CPU3   11
 #define TEGRA_POWERGATE_CELP   12
 #define TEGRA_POWERGATE_3D1    13
+#if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
+#define TEGRA_POWERGATE_CPU0   14
+#endif
+#define TEGRA_POWERGATE_C0NC   15
+#define TEGRA_POWERGATE_C1NC   16
+#define TEGRA_POWERGATE_DISA   18
+#define TEGRA_POWERGATE_DISB   19
+#define TEGRA_POWERGATE_XUSBA  20
+#define TEGRA_POWERGATE_XUSBB  21
+#define TEGRA_POWERGATE_XUSBC  22
+
+#define TEGRA_POWERGATE_CPU    TEGRA_POWERGATE_CPU0
 
 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
 #define TEGRA_NUM_POWERGATE    7
 #define TEGRA_CPU_POWERGATE_ID(cpu)    (TEGRA_POWERGATE_CPU)
 #define TEGRA_IS_CPU_POWERGATE_ID(id)  ((id) == TEGRA_POWERGATE_CPU)
 #else
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC)
 #define TEGRA_NUM_POWERGATE    14
+#else
+#define TEGRA_NUM_POWERGATE    23
+#endif
 #define TEGRA_CPU_POWERGATE_ID(cpu)    ((cpu == 0) ? TEGRA_POWERGATE_CPU0 : \
                                                (cpu + TEGRA_POWERGATE_CPU1 - 1))
 #define TEGRA_IS_CPU_POWERGATE_ID(id)  (((id) == TEGRA_POWERGATE_CPU0) || \
index 15fed8e..d976af6 100644 (file)
@@ -129,6 +129,7 @@ static struct powergate_partition powergate_partition_info[TEGRA_NUM_POWERGATE]
        [TEGRA_POWERGATE_3D]    = { "3d0",
                                                {MC_CLIENT_NV, MC_CLIENT_LAST},
                                                {{"3d", CLK_AND_RST} }, },
+#ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
        [TEGRA_POWERGATE_PCIE]  = { "pcie",
                                                {MC_CLIENT_AFI, MC_CLIENT_LAST},
                                                {{"afi", CLK_AND_RST},
@@ -137,15 +138,16 @@ static struct powergate_partition powergate_partition_info[TEGRA_NUM_POWERGATE]
                                                {"cml0", CLK_ONLY},
 #endif
                                                {"pciex", RST_ONLY} }, },
+#endif
        [TEGRA_POWERGATE_VDEC]  = { "vde",
                                                {MC_CLIENT_VDE, MC_CLIENT_LAST},
                                                {{"vde", CLK_AND_RST} }, },
        [TEGRA_POWERGATE_MPE]   = { "mpe",
 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
-                                       {MC_CLIENT_MPE, MC_CLIENT_LAST},
+                                               {MC_CLIENT_MPE, MC_CLIENT_LAST},
 #else
-                                       {MC_CLIENT_MPEA, MC_CLIENT_MPEB,
-                                        MC_CLIENT_MPEC, MC_CLIENT_LAST},
+                                               {MC_CLIENT_MPEA, MC_CLIENT_MPEB,
+                                                MC_CLIENT_MPEC, MC_CLIENT_LAST},
 #endif
                                                {{"mpe", CLK_AND_RST} }, },
        [TEGRA_POWERGATE_VENC]  = { "ve",
@@ -158,14 +160,18 @@ static struct powergate_partition powergate_partition_info[TEGRA_NUM_POWERGATE]
        [TEGRA_POWERGATE_CPU2]  = { "cpu2",     {MC_CLIENT_LAST}, },
        [TEGRA_POWERGATE_CPU3]  = { "cpu3",     {MC_CLIENT_LAST}, },
        [TEGRA_POWERGATE_CELP]  = { "celp",     {MC_CLIENT_LAST}, },
+#ifdef CONFIG_ARCH_TEGRA_HAS_SATA
        [TEGRA_POWERGATE_SATA]  = { "sata",     {MC_CLIENT_SATA, MC_CLIENT_LAST},
                                                {{"sata", CLK_AND_RST},
                                                {"sata_oob", CLK_AND_RST},
                                                {"cml1", CLK_ONLY},
                                                {"sata_cold", RST_ONLY} }, },
+#endif
+#ifdef CONFIG_ARCH_TEGRA_HAS_DUAL_3D
        [TEGRA_POWERGATE_3D1]   = { "3d1",
                                                {MC_CLIENT_NV2, MC_CLIENT_LAST},
                                                {{"3d2", CLK_AND_RST} }, },
+#endif
        [TEGRA_POWERGATE_HEG]   = { "heg",
                                                {MC_CLIENT_G2, MC_CLIENT_EPP,
                                                        MC_CLIENT_HC,
@@ -175,6 +181,17 @@ static struct powergate_partition powergate_partition_info[TEGRA_NUM_POWERGATE]
                                                {"host1x", CLK_AND_RST},
                                                {"3d", RST_ONLY} }, },
 #endif
+#if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
+       [TEGRA_POWERGATE_CRAIL] = { "crail",    {MC_CLIENT_LAST}, },
+       [TEGRA_POWERGATE_C0NC]  = { "c0nc",     {MC_CLIENT_LAST}, },
+       [TEGRA_POWERGATE_C1NC]  = { "c1nc",     {MC_CLIENT_LAST}, },
+       [TEGRA_POWERGATE_DISA]  = { "disa",     {MC_CLIENT_LAST}, },
+       [TEGRA_POWERGATE_DISB]  = { "disb",     {MC_CLIENT_LAST}, },
+       [TEGRA_POWERGATE_XUSBA] = { "xusba",    {MC_CLIENT_LAST}, },
+       [TEGRA_POWERGATE_XUSBB] = { "xusbb",    {MC_CLIENT_LAST}, },
+       [TEGRA_POWERGATE_XUSBC] = { "xusbc",    {MC_CLIENT_LAST}, },
+#endif
+
 };
 
 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);