mmc: sdhci: set "clk" back to zero before configuring clock rate
Vishal Singh [Wed, 10 Apr 2013 09:23:08 +0000 (14:23 +0530)]
When we have clock gating disabled, as in the case of SDIO card
being used for WiFi, SDHCI_CLOCK_CONTROL register doesn't get
updated with intended value.
This is because the variable "clk", which is used to store the
register value, contains old value (corresponding to init
frequency of 400 KHz).
Setting this to zero so that clock rates can be configured
correctly.

Bug 1246186.
Bug 1256237.

Change-Id: I3f742afdf8aec76ffdbf3601ec42b66a9b22390a
Signed-off-by: Vishal Singh <vissingh@nvidia.com>
Reviewed-on: http://git-master/r/218171
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

drivers/mmc/host/sdhci.c

index 09753ef..7961a28 100644 (file)
@@ -1138,6 +1138,7 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
                clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
                clk &= ~SDHCI_CLOCK_CARD_EN;
                sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+               clk = 0;
        }
        sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);