ARM: tegra: pinmux: Fix GME, AT5 drive pinmux
Chaitanya Bandi [Thu, 29 Aug 2013 10:20:57 +0000 (15:20 +0530)]
Fixed the definitions of GME, AT5 drive pinmux
registers.

Bug 1347466

Change-Id: If30197a6cec9d7cb543c65619680d279fc99c549
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/267904
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arch/arm/mach-tegra/pinmux-t12-tables.c

index 90dd2d6..dd9f1fb 100644 (file)
@@ -81,7 +81,8 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
        DEFAULT_DRIVE_PINGROUP(AT2,             0x874),
        DEFAULT_DRIVE_PINGROUP(AT3,             0x878),
        DEFAULT_DRIVE_PINGROUP(AT4,             0x87c),
-       DEFAULT_DRIVE_PINGROUP(AT5,             0x880),
+       SET_DRIVE_PINGROUP(AT5,         0x880,  14,     0x1f,   19,     0x1f,
+       28,     0x3,    30,     0x3),
        DEFAULT_DRIVE_PINGROUP(CDEV1,           0x884),
        DEFAULT_DRIVE_PINGROUP(CDEV2,           0x888),
        DEFAULT_DRIVE_PINGROUP(CSUS,            0x88c),
@@ -103,7 +104,8 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
        DEFAULT_DRIVE_PINGROUP(DDC,             0x8fc),
        SET_DRIVE_PINGROUP(GMA,                 0x900,  14,     0x1F,   20,
                0x1F,   28,     0x3,    30,     0x3),
-       DEFAULT_DRIVE_PINGROUP(GME,             0x910),
+       SET_DRIVE_PINGROUP(GME,         0x910,  14,     0x1f,   19,     0x1f,
+       28,     0x3,    30,     0x3),
        DEFAULT_DRIVE_PINGROUP(GMF,             0x914),
        DEFAULT_DRIVE_PINGROUP(GMG,             0x918),
        DEFAULT_DRIVE_PINGROUP(GMH,             0x91c),