ARM: tegra: build edp table with volt-temp constraints
Diwakar Tundlam [Fri, 12 Apr 2013 00:28:54 +0000 (17:28 -0700)]
Some chips must be constrained to run at a reduced maximum voltage
above certain temperature threshold. Added code for this constraint be
configured on a per SKU basis.

Bug 1270003
Bug 1270570

Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>

Change-Id: Ic2e6f9406712d276ab9af92f89e98bd92972a5f6
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/218723
(cherry picked from commit 38d3ebb18f43d47584d7cca829a831457afd24f5)
Reviewed-on: http://git-master/r/219076
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

arch/arm/mach-tegra/edp.c
arch/arm/mach-tegra/include/mach/edp.h

index 1e96846..2558e52 100644 (file)
@@ -414,6 +414,7 @@ static struct tegra_edp_cpu_leakage_params leakage_params[] = {
                           {   15618709,   -4576116,   158401,  -1538, },
                         },
                 },
+               .volt_temp_cap = { 70, 1240 },
        },
        {
                .cpu_speedo_id      = 1, /* A01P+ CPU */
@@ -446,6 +447,7 @@ static struct tegra_edp_cpu_leakage_params leakage_params[] = {
                         },
                 },
                .safety_cap = { 1810500, 1810500, 1606500, 1606500 },
+               .volt_temp_cap = { 70, 1240 },
        },
        {
                .cpu_speedo_id      = 2, /* A01P+ fast CPU */
@@ -478,6 +480,7 @@ static struct tegra_edp_cpu_leakage_params leakage_params[] = {
                         },
                 },
                .safety_cap = { 1912500, 1912500, 1912500, 1912500 },
+               .volt_temp_cap = { 70, 1240 },
        },
 };
 #endif
@@ -508,7 +511,8 @@ static inline s64 edp_pow(s64 val, int pwr)
  * temp_C - always valid
  * power_mW - valid or -1 (infinite)
  */
-unsigned int edp_calculate_maxf(struct tegra_edp_cpu_leakage_params *params,
+static unsigned int edp_calculate_maxf(
+                               struct tegra_edp_cpu_leakage_params *params,
                                int temp_C, int power_mW,
                                int iddq_mA,
                                int n_cores_idx)
@@ -523,6 +527,11 @@ unsigned int edp_calculate_maxf(struct tegra_edp_cpu_leakage_params *params,
                freq_KHz = freq_voltage_lut[f].freq / 1000;
                voltage_mV = freq_voltage_lut[f].voltage_mV;
 
+               /* Constrain Volt-Temp. Eg. at Tj >= 70C, no VDD_CPU > 1.24V */
+               if (temp_C >= params->volt_temp_cap.temperature &&
+                   voltage_mV > params->volt_temp_cap.voltage_limit_mV)
+                       continue;
+
                /* Calculate leakage current */
                leakage_mA = 0;
                for (i = 0; i <= 3; i++) {
@@ -614,7 +623,7 @@ unsigned int tegra_edp_find_maxf(int volt)
 }
 
 
-int edp_find_speedo_idx(int cpu_speedo_id, unsigned int *cpu_speedo_idx)
+static int edp_find_speedo_idx(int cpu_speedo_id, unsigned int *cpu_speedo_idx)
 {
        int i;
 
index ab9db4c..60e4e6b 100644 (file)
@@ -39,12 +39,18 @@ struct tegra_edp_limits {
        unsigned int freq_limits[4];
 };
 
+struct tegra_edp_voltage_temp_constraint {
+       int temperature;
+       unsigned int voltage_limit_mV;
+};
+
 struct tegra_edp_cpu_leakage_params {
        int cpu_speedo_id;
        int dyn_consts_n[4];     /* pre-multiplied by 1,000,000 */
        int leakage_consts_n[4];         /* pre-multiplied by 1,000,000 */
        int leakage_consts_ijk[4][4][4]; /* pre-multiplied by 100,000 */
        unsigned int safety_cap[4];
+       struct tegra_edp_voltage_temp_constraint volt_temp_cap;
 };
 
 struct tegra_edp_freq_voltage_table {