arm: tegra: power: fix dynamic VDD_CPU EDP capping granularity
Diwakar Tundlam [Tue, 2 Oct 2012 23:54:39 +0000 (16:54 -0700)]
Changed freq-step to ensure EDP freq caps line up with actual cpufreqs
Also since min-cpufreq changes after bootup, don't use min, use 0.

Change-Id: I57498b719b06f7dd3bade5b2038277c2564c69cc
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/141055
(cherry picked from commit 37d92240720f40c0528188ec4409ac5055397e4b)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146678
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R0b740fe222bf61eb2aadb5356df878770414b3b2

arch/arm/mach-tegra/edp.c

index 99bddd3..10c1932 100644 (file)
@@ -31,7 +31,7 @@
 #include "clock.h"
 #include "cpu-tegra.h"
 
-#define FREQ_STEP 10000000
+#define FREQ_STEP 12750000
 #define OVERRIDE_DEFAULT 6000
 
 static struct tegra_edp_limits *edp_limits;
@@ -523,7 +523,7 @@ static int edp_relate_freq_voltage(struct clk *clk_cpu_g,
        unsigned int i, j, freq;
        int voltage_mV;
 
-       for (i = 0, j = 0, freq = clk_get_min_rate(clk_cpu_g);
+       for (i = 0, j = 0, freq = 0;
                 i < freq_voltage_lut_size;
                 i++, freq += FREQ_STEP) {
 
@@ -581,7 +581,7 @@ int init_cpu_edp_limits_calculated(int cpu_speedo_id)
                                GFP_KERNEL);
        BUG_ON(!edp_calculated_limits);
 
-       cpu_g_minf = clk_get_min_rate(clk_cpu_g);
+       cpu_g_minf = 0;
        cpu_g_maxf = clk_get_max_rate(clk_cpu_g);
        freq_voltage_lut_size = (cpu_g_maxf - cpu_g_minf) / FREQ_STEP + 1;
        freq_voltage_lut =