arm: tegra: pismo: addition of board support files
Bibek Basu [Wed, 26 Dec 2012 09:26:50 +0000 (14:26 +0530)]
Addition of board support files for T114 pismo platform

Bug 983268

Change-Id: I7e2695a092501d8c8a772ebc8010e8d941689c63
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/174253
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

14 files changed:
arch/arm/mach-tegra/Kconfig
arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/board-dalmore-sensors.c
arch/arm/mach-tegra/board-pismo-memory.c [new file with mode: 0644]
arch/arm/mach-tegra/board-pismo-panel.c [new file with mode: 0644]
arch/arm/mach-tegra/board-pismo-pinmux-t11x.h [new file with mode: 0644]
arch/arm/mach-tegra/board-pismo-pinmux.c [new file with mode: 0644]
arch/arm/mach-tegra/board-pismo-power.c [new file with mode: 0644]
arch/arm/mach-tegra/board-pismo-powermon.c [new file with mode: 0644]
arch/arm/mach-tegra/board-pismo-sdhci.c [new file with mode: 0644]
arch/arm/mach-tegra/board-pismo-sensors.c [new file with mode: 0644]
arch/arm/mach-tegra/board-pismo.c [new file with mode: 0644]
arch/arm/mach-tegra/board-pismo.h [new file with mode: 0644]
arch/arm/mach-tegra/tegra-board-id.h

index 6ccd218..46f391b 100644 (file)
@@ -212,6 +212,14 @@ config MACH_DALMORE
        help
          Support for NVIDIA DALMORE development platform
 
+config MACH_PISMO
+       bool "Pismo board"
+       depends on ARCH_TEGRA_11x_SOC
+       select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
+       select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
+       help
+         Support for NVIDIA PISMO development platform
+
 config MACH_TEGRA_PLUTO
        bool "Pluto board"
        depends on ARCH_TEGRA_11x_SOC
index 128c973..7d9f6c1 100644 (file)
@@ -175,6 +175,15 @@ obj-${CONFIG_MACH_DALMORE}              += panel-a-1080p-11-6.o
 obj-${CONFIG_MACH_DALMORE}              += panel-p-wuxga-10-1.o
 obj-${CONFIG_MACH_DALMORE}              += panel-s-wqxga-10-1.o
 
+obj-${CONFIG_MACH_PISMO}                += board-pismo.o
+obj-${CONFIG_MACH_PISMO}                += board-pismo-memory.o
+obj-${CONFIG_MACH_PISMO}                += board-pismo-pinmux.o
+obj-${CONFIG_MACH_PISMO}                += board-pismo-power.o
+obj-${CONFIG_MACH_PISMO}                += board-pismo-powermon.o
+obj-${CONFIG_MACH_PISMO}                += board-pismo-sdhci.o
+obj-${CONFIG_MACH_PISMO}                += board-pismo-panel.o
+obj-${CONFIG_MACH_PISMO}                += board-pismo-sensors.o
+
 obj-${CONFIG_MACH_TEGRA_PLUTO}          += board-pluto.o
 obj-${CONFIG_MACH_TEGRA_PLUTO}          += board-pluto-memory.o
 obj-${CONFIG_MACH_TEGRA_PLUTO}          += board-pluto-pinmux.o
index b1fb99b..c6d682a 100644 (file)
@@ -320,7 +320,7 @@ static struct imx091_platform_data imx091_pdata = {
        .power_off              = dalmore_imx091_power_off,
 };
 
-struct sbs_platform_data sbs_pdata = {
+static struct sbs_platform_data sbs_pdata = {
        .poll_retry_count = 100,
        .i2c_retry_count = 2,
 };
diff --git a/arch/arm/mach-tegra/board-pismo-memory.c b/arch/arm/mach-tegra/board-pismo-memory.c
new file mode 100644 (file)
index 0000000..492d769
--- /dev/null
@@ -0,0 +1,1621 @@
+/*
+ * Copyright (C) 2012 NVIDIA, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_data/tegra_emc.h>
+
+#include "board.h"
+#include "board-pismo.h"
+
+#include "tegra-board-id.h"
+#include "tegra11_emc.h"
+#include "fuse.h"
+#include "devices.h"
+
+static struct tegra11_emc_table e1611_h5tc4g63mfr_pba_table[] = {
+       {
+               0x41,       /* Rev 4.0.3 */
+               12750,      /* SDRAM frequency */
+               900,       /* min voltage */
+               "pll_p",    /* clock source id */
+               0x4000003e, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000000, /* EMC_RC */
+                       0x00000003, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000000, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000005, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000060, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000005, /* EMC_TXSR */
+                       0x00000005, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000001, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000064, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00060000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc084, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x800001c6, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x40040001, /* MC_EMEM_ARB_CFG */
+                       0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x77e30303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00060000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00060000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x0000000e, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               57820,      /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               20400,      /* SDRAM frequency */
+               900,       /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000026, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000000, /* EMC_RC */
+                       0x00000005, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000000, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000005, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x0000009a, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000006, /* EMC_TXSR */
+                       0x00000006, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000001, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x000000a0, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00060000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc084, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x40020001, /* MC_EMEM_ARB_CFG */
+                       0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x76230303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00060000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00060000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000014, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               35610,      /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               40800,      /* SDRAM frequency */
+               900,       /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000012, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000001, /* EMC_RC */
+                       0x0000000a, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000001, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000005, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000134, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000008, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x0000000c, /* EMC_TXSR */
+                       0x0000000c, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000002, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x0000013f, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00060000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc084, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000370, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0xa0000001, /* MC_EMEM_ARB_CFG */
+                       0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x74a30303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00060000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00060000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x0000002a, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               20850,      /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               68000,      /* SDRAM frequency */
+               900,       /* min voltage */
+               "pll_p",    /* clock source id */
+               0x4000000a, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000003, /* EMC_RC */
+                       0x00000011, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000002, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000005, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000c, /* EMC_RDV_MASK */
+                       0x00000202, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x0000000f, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000013, /* EMC_TXSR */
+                       0x00000013, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000003, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000213, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00060000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc084, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x00000001, /* MC_EMEM_ARB_CFG */
+                       0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x74230403, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00060000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000a, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000c, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00060000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000a, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000c, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000046, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               10720,      /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               102000,     /* SDRAM frequency */
+               900,       /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000006, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000004, /* EMC_RC */
+                       0x0000001a, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000003, /* EMC_RAS */
+                       0x00000001, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000001, /* EMC_RD_RCD */
+                       0x00000001, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000005, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000c, /* EMC_RDV_MASK */
+                       0x00000303, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000018, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x0000001c, /* EMC_TXSR */
+                       0x0000001c, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000005, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x0000031c, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00060000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc084, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000714, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x08000001, /* MC_EMEM_ARB_CFG */
+                       0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
+                       0x73c30504, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00060000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000a, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000c, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00060000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000a, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000c, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000068, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               6890,       /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               204000,     /* SDRAM frequency */
+               1000,       /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000002, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000009, /* EMC_RC */
+                       0x00000035, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000007, /* EMC_RAS */
+                       0x00000002, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000002, /* EMC_RD_RCD */
+                       0x00000002, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000607, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000032, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000038, /* EMC_TXSR */
+                       0x00000038, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000009, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000638, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x000000a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc084, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x05057404, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000001f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x01000003, /* MC_EMEM_ARB_CFG */
+                       0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
+                       0x73840a06, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x000000d0, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               3420,       /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               408000,     /* SDRAM frequency */
+               1100,       /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000000, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000012, /* EMC_RC */
+                       0x00000069, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x0000000d, /* EMC_RAS */
+                       0x00000004, /* EMC_RP */
+                       0x00000005, /* EMC_R2W */
+                       0x00000009, /* EMC_W2R */
+                       0x00000002, /* EMC_R2P */
+                       0x0000000c, /* EMC_W2P */
+                       0x00000004, /* EMC_RD_RCD */
+                       0x00000004, /* EMC_WR_RCD */
+                       0x00000002, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000004, /* EMC_WDV */
+                       0x00000004, /* EMC_WDV_MASK */
+                       0x00000007, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000e, /* EMC_RDV_MASK */
+                       0x00000c2f, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000001, /* EMC_PDEX2WR */
+                       0x00000008, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000066, /* EMC_AR2PDEN */
+                       0x00000011, /* EMC_RW2PDEN */
+                       0x0000006f, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000011, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000c70, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000ba88, /* EMC_FBIO_CFG5 */
+                       0x002c0080, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00030000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0003033d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc084, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x0158000c, /* EMC_MRS_WAIT_CNT */
+                       0x0158000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x07070707, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000404, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80001944, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x02000006, /* MC_EMEM_ARB_CFG */
+                       0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+                       0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06040202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
+                       0x7547130b, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00030000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000e, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00018000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00008000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00008000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00008000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00018000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00018000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00018000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00030000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000e, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00018000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00008000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00008000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00008000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00018000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00018000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00018000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x000000d1, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x73200006, /* EMC_CFG */
+               0x80000731, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               1750,       /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               480000,     /* SDRAM frequency */
+               1100,       /* min voltage */
+               "pll_m",    /* clock source id */
+               0x80000000, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000017, /* EMC_RC */
+                       0x00000082, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000010, /* EMC_RAS */
+                       0x00000005, /* EMC_RP */
+                       0x00000005, /* EMC_R2W */
+                       0x00000009, /* EMC_W2R */
+                       0x00000002, /* EMC_R2P */
+                       0x0000000d, /* EMC_W2P */
+                       0x00000005, /* EMC_RD_RCD */
+                       0x00000005, /* EMC_WR_RCD */
+                       0x00000002, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000004, /* EMC_WDV */
+                       0x00000004, /* EMC_WDV_MASK */
+                       0x00000007, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000e, /* EMC_RDV_MASK */
+                       0x00000f23, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000003c8, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x0000000b, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x0000007f, /* EMC_AR2PDEN */
+                       0x00000012, /* EMC_RW2PDEN */
+                       0x00000089, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000015, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000005, /* EMC_TCLKSTABLE */
+                       0x00000006, /* EMC_TCLKSTOP */
+                       0x00000f64, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000ba88, /* EMC_FBIO_CFG5 */
+                       0xf0140091, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS4 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS5 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS6 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0003033d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc084, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x07077704, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x013f000c, /* EMC_MRS_WAIT_CNT */
+                       0x013f000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000808, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80001f05, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x09000007, /* MC_EMEM_ARB_CFG */
+                       0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RP */
+                       0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06040202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000f080c, /* MC_EMEM_ARB_DA_COVERS */
+                       0x7448170d, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000006, /* EMC_EINPUT_DURATION */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000e, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x0000400b, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000400b, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000006, /* EMC_EINPUT_DURATION */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000e, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x0000400b, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000400b, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x000000f6, /* MC_PTSA_GRANT_DECREMENT */
+                       0x000f000f, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x000f0010, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00120014, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00140014, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x001a0014, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x0000001a, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x001a001a, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00b40055, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00b400b4, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x73200006, /* EMC_CFG */
+               0x80000931, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               1750,       /* expected dvfs latency (ns) */
+       },
+};
+
+static struct tegra11_emc_pdata e1611_h5tc4g63mfr_pba_pdata = {
+       .description = "e1611_h5tc4g63mfr_pba",
+       .tables = e1611_h5tc4g63mfr_pba_table,
+       .num_tables = ARRAY_SIZE(e1611_h5tc4g63mfr_pba_table),
+};
+
+static struct tegra11_emc_pdata *pismo_get_emc_data(void)
+{
+
+       /* load T40T Table */
+       return &e1611_h5tc4g63mfr_pba_pdata;
+}
+
+int __init pismo_emc_init(void)
+{
+       tegra_emc_device.dev.platform_data = pismo_get_emc_data();
+       platform_device_register(&tegra_emc_device);
+       tegra11_emc_init();
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-pismo-panel.c b/arch/arm/mach-tegra/board-pismo-panel.c
new file mode 100644 (file)
index 0000000..4be4e98
--- /dev/null
@@ -0,0 +1,490 @@
+/*
+ * arch/arm/mach-tegra/board-pismo-panel.c
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/ioport.h>
+#include <linux/fb.h>
+#include <linux/nvmap.h>
+#include <linux/nvhost.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/tegra_pwm_bl.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pwm_backlight.h>
+
+#include <mach/irqs.h>
+#include <mach/dc.h>
+
+#include "board.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "board-panel.h"
+#include "common.h"
+#include "iomap.h"
+#include "tegra11_host1x_devices.h"
+
+struct platform_device * __init pismo_host1x_init(void)
+{
+       struct platform_device *pdev = NULL;
+
+#ifdef CONFIG_TEGRA_GRHOST
+       pdev = tegra11_register_host1x_devices();
+       if (!pdev) {
+               pr_err("host1x devices registration failed\n");
+               return NULL;
+       }
+#endif
+       return pdev;
+}
+
+#ifdef CONFIG_TEGRA_DC
+
+/* HDMI Hotplug detection pin */
+#define pismo_hdmi_hpd TEGRA_GPIO_PN7
+
+static struct regulator *pismo_hdmi_reg;
+static struct regulator *pismo_hdmi_pll;
+static struct regulator *pismo_hdmi_vddio;
+
+static struct resource pismo_disp1_resources[] = {
+       {
+               .name   = "irq",
+               .start  = INT_DISPLAY_GENERAL,
+               .end    = INT_DISPLAY_GENERAL,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               .name   = "regs",
+               .start  = TEGRA_DISPLAY_BASE,
+               .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "fbmem",
+               .start  = 0, /* Filled in by pismo_panel_init() */
+               .end    = 0, /* Filled in by pismo_panel_init() */
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "ganged_dsia_regs",
+               .start  = 0, /* Filled in the panel file by init_resources() */
+               .end    = 0, /* Filled in the panel file by init_resources() */
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "ganged_dsib_regs",
+               .start  = 0, /* Filled in the panel file by init_resources() */
+               .end    = 0, /* Filled in the panel file by init_resources() */
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "dsi_regs",
+               .start  = 0, /* Filled in the panel file by init_resources() */
+               .end    = 0, /* Filled in the panel file by init_resources() */
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "mipi_cal",
+               .start  = TEGRA_MIPI_CAL_BASE,
+               .end    = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct resource pismo_disp2_resources[] = {
+       {
+               .name   = "irq",
+               .start  = INT_DISPLAY_B_GENERAL,
+               .end    = INT_DISPLAY_B_GENERAL,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               .name   = "regs",
+               .start  = TEGRA_DISPLAY2_BASE,
+               .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "fbmem",
+               .start  = 0, /* Filled in by pismo_panel_init() */
+               .end    = 0, /* Filled in by pismo_panel_init() */
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "hdmi_regs",
+               .start  = TEGRA_HDMI_BASE,
+               .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+
+static struct tegra_dc_sd_settings sd_settings;
+
+static struct tegra_dc_out pismo_disp1_out = {
+       .type           = TEGRA_DC_OUT_DSI,
+       .sd_settings    = &sd_settings,
+};
+
+static int pismo_hdmi_enable(struct device *dev)
+{
+       int ret;
+       if (!pismo_hdmi_reg) {
+               pismo_hdmi_reg = regulator_get(dev, "avdd_hdmi");
+               if (IS_ERR_OR_NULL(pismo_hdmi_reg)) {
+                       pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
+                       pismo_hdmi_reg = NULL;
+                       return PTR_ERR(pismo_hdmi_reg);
+               }
+       }
+       ret = regulator_enable(pismo_hdmi_reg);
+       if (ret < 0) {
+               pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
+               return ret;
+       }
+       if (!pismo_hdmi_pll) {
+               pismo_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll");
+               if (IS_ERR_OR_NULL(pismo_hdmi_pll)) {
+                       pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
+                       pismo_hdmi_pll = NULL;
+                       regulator_put(pismo_hdmi_reg);
+                       pismo_hdmi_reg = NULL;
+                       return PTR_ERR(pismo_hdmi_pll);
+               }
+       }
+       ret = regulator_enable(pismo_hdmi_pll);
+       if (ret < 0) {
+               pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
+               return ret;
+       }
+       return 0;
+}
+
+static int pismo_hdmi_disable(void)
+{
+       if (pismo_hdmi_reg) {
+               regulator_disable(pismo_hdmi_reg);
+               regulator_put(pismo_hdmi_reg);
+               pismo_hdmi_reg = NULL;
+       }
+
+       if (pismo_hdmi_pll) {
+               regulator_disable(pismo_hdmi_pll);
+               regulator_put(pismo_hdmi_pll);
+               pismo_hdmi_pll = NULL;
+       }
+
+       return 0;
+}
+
+static int pismo_hdmi_postsuspend(void)
+{
+       if (pismo_hdmi_vddio) {
+               regulator_disable(pismo_hdmi_vddio);
+               regulator_put(pismo_hdmi_vddio);
+               pismo_hdmi_vddio = NULL;
+       }
+       return 0;
+}
+
+static int pismo_hdmi_hotplug_init(struct device *dev)
+{
+       if (!pismo_hdmi_vddio) {
+               pismo_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0");
+               if (WARN_ON(IS_ERR(pismo_hdmi_vddio))) {
+                       pr_err("%s: couldn't get regulator vdd_hdmi_5v0: %ld\n",
+                               __func__, PTR_ERR(pismo_hdmi_vddio));
+                               pismo_hdmi_vddio = NULL;
+               } else {
+                       regulator_enable(pismo_hdmi_vddio);
+               }
+       }
+
+       return 0;
+}
+
+static struct tegra_dc_out pismo_disp2_out = {
+       .type           = TEGRA_DC_OUT_HDMI,
+       .flags          = TEGRA_DC_OUT_HOTPLUG_HIGH,
+       .parent_clk     = "pll_d2_out0",
+
+       .dcc_bus        = 3,
+       .hotplug_gpio   = pismo_hdmi_hpd,
+
+       .max_pixclock   = KHZ2PICOS(148500),
+
+       .align          = TEGRA_DC_ALIGN_MSB,
+       .order          = TEGRA_DC_ORDER_RED_BLUE,
+
+       .enable         = pismo_hdmi_enable,
+       .disable        = pismo_hdmi_disable,
+       .postsuspend    = pismo_hdmi_postsuspend,
+       .hotplug_init   = pismo_hdmi_hotplug_init,
+};
+
+static struct tegra_fb_data pismo_disp1_fb_data = {
+       .win            = 0,
+       .bits_per_pixel = 32,
+       .flags          = TEGRA_FB_FLIP_ON_PROBE,
+};
+
+static struct tegra_dc_platform_data pismo_disp1_pdata = {
+       .flags          = TEGRA_DC_FLAG_ENABLED,
+       .default_out    = &pismo_disp1_out,
+       .fb             = &pismo_disp1_fb_data,
+       .emc_clk_rate   = 204000000,
+#ifdef CONFIG_TEGRA_DC_CMU
+       .cmu_enable     = 1,
+#endif
+};
+
+static struct tegra_fb_data pismo_disp2_fb_data = {
+       .win            = 0,
+       .xres           = 1280,
+       .yres           = 720,
+       .bits_per_pixel = 32,
+       .flags          = TEGRA_FB_FLIP_ON_PROBE,
+};
+
+static struct tegra_dc_platform_data pismo_disp2_pdata = {
+       .flags          = TEGRA_DC_FLAG_ENABLED,
+       .default_out    = &pismo_disp2_out,
+       .fb             = &pismo_disp2_fb_data,
+       .emc_clk_rate   = 300000000,
+};
+
+static struct platform_device pismo_disp2_device = {
+       .name           = "tegradc",
+       .id             = 1,
+       .resource       = pismo_disp2_resources,
+       .num_resources  = ARRAY_SIZE(pismo_disp2_resources),
+       .dev = {
+               .platform_data = &pismo_disp2_pdata,
+       },
+};
+
+static struct platform_device pismo_disp1_device = {
+       .name           = "tegradc",
+       .id             = 0,
+       .resource       = pismo_disp1_resources,
+       .num_resources  = ARRAY_SIZE(pismo_disp1_resources),
+       .dev = {
+               .platform_data = &pismo_disp1_pdata,
+       },
+};
+
+static struct nvmap_platform_carveout pismo_carveouts[] = {
+       [0] = {
+               .name           = "iram",
+               .usage_mask     = NVMAP_HEAP_CARVEOUT_IRAM,
+               .base           = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
+               .size           = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
+               .buddy_size     = 0, /* no buddy allocation for IRAM */
+       },
+       [1] = {
+               .name           = "generic-0",
+               .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
+               .base           = 0, /* Filled in by pismo_panel_init() */
+               .size           = 0, /* Filled in by pismo_panel_init() */
+               .buddy_size     = SZ_32K,
+       },
+       [2] = {
+               .name           = "vpr",
+               .usage_mask     = NVMAP_HEAP_CARVEOUT_VPR,
+               .base           = 0, /* Filled in by pismo_panel_init() */
+               .size           = 0, /* Filled in by pismo_panel_init() */
+               .buddy_size     = SZ_32K,
+       },
+};
+
+static struct nvmap_platform_data pismo_nvmap_data = {
+       .carveouts      = pismo_carveouts,
+       .nr_carveouts   = ARRAY_SIZE(pismo_carveouts),
+};
+static struct platform_device pismo_nvmap_device __initdata = {
+       .name   = "tegra-nvmap",
+       .id     = -1,
+       .dev    = {
+               .platform_data = &pismo_nvmap_data,
+       },
+};
+
+static struct tegra_dc_sd_settings pismo_sd_settings = {
+       .enable = 1, /* enabled by default. */
+       .use_auto_pwm = false,
+       .hw_update_delay = 0,
+       .bin_width = -1,
+       .aggressiveness = 5,
+       .use_vid_luma = false,
+       .phase_in_adjustments = 0,
+       .k_limit_enable = true,
+       .k_limit = 200,
+       .sd_window_enable = false,
+       .soft_clipping_enable = true,
+       /* Low soft clipping threshold to compensate for aggressive k_limit */
+       .soft_clipping_threshold = 128,
+       .smooth_k_enable = false,
+       .smooth_k_incr = 64,
+       /* Default video coefficients */
+       .coeff = {5, 9, 2},
+       .fc = {0, 0},
+       /* Immediate backlight changes */
+       .blp = {1024, 255},
+       /* Gammas: R: 2.2 G: 2.2 B: 2.2 */
+       /* Default BL TF */
+       .bltf = {
+                       {
+                               {57, 65, 73, 82},
+                               {92, 103, 114, 125},
+                               {138, 150, 164, 178},
+                               {193, 208, 224, 241},
+                       },
+               },
+       /* Default LUT */
+       .lut = {
+                       {
+                               {255, 255, 255},
+                               {199, 199, 199},
+                               {153, 153, 153},
+                               {116, 116, 116},
+                               {85, 85, 85},
+                               {59, 59, 59},
+                               {36, 36, 36},
+                               {17, 17, 17},
+                               {0, 0, 0},
+                       },
+               },
+       .sd_brightness = &sd_brightness,
+       .use_vpulse2 = true,
+};
+
+static void pismo_panel_select(void)
+{
+       struct tegra_panel *panel = NULL;
+
+       panel = &dsi_a_1080p_11_6;
+       if (panel) {
+               if (panel->init_sd_settings)
+                       panel->init_sd_settings(&pismo_sd_settings);
+
+               if (panel->init_dc_out)
+                       panel->init_dc_out(&pismo_disp1_out);
+
+               if (panel->init_fb_data)
+                       panel->init_fb_data(&pismo_disp1_fb_data);
+
+               if (panel->init_cmu_data)
+                       panel->init_cmu_data(&pismo_disp1_pdata);
+
+               if (panel->set_disp_device)
+                       panel->set_disp_device(&pismo_disp1_device);
+
+               if (panel->init_resources)
+                       panel->init_resources(pismo_disp1_resources,
+                               ARRAY_SIZE(pismo_disp1_resources));
+
+               if (panel->register_bl_dev)
+                       panel->register_bl_dev();
+
+               if (panel->register_i2c_bridge)
+                       panel->register_i2c_bridge();
+       }
+
+}
+int __init pismo_panel_init(void)
+{
+       int err = 0;
+       struct resource __maybe_unused *res;
+       struct platform_device *phost1x;
+
+       sd_settings = pismo_sd_settings;
+
+       pismo_panel_select();
+
+#ifdef CONFIG_TEGRA_NVMAP
+       pismo_carveouts[1].base = tegra_carveout_start;
+       pismo_carveouts[1].size = tegra_carveout_size;
+       pismo_carveouts[2].base = tegra_vpr_start;
+       pismo_carveouts[2].size = tegra_vpr_size;
+
+       err = platform_device_register(&pismo_nvmap_device);
+       if (err) {
+               pr_err("nvmap device registration failed\n");
+               return err;
+       }
+#endif
+
+       phost1x = pismo_host1x_init();
+       if (!phost1x) {
+               pr_err("host1x devices registration failed\n");
+               return -EINVAL;
+       }
+
+       gpio_request(pismo_hdmi_hpd, "hdmi_hpd");
+       gpio_direction_input(pismo_hdmi_hpd);
+
+       res = platform_get_resource_byname(&pismo_disp1_device,
+                                        IORESOURCE_MEM, "fbmem");
+       res->start = tegra_fb_start;
+       res->end = tegra_fb_start + tegra_fb_size - 1;
+
+       /* Copy the bootloader fb to the fb. */
+       __tegra_move_framebuffer(&pismo_nvmap_device,
+               tegra_fb_start, tegra_bootloader_fb_start,
+                       min(tegra_fb_size, tegra_bootloader_fb_size));
+
+       res = platform_get_resource_byname(&pismo_disp2_device,
+                                        IORESOURCE_MEM, "fbmem");
+
+       res->start = tegra_fb2_start;
+       res->end = tegra_fb2_start + tegra_fb2_size - 1;
+
+       pismo_disp1_device.dev.parent = &phost1x->dev;
+       err = platform_device_register(&pismo_disp1_device);
+       if (err) {
+               pr_err("disp1 device registration failed\n");
+               return err;
+       }
+
+       pismo_disp2_device.dev.parent = &phost1x->dev;
+       err = platform_device_register(&pismo_disp2_device);
+       if (err) {
+               pr_err("disp2 device registration failed\n");
+               return err;
+       }
+
+#ifdef CONFIG_TEGRA_NVAVP
+       nvavp_device.dev.parent = &phost1x->dev;
+       err = platform_device_register(&nvavp_device);
+       if (err) {
+               pr_err("nvavp device registration failed\n");
+               return err;
+       }
+#endif
+       return err;
+}
+#else
+int __init pismo_panel_init(void)
+{
+       if (pismo_host1x_init())
+               return 0;
+       else
+               return -EINVAL;
+}
+#endif
diff --git a/arch/arm/mach-tegra/board-pismo-pinmux-t11x.h b/arch/arm/mach-tegra/board-pismo-pinmux-t11x.h
new file mode 100644 (file)
index 0000000..14bf6ad
--- /dev/null
@@ -0,0 +1,283 @@
+/*
+ * arch/arm/mach-tegra/board-pismo-pinmux-t11x.h
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth floor, Boston, MA  02110-1301, USA
+ */
+
+static __initdata struct tegra_pingroup_config pismo_pinmux_common[] = {
+
+       /* EXTPERIPH1 pinmux */
+       DEFAULT_PINMUX(CLK1_OUT,      EXTPERIPH1,  NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2S0 pinmux */
+       DEFAULT_PINMUX(DAP1_DIN,      I2S0,        NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(DAP1_DOUT,     I2S0,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP1_FS,       I2S0,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP1_SCLK,     I2S0,        NORMAL,    NORMAL,   INPUT),
+
+       /* I2S1 pinmux */
+       DEFAULT_PINMUX(DAP2_DIN,      I2S1,        NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(DAP2_DOUT,     I2S1,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP2_FS,       I2S1,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP2_SCLK,     I2S1,        NORMAL,    NORMAL,   INPUT),
+
+       /* I2S3 pinmux */
+       DEFAULT_PINMUX(DAP4_DIN,      I2S3,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP4_DOUT,     I2S3,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP4_FS,       I2S3,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP4_SCLK,     I2S3,        NORMAL,    NORMAL,   INPUT),
+
+       /* CLDVFS pinmux */
+       DEFAULT_PINMUX(DVFS_PWM,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(DVFS_CLK,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+
+       /* ULPI pinmux */
+       DEFAULT_PINMUX(ULPI_CLK,      ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA0,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA1,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA2,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA3,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA4,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA5,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA6,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA7,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DIR,      ULPI,        NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(ULPI_NXT,      ULPI,        NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(ULPI_STP,      ULPI,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2C3 pinmux */
+       I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+       /* VI pinmux */
+       VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+
+       /* VI_ALT1 pinmux */
+       VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+
+       /* VGP4 pinmux */
+       VI_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+
+       /* I2C2 pinmux */
+       I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+       /* UARTD pinmux */
+       DEFAULT_PINMUX(GMI_A16,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(GMI_A17,       UARTD,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(GMI_A18,       UARTD,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(GMI_A19,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* SPI4 pinmux */
+       DEFAULT_PINMUX(GMI_AD5,       SPI4,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_AD6,       SPI4,        PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_AD7,       SPI4,        PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_CS6_N,     SPI4,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_WR_N,      SPI4,        NORMAL,    NORMAL,   INPUT),
+
+       /* PWM1 pinmux */
+       DEFAULT_PINMUX(GMI_AD9,       PWM1,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* SOC pinmux */
+       DEFAULT_PINMUX(GMI_CS1_N,     SOC,         NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(GMI_OE_N,      SOC,         NORMAL,    TRISTATE, INPUT),
+
+       /* EXTPERIPH2 pinmux */
+       DEFAULT_PINMUX(CLK2_OUT,      EXTPERIPH2,  NORMAL,    NORMAL,   OUTPUT),
+
+       /* SDMMC1 pinmux */
+       DEFAULT_PINMUX(SDMMC1_CLK,    SDMMC1,      NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_CMD,    SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT0,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT1,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT2,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT3,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+
+       /* SDMMC3 pinmux */
+       DEFAULT_PINMUX(SDMMC3_CLK,    SDMMC3,      NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CMD,    SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT0,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT1,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT2,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT3,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(KB_COL4,       SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CD_N,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CLK_LB_IN,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+
+       /* SDMMC4 pinmux */
+       DEFAULT_PINMUX(SDMMC4_CLK,    SDMMC4,      NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_CMD,    SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT0,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT1,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT2,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT3,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT4,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT5,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT6,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT7,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+
+       /* BLINK pinmux */
+       DEFAULT_PINMUX(CLK_32K_OUT,   BLINK,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* KBC pinmux */
+       DEFAULT_PINMUX(KB_COL0,       KBC,         PULL_UP,   NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_COL1,       KBC,         PULL_UP,   NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_COL2,       KBC,         PULL_UP,   NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW0,       KBC,         PULL_UP,   NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW1,       KBC,         PULL_UP,   NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW2,       KBC,         PULL_UP,   NORMAL, INPUT),
+
+       /* UARTA pinmux */
+       DEFAULT_PINMUX(KB_ROW10,      UARTA,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(KB_ROW9,       UARTA,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2CPWR pinmux */
+       I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+       /* SYSCLK pinmux */
+       DEFAULT_PINMUX(SYS_CLK_REQ,   SYSCLK,      NORMAL,    NORMAL,   OUTPUT),
+
+       /* RTCK pinmux */
+       DEFAULT_PINMUX(JTAG_RTCK,     RTCK,        NORMAL,    NORMAL, INPUT),
+
+       /* CLK pinmux */
+       DEFAULT_PINMUX(CLK_32K_IN,    CLK,         NORMAL,    TRISTATE, INPUT),
+
+       /* PWRON pinmux */
+       DEFAULT_PINMUX(CORE_PWR_REQ,  PWRON,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* CPU pinmux */
+       DEFAULT_PINMUX(CPU_PWR_REQ,   CPU,         NORMAL,    NORMAL,   OUTPUT),
+
+       /* PMI pinmux */
+       DEFAULT_PINMUX(PWR_INT_N,     PMI,         NORMAL,    TRISTATE, INPUT),
+
+       /* RESET_OUT_N pinmux */
+       DEFAULT_PINMUX(RESET_OUT_N,   RESET_OUT_N, NORMAL,    NORMAL,   OUTPUT),
+
+       /* EXTPERIPH3 pinmux */
+       DEFAULT_PINMUX(CLK3_OUT,      EXTPERIPH3,  NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2C1 pinmux */
+       I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+       /* UARTB pinmux */
+       DEFAULT_PINMUX(UART2_CTS_N,   UARTB,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(UART2_RTS_N,   UARTB,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* IRDA pinmux */
+       DEFAULT_PINMUX(UART2_RXD,     IRDA,        NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(UART2_TXD,     IRDA,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* UARTC pinmux */
+       DEFAULT_PINMUX(UART3_CTS_N,   UARTC,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(UART3_RTS_N,   UARTC,       NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(UART3_RXD,     UARTC,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(UART3_TXD,     UARTC,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* OWR pinmux */
+       DEFAULT_PINMUX(OWR,           OWR,         NORMAL,    NORMAL,   INPUT),
+
+       /* CEC pinmux */
+       CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+       /* I2C4 pinmux */
+       DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+       DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+
+       /* USB pinmux */
+       USB_PINMUX(SPDIF_IN, USB, PULL_UP, NORMAL, INPUT, DISABLE, ENABLE),
+       USB_PINMUX(USB_VBUS_EN0, USB, PULL_UP, NORMAL, INPUT, DISABLE, ENABLE),
+
+       /* nct */
+       DEFAULT_PINMUX(GPIO_X6_AUD,   SPI6,        PULL_UP,   TRISTATE, INPUT),
+};
+
+static __initdata struct tegra_pingroup_config unused_pins_lowpower[] = {
+       DEFAULT_PINMUX(USB_VBUS_EN1,  RSVD3,       PULL_DOWN, TRISTATE, OUTPUT),
+};
+
+static struct gpio_init_pin_info init_gpio_mode_pismo_common[] = {
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX4, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX5, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX6, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX7, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX1, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP1, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP2, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP0, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV0, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV1, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB5, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB6, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB7, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC1, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG0, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG1, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH2, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH4, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH5, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH6, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH7, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG4, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH0, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK0, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK1, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PJ0, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK4, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI6, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PJ3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI5, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI4, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI7, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PC7, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC5, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ5, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ6, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ7, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR4, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR5, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR6, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR7, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PS0, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PEE1, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU0, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU1, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU4, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU5, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU6, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PN7, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK5, true, 1),
+};
diff --git a/arch/arm/mach-tegra/board-pismo-pinmux.c b/arch/arm/mach-tegra/board-pismo-pinmux.c
new file mode 100644 (file)
index 0000000..b0c20b2
--- /dev/null
@@ -0,0 +1,285 @@
+/*
+ * arch/arm/mach-tegra/board-pismo-pinmux.c
+ *
+ * Copyright (C) 2012 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <mach/pinmux.h>
+#include <mach/gpio-tegra.h>
+#include "board.h"
+#include "board-pismo.h"
+#include "devices.h"
+#include "gpio-names.h"
+
+#include <mach/pinmux-t11.h>
+
+#define DEFAULT_DRIVE(_name)                                   \
+       {                                                       \
+               .pingroup = TEGRA_DRIVE_PINGROUP_##_name,       \
+               .hsm = TEGRA_HSM_DISABLE,                       \
+               .schmitt = TEGRA_SCHMITT_ENABLE,                \
+               .drive = TEGRA_DRIVE_DIV_1,                     \
+               .pull_down = TEGRA_PULL_31,                     \
+               .pull_up = TEGRA_PULL_31,                       \
+               .slew_rising = TEGRA_SLEW_SLOWEST,              \
+               .slew_falling = TEGRA_SLEW_SLOWEST,             \
+       }
+/* Setting the drive strength of pins
+ * hsm: Enable High speed mode (ENABLE/DISABLE)
+ * Schimit: Enable/disable schimit (ENABLE/DISABLE)
+ * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
+ * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
+ *                strength code. Value from 0 to 31.
+ * pullup_drive - drive up (rising edge)  - Driver Output Pull-Up drive
+ *                strength code. Value from 0 to 31.
+ * pulldn_slew -  Driver Output Pull-Up slew control code  - 2bit code
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ * pullup_slew -  Driver Output Pull-Down slew control code -
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ */
+#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
+       {                                               \
+               .pingroup = TEGRA_DRIVE_PINGROUP_##_name,   \
+               .hsm = TEGRA_HSM_##_hsm,                    \
+               .schmitt = TEGRA_SCHMITT_##_schmitt,        \
+               .drive = TEGRA_DRIVE_##_drive,              \
+               .pull_down = TEGRA_PULL_##_pulldn_drive,    \
+               .pull_up = TEGRA_PULL_##_pullup_drive,          \
+               .slew_rising = TEGRA_SLEW_##_pulldn_slew,   \
+               .slew_falling = TEGRA_SLEW_##_pullup_slew,      \
+       }
+
+/* Setting the drive strength of pins
+ * hsm: Enable High speed mode (ENABLE/DISABLE)
+ * Schimit: Enable/disable schimit (ENABLE/DISABLE)
+ * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
+ * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
+ *                strength code. Value from 0 to 31.
+ * pullup_drive - drive up (rising edge)  - Driver Output Pull-Up drive
+ *                strength code. Value from 0 to 31.
+ * pulldn_slew -  Driver Output Pull-Up slew control code  - 2bit code
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ * pullup_slew -  Driver Output Pull-Down slew control code -
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ * drive_type - Drive type to be used depending on the resistors.
+ */
+
+#define SET_DRIVE_WITH_TYPE(_name, _hsm, _schmitt, _drive, _pulldn_drive,\
+               _pullup_drive, _pulldn_slew, _pullup_slew, _drive_type) \
+       {                                                               \
+               .pingroup = TEGRA_DRIVE_PINGROUP_##_name,               \
+               .hsm = TEGRA_HSM_##_hsm,                                \
+               .schmitt = TEGRA_SCHMITT_##_schmitt,                    \
+               .drive = TEGRA_DRIVE_##_drive,                          \
+               .pull_down = TEGRA_PULL_##_pulldn_drive,                \
+               .pull_up = TEGRA_PULL_##_pullup_drive,                  \
+               .slew_rising = TEGRA_SLEW_##_pulldn_slew,               \
+               .slew_falling = TEGRA_SLEW_##_pullup_slew,              \
+               .drive_type = TEGRA_DRIVE_TYPE_##_drive_type,           \
+       }
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io)      \
+       {                                                       \
+               .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
+               .func           = TEGRA_MUX_##_mux,             \
+               .pupd           = TEGRA_PUPD_##_pupd,           \
+               .tristate       = TEGRA_TRI_##_tri,             \
+               .io             = TEGRA_PIN_##_io,              \
+               .lock           = TEGRA_PIN_LOCK_DEFAULT,       \
+               .od             = TEGRA_PIN_OD_DEFAULT,         \
+               .ioreset        = TEGRA_PIN_IO_RESET_DEFAULT,   \
+       }
+
+#define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \
+       {                                                       \
+               .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
+               .func           = TEGRA_MUX_##_mux,             \
+               .pupd           = TEGRA_PUPD_##_pupd,           \
+               .tristate       = TEGRA_TRI_##_tri,             \
+               .io             = TEGRA_PIN_##_io,              \
+               .lock           = TEGRA_PIN_LOCK_##_lock,       \
+               .od             = TEGRA_PIN_OD_##_od,           \
+               .ioreset        = TEGRA_PIN_IO_RESET_DEFAULT,   \
+       }
+
+#define DDC_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _rcv_sel) \
+       {                                                       \
+               .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
+               .func           = TEGRA_MUX_##_mux,             \
+               .pupd           = TEGRA_PUPD_##_pupd,           \
+               .tristate       = TEGRA_TRI_##_tri,             \
+               .io             = TEGRA_PIN_##_io,              \
+               .lock           = TEGRA_PIN_LOCK_##_lock,       \
+               .rcv_sel        = TEGRA_PIN_RCV_SEL_##_rcv_sel,         \
+               .ioreset        = TEGRA_PIN_IO_RESET_DEFAULT,   \
+       }
+
+#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
+       {                                                       \
+               .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
+               .func           = TEGRA_MUX_##_mux,             \
+               .pupd           = TEGRA_PUPD_##_pupd,           \
+               .tristate       = TEGRA_TRI_##_tri,             \
+               .io             = TEGRA_PIN_##_io,              \
+               .lock           = TEGRA_PIN_LOCK_##_lock,       \
+               .od             = TEGRA_PIN_OD_DEFAULT,         \
+               .ioreset        = TEGRA_PIN_IO_RESET_##_ioreset \
+       }
+
+#define CEC_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od)   \
+       {                                                               \
+               .pingroup   = TEGRA_PINGROUP_##_pingroup,                   \
+               .func       = TEGRA_MUX_##_mux,                             \
+               .pupd       = TEGRA_PUPD_##_pupd,                           \
+               .tristate   = TEGRA_TRI_##_tri,                             \
+               .io         = TEGRA_PIN_##_io,                              \
+               .lock       = TEGRA_PIN_LOCK_##_lock,                       \
+               .od         = TEGRA_PIN_OD_##_od,                           \
+               .ioreset    = TEGRA_PIN_IO_RESET_DEFAULT,                   \
+       }
+
+#define USB_PINMUX CEC_PINMUX
+
+#define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value)   \
+       {                                       \
+               .gpio_nr        = _gpio,        \
+               .is_input       = _is_input,    \
+               .value          = _value,       \
+       }
+
+static __initdata struct tegra_drive_pingroup_config pismo_drive_pinmux[] = {
+       /* DEFAULT_DRIVE(<pin_group>), */
+       /* SDMMC1 */
+       SET_DRIVE(SDIO1, ENABLE, DISABLE, DIV_1, 36, 20, SLOW, SLOW),
+
+       /* SDMMC3 */
+       SET_DRIVE(SDIO3, ENABLE, DISABLE, DIV_1, 22, 36, FASTEST, FASTEST),
+
+       /* SDMMC4 */
+       SET_DRIVE_WITH_TYPE(GMA, ENABLE, DISABLE, DIV_1, 2, 1, FASTEST,
+                                                               FASTEST, 1),
+};
+
+/* Initially setting all used GPIO's to non-TRISTATE */
+static __initdata struct tegra_pingroup_config pismo_pinmux_set_nontristate[] = {
+       DEFAULT_PINMUX(CLK1_REQ,        RSVD3,  PULL_DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_X4_AUD,     RSVD,   PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_X5_AUD,     RSVD,   PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_X6_AUD,     RSVD3,  PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_X7_AUD,     RSVD,   PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_W2_AUD,     RSVD1,  PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_W3_AUD,     SPI6,   PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_X1_AUD,     RSVD3,  PULL_DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_X3_AUD,     RSVD3,  PULL_UP,      NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(DAP3_FS,         I2S2,   PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(DAP3_DIN,        I2S2,   PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(DAP3_DOUT,       I2S2,   PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(DAP3_SCLK,       I2S2,   PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PV0,        RSVD3,  NORMAL,       NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_PV1,        RSVD,   NORMAL,       NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(GPIO_PBB3,       RSVD3,  PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PBB5,       RSVD3,  PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PBB6,       RSVD3,  PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PBB7,       RSVD3,  PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PCC1,       RSVD3,  PULL_DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_PCC2,       RSVD3,  PULL_DOWN,    NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(GMI_AD0,         GMI,    NORMAL,       NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_AD1,         GMI,    NORMAL,       NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_AD10,        GMI,    PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_AD11,        GMI,    PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_AD12,        GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_AD13,        GMI,    PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_AD2,         GMI,    NORMAL,       NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_AD3,         GMI,    NORMAL,       NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_AD8,         GMI,    PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_ADV_N,       GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_CLK,         GMI,    PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_CS0_N,       GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_CS2_N,       GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_CS3_N,       GMI,    PULL_UP,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_CS4_N,       GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_CS7_N,       GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_DQS_P,       GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_IORDY,       GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_WP_N,        GMI,    PULL_UP,      NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(SDMMC1_WP_N,     SPI4,   PULL_UP,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(CLK2_REQ,        RSVD3,  NORMAL,       NORMAL,    OUTPUT),
+
+       DEFAULT_PINMUX(KB_COL3,         KBC,    PULL_UP,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(KB_COL5,         KBC,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(KB_COL6,         KBC,    PULL_UP,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(KB_COL7,         KBC,    PULL_UP,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(KB_ROW3,         KBC,    PULL_DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(KB_ROW4,         KBC,    PULL_DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(KB_ROW6,         KBC,    PULL_DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(KB_ROW7,         KBC,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(KB_ROW8,         KBC,    PULL_UP,      NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(CLK3_REQ,        RSVD3,  NORMAL,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PU4,        RSVD3,  NORMAL,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PU5,        RSVD3,  NORMAL,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_PU6,        RSVD3,  NORMAL,      NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(HDMI_INT,        RSVD,   PULL_DOWN,    NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(GMI_AD9,         PWM1,   NORMAL,    NORMAL,     OUTPUT),
+};
+
+#include "board-pismo-pinmux-t11x.h"
+
+static void __init pismo_gpio_init_configure(void)
+{
+       int len;
+       int i;
+       struct gpio_init_pin_info *pins_info;
+
+       len = ARRAY_SIZE(init_gpio_mode_pismo_common);
+       pins_info = init_gpio_mode_pismo_common;
+
+       for (i = 0; i < len; ++i) {
+               tegra_gpio_init_configure(pins_info->gpio_nr,
+                       pins_info->is_input, pins_info->value);
+               pins_info++;
+       }
+}
+
+int __init pismo_pinmux_init(void)
+{
+       tegra_pinmux_config_table(pismo_pinmux_set_nontristate,
+                               ARRAY_SIZE(pismo_pinmux_set_nontristate));
+       pismo_gpio_init_configure();
+
+       tegra_pinmux_config_table(pismo_pinmux_common,
+                       ARRAY_SIZE(pismo_pinmux_common));
+       tegra_drive_pinmux_config_table(pismo_drive_pinmux,
+                                       ARRAY_SIZE(pismo_drive_pinmux));
+       tegra_pinmux_config_table(unused_pins_lowpower,
+               ARRAY_SIZE(unused_pins_lowpower));
+
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-pismo-power.c b/arch/arm/mach-tegra/board-pismo-power.c
new file mode 100644 (file)
index 0000000..427eb2d
--- /dev/null
@@ -0,0 +1,882 @@
+/*
+ * arch/arm/mach-tegra/board-pismo-power.c
+ *
+ * Copyright (C) 2012 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/i2c.h>
+#include <linux/pda_power.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/io.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/as3720.h>
+#include <linux/gpio.h>
+#include <linux/regulator/userspace-consumer.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/irqs.h>
+#include <mach/edp.h>
+#include <mach/gpio-tegra.h>
+
+#include "pm.h"
+#include "tegra-board-id.h"
+#include "board.h"
+#include "gpio-names.h"
+#include "board-pismo.h"
+#include "tegra_cl_dvfs.h"
+#include "devices.h"
+#include "tegra11_soctherm.h"
+#include "iomap.h"
+
+#define PMC_CTRL               0x0
+#define PMC_CTRL_INTR_LOW      (1 << 17)
+
+static struct regulator_consumer_supply as3720_ldo0_supply[] = {
+       REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
+       REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
+       REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
+       REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
+       REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
+};
+
+static struct regulator_consumer_supply as3720_ldo1_supply[] = {
+       REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
+       REGULATOR_SUPPLY("pwrdet_cam", NULL),
+};
+
+static struct regulator_consumer_supply as3720_ldo2_supply[] = {
+       REGULATOR_SUPPLY("vpp_fuse", NULL),
+};
+
+static struct regulator_consumer_supply as3720_ldo3_supply[] = {
+       REGULATOR_SUPPLY("vdd_rtc", NULL),
+};
+
+static struct regulator_consumer_supply as3720_ldo5_supply[] = {
+       REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
+       REGULATOR_SUPPLY("vdd_als", NULL),
+       REGULATOR_SUPPLY("vdd", "0-004c"),
+       REGULATOR_SUPPLY("vdd", "0-0069"),
+};
+
+static struct regulator_consumer_supply as3720_ldo6_supply[] = {
+       REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
+       REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
+};
+
+static struct regulator_consumer_supply as3720_ldo8_supply[] = {
+       REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
+};
+
+static struct regulator_consumer_supply as3720_sd0_supply[] = {
+       REGULATOR_SUPPLY("vdd_cpu", NULL),
+};
+
+static struct regulator_consumer_supply as3720_sd1_supply[] = {
+       REGULATOR_SUPPLY("vdd_core", NULL),
+};
+
+static struct regulator_consumer_supply as3720_sd2_supply[] = {
+       REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
+       REGULATOR_SUPPLY("vcore_emmc", NULL),
+       REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
+       REGULATOR_SUPPLY("vdd_af_cam1", NULL),
+};
+
+static struct regulator_consumer_supply as3720_sd3_supply[] = {
+       REGULATOR_SUPPLY("vdd_emmc", NULL),
+       REGULATOR_SUPPLY("vddio_sys", NULL),
+       REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
+       REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
+       REGULATOR_SUPPLY("vddio_bb", NULL),
+       REGULATOR_SUPPLY("pwrdet_bb", NULL),
+       REGULATOR_SUPPLY("vddio_uart", NULL),
+       REGULATOR_SUPPLY("pwrdet_uart", NULL),
+       REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
+       REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
+       REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
+       REGULATOR_SUPPLY("avdd_osc", NULL),
+       REGULATOR_SUPPLY("vddio_gmi", NULL),
+       REGULATOR_SUPPLY("pwrdet_nand", NULL),
+       REGULATOR_SUPPLY("vddio_audio", NULL),
+       REGULATOR_SUPPLY("pwrdet_audio", NULL),
+       REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
+       REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
+       REGULATOR_SUPPLY("pwrdet_mipi", NULL),
+       REGULATOR_SUPPLY("vddio_bt_1v8", NULL),
+       REGULATOR_SUPPLY("vddio_wifi_1v8", NULL),
+       REGULATOR_SUPPLY("vdd_gps_1v8", NULL),
+};
+
+static struct regulator_consumer_supply as3720_sd4_supply[] = {
+       REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
+       REGULATOR_SUPPLY("avdd_plle", NULL),
+       REGULATOR_SUPPLY("avdd_pllm", NULL),
+       REGULATOR_SUPPLY("avdd_pllu", NULL),
+       REGULATOR_SUPPLY("avdd_pllx", NULL),
+       REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
+       REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
+       REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
+       REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
+       REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
+       REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
+       REGULATOR_SUPPLY("avddio_usb", NULL),
+};
+
+static struct regulator_consumer_supply as3720_sd5_supply[] = {
+       REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
+       REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
+       REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
+       REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
+       REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
+       REGULATOR_SUPPLY("pwrdet_hv", NULL),
+       REGULATOR_SUPPLY("vdd_bt_3v3", NULL),
+       REGULATOR_SUPPLY("vdd_wifi_3v3", NULL),
+};
+
+static struct regulator_consumer_supply as3720_sd6_supply[] = {
+       REGULATOR_SUPPLY("vddio_ddr", NULL),
+       REGULATOR_SUPPLY("vddio_ddr0", NULL),
+       REGULATOR_SUPPLY("vddio_ddr1", NULL),
+};
+
+static struct regulator_init_data as3720_ldo0 = {
+       .constraints = {
+               .min_uV = 1200000,
+               .max_uV = 1200000,
+               .valid_modes_mask = REGULATOR_MODE_NORMAL
+                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask = REGULATOR_CHANGE_MODE
+                       | REGULATOR_CHANGE_STATUS
+                       | REGULATOR_CHANGE_VOLTAGE,
+               .always_on = false,
+               .boot_on = 1,
+               .apply_uV = 1,
+       },
+       .consumer_supplies = as3720_ldo0_supply,
+       .num_consumer_supplies = ARRAY_SIZE(as3720_ldo0_supply),
+};
+
+static struct regulator_init_data as3720_ldo1 = {
+       .constraints = {
+               .min_uV = 1800000,
+               .max_uV = 1800000,
+               .valid_modes_mask = REGULATOR_MODE_NORMAL
+                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask = REGULATOR_CHANGE_MODE
+                       | REGULATOR_CHANGE_STATUS
+                       | REGULATOR_CHANGE_VOLTAGE,
+               .always_on = true,
+               .boot_on = 1,
+               .apply_uV = 1,
+       },
+       .consumer_supplies = as3720_ldo1_supply,
+       .num_consumer_supplies = ARRAY_SIZE(as3720_ldo1_supply),
+};
+
+static struct regulator_init_data as3720_ldo2 = {
+       .constraints = {
+               .min_uV = 1800000,
+               .max_uV = 1800000,
+               .valid_modes_mask = REGULATOR_MODE_NORMAL
+                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask = REGULATOR_CHANGE_MODE
+                       | REGULATOR_CHANGE_STATUS
+                       | REGULATOR_CHANGE_VOLTAGE,
+               .always_on = false,
+               .boot_on = 1,
+               .apply_uV = 1,
+       },
+       .consumer_supplies = as3720_ldo2_supply,
+       .num_consumer_supplies = ARRAY_SIZE(as3720_ldo2_supply),
+};
+
+static struct regulator_init_data as3720_ldo3 = {
+       .constraints = {
+               .min_uV = 1100000,
+               .max_uV = 1100000,
+               .valid_modes_mask = REGULATOR_MODE_NORMAL
+                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask = REGULATOR_CHANGE_MODE
+                       | REGULATOR_CHANGE_STATUS
+                       | REGULATOR_CHANGE_VOLTAGE,
+               .always_on = true,
+               .boot_on = 1,
+               .apply_uV = 1,
+       },
+       .consumer_supplies = as3720_ldo3_supply,
+       .num_consumer_supplies = ARRAY_SIZE(as3720_ldo3_supply),
+};
+
+static struct regulator_init_data as3720_ldo5 = {
+       .constraints = {
+               .min_uV = 3300000,
+               .max_uV = 3300000,
+               .valid_modes_mask = REGULATOR_MODE_NORMAL
+                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask = REGULATOR_CHANGE_MODE
+                       | REGULATOR_CHANGE_STATUS
+                       | REGULATOR_CHANGE_VOLTAGE,
+               .always_on = true,
+               .boot_on = 1,
+               .apply_uV = 1,
+       },
+       .consumer_supplies = as3720_ldo5_supply,
+       .num_consumer_supplies = ARRAY_SIZE(as3720_ldo5_supply),
+};
+static struct regulator_init_data as3720_ldo6 = {
+       .constraints = {
+               .min_uV = 1800000,
+               .max_uV = 3300000,
+               .valid_modes_mask = REGULATOR_MODE_NORMAL
+                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask = REGULATOR_CHANGE_MODE
+                       | REGULATOR_CHANGE_STATUS
+                       | REGULATOR_CHANGE_VOLTAGE,
+               .always_on = false,
+               .boot_on = 0,
+               .apply_uV = 1,
+       },
+       .consumer_supplies = as3720_ldo6_supply,
+       .num_consumer_supplies = ARRAY_SIZE(as3720_ldo6_supply),
+};
+
+static struct regulator_init_data as3720_ldo8 = {
+       .constraints = {
+               .min_uV = 3300000,
+               .max_uV = 3300000,
+               .valid_modes_mask = REGULATOR_MODE_NORMAL
+                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask = REGULATOR_CHANGE_MODE
+                       | REGULATOR_CHANGE_STATUS
+                       | REGULATOR_CHANGE_VOLTAGE,
+               .always_on = true,
+               .boot_on = 1,
+               .apply_uV = 1,
+       },
+       .consumer_supplies = as3720_ldo8_supply,
+       .num_consumer_supplies = ARRAY_SIZE(as3720_ldo8_supply),
+};
+
+static struct regulator_init_data as3720_sd0 = {
+       .constraints = {
+               .min_uV = 1100000,
+               .max_uV = 1100000,
+               .valid_modes_mask = REGULATOR_MODE_NORMAL
+                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask = REGULATOR_CHANGE_MODE
+                       | REGULATOR_CHANGE_STATUS
+                       | REGULATOR_CHANGE_VOLTAGE,
+               .always_on = true,
+               .boot_on = 1,
+               .apply_uV = 1,
+       },
+       .consumer_supplies = as3720_sd0_supply,
+       .num_consumer_supplies = ARRAY_SIZE(as3720_sd0_supply),
+};
+
+static struct regulator_init_data as3720_sd1 = {
+       .constraints = {
+               .min_uV =  900000,
+               .max_uV = 1400000,
+               .valid_modes_mask = REGULATOR_MODE_NORMAL
+                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask = REGULATOR_CHANGE_MODE
+                       | REGULATOR_CHANGE_STATUS
+                       | REGULATOR_CHANGE_VOLTAGE,
+               .always_on = true,
+               .boot_on = 1,
+               .apply_uV = 0,
+       },
+       .consumer_supplies = as3720_sd1_supply,
+       .num_consumer_supplies = ARRAY_SIZE(as3720_sd1_supply),
+};
+
+static struct regulator_init_data as3720_sd2 = {
+       .constraints = {
+               .min_uV = 2850000,
+               .max_uV = 3300000,
+               .valid_modes_mask = REGULATOR_MODE_NORMAL
+                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask = REGULATOR_CHANGE_MODE
+                       | REGULATOR_CHANGE_STATUS
+                       | REGULATOR_CHANGE_VOLTAGE,
+               .always_on = true,
+               .boot_on = 1,
+               .apply_uV = 1,
+       },
+       .consumer_supplies = as3720_sd2_supply,
+       .num_consumer_supplies = ARRAY_SIZE(as3720_sd2_supply),
+};
+
+static struct regulator_init_data as3720_sd3 = {
+       .constraints = {
+               .min_uV = 1800000,
+               .max_uV = 1800000,
+               .valid_modes_mask = REGULATOR_MODE_NORMAL
+                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask = REGULATOR_CHANGE_MODE
+                       | REGULATOR_CHANGE_STATUS
+                       | REGULATOR_CHANGE_VOLTAGE,
+               .always_on = true,
+               .boot_on = 1,
+               .apply_uV = 1,
+       },
+       .consumer_supplies = as3720_sd3_supply,
+       .num_consumer_supplies = ARRAY_SIZE(as3720_sd3_supply),
+};
+
+static struct regulator_init_data as3720_sd4 = {
+       .constraints = {
+               .min_uV = 1050000,
+               .max_uV = 1050000,
+               .valid_modes_mask = REGULATOR_MODE_NORMAL
+                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask = REGULATOR_CHANGE_MODE
+                       | REGULATOR_CHANGE_STATUS
+                       | REGULATOR_CHANGE_VOLTAGE,
+               .always_on = true,
+               .boot_on = 1,
+               .apply_uV = 1,
+       },
+       .consumer_supplies = as3720_sd4_supply,
+       .num_consumer_supplies = ARRAY_SIZE(as3720_sd4_supply),
+};
+
+static struct regulator_init_data as3720_sd5 = {
+       .constraints = {
+               .min_uV = 3300000,
+               .max_uV = 3300000,
+               .valid_modes_mask = REGULATOR_MODE_NORMAL
+                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask = REGULATOR_CHANGE_MODE
+                       | REGULATOR_CHANGE_STATUS
+                       | REGULATOR_CHANGE_VOLTAGE,
+               .always_on = true,
+               .boot_on = 1,
+               .apply_uV = 1,
+       },
+       .consumer_supplies = as3720_sd5_supply,
+       .num_consumer_supplies = ARRAY_SIZE(as3720_sd5_supply),
+};
+
+static struct regulator_init_data as3720_sd6 = {
+       .constraints = {
+               .min_uV = 1350000,
+               .max_uV = 1350000,
+               .valid_modes_mask = REGULATOR_MODE_NORMAL
+                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask = REGULATOR_CHANGE_MODE
+                       | REGULATOR_CHANGE_STATUS
+                       | REGULATOR_CHANGE_VOLTAGE,
+               .always_on = true,
+               .boot_on = 1,
+               .apply_uV = 1,
+       },
+       .consumer_supplies = as3720_sd6_supply,
+       .num_consumer_supplies = ARRAY_SIZE(as3720_sd6_supply),
+};
+
+static struct as3720_reg_init as3720_core_init_data[] = {
+       /* disable all regulators */
+       AS3720_REG_INIT(AS3720_SD_CONTROL_REG, 0x7f),
+       AS3720_REG_INIT(AS3720_LDOCONTROL0_REG, 0xef),
+       AS3720_REG_INIT(AS3720_LDOCONTROL1_REG, 0x01),
+       /* set to lowest voltage output */
+       /* set to OTP settings */
+       AS3720_REG_INIT(AS3720_SD0_VOLTAGE_REG, 0x32),
+       AS3720_REG_INIT(AS3720_SD1_VOLTAGE_REG, 0x32),
+       AS3720_REG_INIT(AS3720_SD2_VOLTAGE_REG, 0xFF),
+       AS3720_REG_INIT(AS3720_SD3_VOLTAGE_REG, 0xD0),
+       AS3720_REG_INIT(AS3720_SD4_VOLTAGE_REG, 0xA4),
+       AS3720_REG_INIT(AS3720_SD5_VOLTAGE_REG, 0xFE),
+       AS3720_REG_INIT(AS3720_SD6_VOLTAGE_REG, 0x52),
+       AS3720_REG_INIT(AS3720_LDO0_VOLTAGE_REG, 0x90),
+       AS3720_REG_INIT(AS3720_LDO1_VOLTAGE_REG, 0x43),
+       AS3720_REG_INIT(AS3720_LDO2_VOLTAGE_REG, 0x43),
+       AS3720_REG_INIT(AS3720_LDO3_VOLTAGE_REG, 0xA8),
+       AS3720_REG_INIT(AS3720_LDO4_VOLTAGE_REG, 0x00),
+       AS3720_REG_INIT(AS3720_LDO5_VOLTAGE_REG, 0xff),
+       AS3720_REG_INIT(AS3720_LDO6_VOLTAGE_REG, 0xff),
+       AS3720_REG_INIT(AS3720_LDO7_VOLTAGE_REG, 0x90),
+       AS3720_REG_INIT(AS3720_LDO8_VOLTAGE_REG, 0x7F),
+       AS3720_REG_INIT(AS3720_LDO9_VOLTAGE_REG, 0x00),
+       AS3720_REG_INIT(AS3720_LDO10_VOLTAGE_REG, 0x00),
+       AS3720_REG_INIT(AS3720_LDO11_VOLTAGE_REG, 0x00),
+       {.reg = AS3720_REG_INIT_TERMINATE},
+};
+
+/* config settings are OTP plus initial state
+ * GPIOsignal_out at 20h not configurable through OTP and is initialized to
+ * zero. To enable output, the invert bit must be turned on.
+ * GPIOxcontrol register format
+ * bit(s)  bitname
+ * ---------------------
+ *  7     gpiox_invert   invert input or output
+ * 6:3    gpiox_iosf     0: normal
+ * 2:0    gpiox_mode     0: input, 1: output push/pull, 3: ADC input (tristate)
+ *
+ * Examples:
+ * otp  meaning
+ * ------------
+ * 0x3  gpiox_invert=0(no invert), gpiox_iosf=0(normal), gpiox_mode=3(ADC input)
+ * 0x81 gpiox_invert=1(invert), gpiox_iosf=0(normal), gpiox_mode=1(output)
+ *
+ * Note: output state should be defined for gpiox_mode = output.  Do not change
+ * the state of the invert bit for critical devices such as GPIO 7 which enables
+ * SDRAM. Driver applies invert mask to output state to configure GPIOsignal_out
+ * register correctly.
+ * E.g. Invert = 1, (requested) output state = 1 => GPIOsignal_out = 0
+ */
+
+static struct as3720_gpio_config as3720_gpio_cfgs[] = {
+       {
+               /* otp = 0x3 */
+               .gpio = AS3720_GPIO0,
+               .mode = AS3720_GPIO_MODE_ADC_IN,
+       },
+       {
+               /* otp = 0x3 */
+               .gpio = AS3720_GPIO1,
+               .mode = AS3720_GPIO_MODE_ADC_IN,
+       },
+       {
+               /* otp = 0x3 */
+               .gpio = AS3720_GPIO2,
+               .mode = AS3720_GPIO_MODE_ADC_IN,
+       },
+       {
+               /* otp = 0x01 => REGEN_3 = LP0 gate (1.8V, 5 V) */
+               .gpio       = AS3720_GPIO3,
+               .invert     = AS3720_GPIO_CFG_INVERT, /* don't go into LP0 */
+               .mode       = AS3720_GPIO_MODE_OUTPUT_VDDH,
+               .output_state = AS3720_GPIO_CFG_OUTPUT_ENABLED,
+       },
+       {
+               /* otp = 0x81 => on by default
+                * gates SDMMC3
+                */
+               .gpio       = AS3720_GPIO4,
+               .invert     = AS3720_GPIO_CFG_NO_INVERT,
+               .mode       = AS3720_GPIO_MODE_OUTPUT_VDDH,
+               .output_state = AS3720_GPIO_CFG_OUTPUT_DISABLED,
+       },
+       {
+               /* otp = 0x3  EN_MIC_BIAS_L */
+               .gpio = AS3720_GPIO5,
+               .mode = AS3720_GPIO_MODE_ADC_IN,
+       },
+       {
+               /* otp = 0x3  CAM_LDO1_EN */
+               .gpio = AS3720_GPIO6,
+               .mode = AS3720_GPIO_MODE_ADC_IN,
+       },
+       {
+               /* otp = 0x81 */
+               .gpio       = AS3720_GPIO7,
+               .invert     = AS3720_GPIO_CFG_INVERT,
+               .mode       = AS3720_GPIO_MODE_OUTPUT_VDDH,
+               .output_state = AS3720_GPIO_CFG_OUTPUT_ENABLED,
+       },
+};
+
+static struct as3720_platform_data as3720_pdata = {
+       .reg_init[AS3720_LDO0] = &as3720_ldo0,
+       .reg_init[AS3720_LDO1] = &as3720_ldo1,
+       .reg_init[AS3720_LDO2] = &as3720_ldo2,
+       .reg_init[AS3720_LDO3] = &as3720_ldo3,
+       .reg_init[AS3720_LDO5] = &as3720_ldo5,
+       .reg_init[AS3720_LDO6] = &as3720_ldo6,
+       .reg_init[AS3720_LDO8] = &as3720_ldo8,
+       .reg_init[AS3720_SD0] = &as3720_sd0,
+       .reg_init[AS3720_SD1] = &as3720_sd1,
+       .reg_init[AS3720_SD2] = &as3720_sd2,
+       .reg_init[AS3720_SD3] = &as3720_sd3,
+       .reg_init[AS3720_SD4] = &as3720_sd4,
+       .reg_init[AS3720_SD5] = &as3720_sd5,
+       .reg_init[AS3720_SD6] = &as3720_sd6,
+
+       .core_init_data = &as3720_core_init_data[0],
+       .gpio_base = AS3720_GPIO_BASE,
+       .rtc_start_year = 2010,
+
+       .num_gpio_cfgs = ARRAY_SIZE(as3720_gpio_cfgs),
+       .gpio_cfgs     = as3720_gpio_cfgs,
+};
+
+static struct i2c_board_info __initdata as3720_regulators[] = {
+       {
+               I2C_BOARD_INFO("as3720", 0x40),
+               .flags = I2C_CLIENT_WAKE,
+               .irq = INT_EXTERNAL_PMU,
+               .platform_data = &as3720_pdata,
+       },
+};
+
+int __init pismo_as3720_regulator_init(void)
+{
+       printk(KERN_INFO "%s: i2c_register_board_info\n",
+               __func__);
+       i2c_register_board_info(4, as3720_regulators,
+                               ARRAY_SIZE(as3720_regulators));
+       return 0;
+}
+
+static int ac_online(void)
+{
+       return 1;
+}
+
+static struct resource pismo_pda_resources[] = {
+       [0] = {
+               .name   = "ac",
+       },
+};
+
+static struct pda_power_pdata pismo_pda_data = {
+       .is_ac_online   = ac_online,
+};
+
+static struct platform_device pismo_pda_power_device = {
+       .name           = "pda-power",
+       .id             = -1,
+       .resource       = pismo_pda_resources,
+       .num_resources  = ARRAY_SIZE(pismo_pda_resources),
+       .dev    = {
+               .platform_data  = &pismo_pda_data,
+       },
+};
+
+static struct tegra_suspend_platform_data pismo_suspend_data = {
+       .cpu_timer      = 2000,
+       .cpu_off_timer  = 2000,
+       .suspend_mode   = TEGRA_SUSPEND_NONE,
+       .core_timer     = 0x7e7e,
+       .core_off_timer = 2000,
+       .corereq_high   = true,
+       .sysclkreq_high = true,
+};
+
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
+/* board parameters for cpu dfll */
+static struct tegra_cl_dvfs_cfg_param pismo_cl_dvfs_param = {
+       .sample_rate = 12500,
+
+       .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
+       .cf = 10,
+       .ci = 0,
+       .cg = 2,
+
+       .droop_cut_value = 0xF,
+       .droop_restore_ramp = 0x0,
+       .scale_out_ramp = 0x0,
+};
+#endif
+
+/* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
+#define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
+static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
+static inline void fill_reg_map(void)
+{
+       int i;
+       for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
+               pmu_cpu_vdd_map[i].reg_value = i + 0x23;
+               pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
+       }
+}
+
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
+static struct tegra_cl_dvfs_platform_data pismo_cl_dvfs_data = {
+       .dfll_clk_name = "dfll_cpu",
+       .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
+       .u.pmu_i2c = {
+               .fs_rate = 400000,
+               .slave_addr = 0x86,
+               .reg = 0x00,
+       },
+       .vdd_map = pmu_cpu_vdd_map,
+       .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
+
+       .cfg_param = &pismo_cl_dvfs_param,
+};
+
+static int __init pismo_cl_dvfs_init(void)
+{
+       fill_reg_map();
+       tegra_cl_dvfs_device.dev.platform_data = &pismo_cl_dvfs_data;
+       platform_device_register(&tegra_cl_dvfs_device);
+
+       return 0;
+}
+#endif
+
+static struct regulator_bulk_data pismo_gps_regulator_supply[] = {
+       [0] = {
+               .supply = "vdd_gps_3v3",
+       },
+       [1] = {
+               .supply = "vdd_gps_1v8",
+       },
+};
+
+static struct regulator_userspace_consumer_data pismo_gps_regulator_pdata = {
+       .num_supplies   = ARRAY_SIZE(pismo_gps_regulator_supply),
+       .supplies       = pismo_gps_regulator_supply,
+};
+
+static struct platform_device pismo_gps_regulator_device = {
+       .name   = "reg-userspace-consumer",
+       .id     = 2,
+       .dev    = {
+                       .platform_data = &pismo_gps_regulator_pdata,
+       },
+};
+
+static struct regulator_bulk_data pismo_bt_regulator_supply[] = {
+       [0] = {
+               .supply = "vdd_bt_3v3",
+       },
+       [1] = {
+               .supply = "vddio_bt_1v8",
+       },
+};
+
+static struct regulator_userspace_consumer_data pismo_bt_regulator_pdata = {
+       .num_supplies   = ARRAY_SIZE(pismo_bt_regulator_supply),
+       .supplies       = pismo_bt_regulator_supply,
+};
+
+static struct platform_device pismo_bt_regulator_device = {
+       .name   = "reg-userspace-consumer",
+       .id     = 1,
+       .dev    = {
+                       .platform_data = &pismo_bt_regulator_pdata,
+       },
+};
+
+/* Gated by CAM_LDO1_EN From AMS7230 GPIO6*/
+static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
+       REGULATOR_SUPPLY("dvdd_cam", NULL),
+       REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
+       REGULATOR_SUPPLY("vi2c", "2-0030"),
+       REGULATOR_SUPPLY("vif", "2-0036"),
+       REGULATOR_SUPPLY("dovdd", "2-0010"),
+       REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
+};
+
+/* Gated by PMU_REGEN3 From AMS7230 GPIO3*/
+static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
+       REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
+};
+
+/* Not gated */
+static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
+       REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
+};
+
+/* Not Gated */
+static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
+       REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
+};
+
+/* Macro for defining fixed regulator sub device data */
+#define FIXED_SUPPLY(_name) "fixed_reg_"#_name
+#define FIXED_REG(_id, _var, _name, _always_on, _boot_on,      \
+       _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
+       static struct regulator_init_data ri_data_##_var =              \
+       {                                                               \
+               .num_consumer_supplies =                                \
+                       ARRAY_SIZE(fixed_reg_##_name##_supply),         \
+               .consumer_supplies = fixed_reg_##_name##_supply,        \
+               .constraints = {                                        \
+                       .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
+                                       REGULATOR_MODE_STANDBY),        \
+                       .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
+                                       REGULATOR_CHANGE_STATUS |       \
+                                       REGULATOR_CHANGE_VOLTAGE),      \
+                       .always_on = _always_on,                        \
+                       .boot_on = _boot_on,                            \
+               },                                                      \
+       };                                                              \
+       static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
+       {                                                               \
+               .supply_name = FIXED_SUPPLY(_name),                     \
+               .microvolts = _millivolts * 1000,                       \
+               .gpio = _gpio_nr,                                       \
+               .gpio_is_open_drain = _open_drain,                      \
+               .enable_high = _active_high,                            \
+               .enabled_at_boot = _boot_state,                         \
+               .init_data = &ri_data_##_var,                           \
+       };                                                              \
+       static struct platform_device fixed_reg_##_var##_dev = {        \
+               .name = "reg-fixed-voltage",                            \
+               .id = _id,                                              \
+               .dev = {                                                \
+                       .platform_data = &fixed_reg_##_var##_pdata,     \
+               },                                                      \
+       }
+
+FIXED_REG(1,   en_1v8_cam,     en_1v8_cam,     0,      0,
+       AS3720_GPIO_BASE + AS3720_GPIO6,        false,  true,   0,      1800);
+
+FIXED_REG(2,   vdd_hdmi_5v0,   vdd_hdmi_5v0,   0,      0,
+       TEGRA_GPIO_PK1, false,  true,   0,      5000);
+
+FIXED_REG(3,   usb1_vbus,      usb1_vbus,      0,      0,
+       -EINVAL,        true,   true,   1,      5000);
+
+FIXED_REG(4,   usb3_vbus,      usb3_vbus,      0,      0,
+       -EINVAL,        true,   true,   1,      5000);
+
+/*
+ * Creating the fixed regulator device tables
+ */
+
+#define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
+
+#define PISMO_COMMON_FIXED_REG         \
+       ADD_FIXED_REG(usb1_vbus),               \
+       ADD_FIXED_REG(usb3_vbus),               \
+       ADD_FIXED_REG(vdd_hdmi_5v0),            \
+       ADD_FIXED_REG(en_1v8_cam),
+
+/* Gpio switch regulator platform data for pluto */
+static struct platform_device *fixed_reg_devs_pm347[] = {
+       PISMO_COMMON_FIXED_REG
+};
+
+
+static int __init pismo_fixed_regulator_init(void)
+{
+
+       if (!machine_is_pismo())
+               return 0;
+
+       return platform_add_devices(fixed_reg_devs_pm347,
+                               ARRAY_SIZE(fixed_reg_devs_pm347));
+}
+
+subsys_initcall_sync(pismo_fixed_regulator_init);
+
+int __init pismo_regulator_init(void)
+{
+
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
+       pismo_cl_dvfs_init();
+#endif
+       pismo_as3720_regulator_init();
+
+       platform_device_register(&pismo_pda_power_device);
+       platform_device_register(&pismo_bt_regulator_device);
+       platform_device_register(&pismo_gps_regulator_device);
+       return 0;
+}
+
+int __init pismo_suspend_init(void)
+{
+       tegra_init_suspend(&pismo_suspend_data);
+       return 0;
+}
+
+int __init pismo_edp_init(void)
+{
+#ifdef CONFIG_TEGRA_EDP_LIMITS
+       unsigned int regulator_mA;
+
+       regulator_mA = get_maximum_cpu_current_supported();
+       if (!regulator_mA)
+               regulator_mA = 15000;
+
+       pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
+
+       tegra_init_cpu_edp_limits(regulator_mA);
+#endif
+       return 0;
+}
+
+
+static struct soctherm_platform_data pismo_soctherm_data = {
+       .soctherm_clk_rate = 136000000,
+       .tsensor_clk_rate = 500000,
+       .sensor_data = {
+               [TSENSE_CPU0] = {
+                       .enable = true,
+                       .tall = 16300,
+                       .tiddq = 1,
+                       .ten_count = 1,
+                       .tsample = 163,
+                       .pdiv = 10,
+               },
+               [TSENSE_CPU1] = {
+                       .enable = true,
+                       .tall = 16300,
+                       .tiddq = 1,
+                       .ten_count = 1,
+                       .tsample = 163,
+                       .pdiv = 10,
+               },
+               [TSENSE_CPU2] = {
+                       .enable = true,
+                       .tall = 16300,
+                       .tiddq = 1,
+                       .ten_count = 1,
+                       .tsample = 163,
+                       .pdiv = 10,
+               },
+               [TSENSE_CPU3] = {
+                       .enable = true,
+                       .tall = 16300,
+                       .tiddq = 1,
+                       .ten_count = 1,
+                       .tsample = 163,
+                       .pdiv = 10,
+               },
+               /* MEM0/MEM1 won't be used */
+               [TSENSE_MEM0] = {
+                       .enable = false,
+               },
+               [TSENSE_MEM1] = {
+                       .enable = false,
+               },
+               [TSENSE_GPU] = {
+                       .enable = true,
+                       .tall = 16300,
+                       .tiddq = 1,
+                       .ten_count = 1,
+                       .tsample = 163,
+                       .pdiv = 10,
+               },
+               [TSENSE_PLLX] = {
+                       .enable = true,
+                       .tall = 16300,
+                       .tiddq = 1,
+                       .ten_count = 1,
+                       .tsample = 163,
+                       .pdiv = 10,
+               },
+       },
+};
+
+int __init pismo_soctherm_init(void)
+{
+       return tegra11_soctherm_init(&pismo_soctherm_data);
+}
+
+
diff --git a/arch/arm/mach-tegra/board-pismo-powermon.c b/arch/arm/mach-tegra/board-pismo-powermon.c
new file mode 100644 (file)
index 0000000..ac87c24
--- /dev/null
@@ -0,0 +1,350 @@
+/*
+ * arch/arm/mach-tegra/board-pismo-powermon.c
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation. All Rights Reserved.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <linux/i2c.h>
+#include <linux/ina219.h>
+
+#include "board.h"
+#include "board-pismo.h"
+
+#define PRECISION_MULTIPLIER_PISMO 1000
+
+enum {
+       VDD_12V_DCIN_RS,
+       VDD_AC_BAT_VIN1,
+       VDD_5V0_SYS,
+       VDD_3V3_SYS,
+       VDD_3V3_SYS_VIN4_5_7,
+       AVDD_USB_HDMI,
+       VDD_AC_BAT_D1,
+       VDD_AO_SMPS12_IN,
+       VDD_3V3_SYS_SMPS45_IN,
+       VDD_AO_SMPS2_IN,
+       VDDIO_HV_AP,
+       VDD_1V8_LDO3_IN,
+       VDD_3V3_SYS_LDO4_IN,
+       VDD_AO_LDO8_IN,
+       VDD_1V8_AP,
+       VDD_1V8_DSM,
+};
+
+static struct ina219_platform_data power_mon_info[] = {
+       [VDD_12V_DCIN_RS] = {
+               .calibration_data  = 0xaec0,
+               .power_lsb = 1.8311874106 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "VDD_12V_DCIN_RS",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 10,
+       },
+
+       [VDD_AC_BAT_VIN1] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "VDD_AC_BAT_VIN1",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 10,
+       },
+
+       [VDD_5V0_SYS] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 2.5000762963 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "VDD_5V0_SYS",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 5,
+       },
+
+       [VDD_3V3_SYS] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 2.5000762963 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "VDD_3V3_SYS",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 5,
+       },
+
+       [VDD_3V3_SYS_VIN4_5_7] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "VDD_3V3_SYS_VIN4_5_7",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 10,
+       },
+
+       [AVDD_USB_HDMI] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "AVDD_USB_HDMI",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 10,
+       },
+
+       [VDD_AC_BAT_D1] = {
+               .calibration_data  = 0x7CD2,
+               .power_lsb = 2.563685298 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "VDD_AC_BAT_D1",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 10,
+       },
+
+       [VDD_AO_SMPS12_IN] = {
+               .calibration_data  = 0xaec0,
+               .power_lsb = 1.8311874106 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "VDD_AO_SMPS12_IN",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 10,
+       },
+
+       [VDD_3V3_SYS_SMPS45_IN] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "VDD_3V3_SYS_SMPS45_IN",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 10,
+       },
+
+       [VDD_AO_SMPS2_IN] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "VDD_AO_SMPS2_IN",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 10,
+       },
+
+       [VDDIO_HV_AP] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "VDDIO_HV_AP",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 10,
+       },
+
+       [VDD_1V8_LDO3_IN] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "VDD_1V8_LDO3_IN",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 10,
+       },
+
+       [VDD_3V3_SYS_LDO4_IN] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "VDD_3V3_SYS_LDO4_IN",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 10,
+       },
+
+       [VDD_AO_LDO8_IN] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "VDD_AO_LDO8_IN",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 10,
+       },
+
+       [VDD_1V8_AP] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "VDD_1V8_AP",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 10,
+       },
+
+       [VDD_1V8_DSM] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_PISMO,
+               .rail_name = "VDD_1V8_DSM",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_PISMO,
+               .cont_conf = 0x3FFF,
+               .trig_conf = 0x1DB,
+               .shunt_resistor = 10,
+       },
+};
+
+enum {
+       INA_I2C_ADDR_40,
+       INA_I2C_ADDR_41,
+       INA_I2C_ADDR_42,
+       INA_I2C_ADDR_43,
+       INA_I2C_ADDR_44,
+       INA_I2C_ADDR_45,
+       INA_I2C_ADDR_46,
+       INA_I2C_ADDR_47,
+       INA_I2C_ADDR_48,
+       INA_I2C_ADDR_49,
+       INA_I2C_ADDR_4A,
+       INA_I2C_ADDR_4B,
+       INA_I2C_ADDR_4C,
+       INA_I2C_ADDR_4D,
+       INA_I2C_ADDR_4E,
+       INA_I2C_ADDR_4F,
+};
+
+static struct i2c_board_info pismo_i2c0_ina219_board_info[] = {
+       [INA_I2C_ADDR_40] = {
+               I2C_BOARD_INFO("ina219", 0x40),
+               .platform_data = &power_mon_info[VDD_12V_DCIN_RS],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_41] = {
+               I2C_BOARD_INFO("ina219", 0x41),
+               .platform_data = &power_mon_info[VDD_AC_BAT_VIN1],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_42] = {
+               I2C_BOARD_INFO("ina219", 0x42),
+               .platform_data = &power_mon_info[VDD_5V0_SYS],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_43] = {
+               I2C_BOARD_INFO("ina219", 0x43),
+               .platform_data = &power_mon_info[VDD_3V3_SYS],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_44] = {
+               I2C_BOARD_INFO("ina219", 0x44),
+               .platform_data = &power_mon_info[VDD_3V3_SYS_VIN4_5_7],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_45] = {
+               I2C_BOARD_INFO("ina219", 0x45),
+               .platform_data = &power_mon_info[AVDD_USB_HDMI],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_46] = {
+               I2C_BOARD_INFO("ina219", 0x46),
+               .platform_data = &power_mon_info[VDD_AC_BAT_D1],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_47] = {
+               I2C_BOARD_INFO("ina219", 0x47),
+               .platform_data = &power_mon_info[VDD_AO_SMPS12_IN],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_48] = {
+               I2C_BOARD_INFO("ina219", 0x48),
+               .platform_data = &power_mon_info[VDD_3V3_SYS_SMPS45_IN],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_49] = {
+               I2C_BOARD_INFO("ina219", 0x49),
+               .platform_data = &power_mon_info[VDD_AO_SMPS2_IN],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_4A] = {
+               I2C_BOARD_INFO("ina219", 0x4A),
+               .platform_data = &power_mon_info[VDDIO_HV_AP],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_4B] = {
+               I2C_BOARD_INFO("ina219", 0x4B),
+               .platform_data = &power_mon_info[VDD_1V8_LDO3_IN],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_4C] = {
+               I2C_BOARD_INFO("ina219", 0x4C),
+               .platform_data = &power_mon_info[VDD_3V3_SYS_LDO4_IN],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_4D] = {
+               I2C_BOARD_INFO("ina219", 0x4D),
+               .platform_data = &power_mon_info[VDD_AO_LDO8_IN],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_4E] = {
+               I2C_BOARD_INFO("ina219", 0x4E),
+               .platform_data = &power_mon_info[VDD_1V8_AP],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_4F] = {
+               I2C_BOARD_INFO("ina219", 0x4F),
+               .platform_data = &power_mon_info[VDD_1V8_DSM],
+               .irq = -1,
+       },
+};
+
+int __init pismo_pmon_init(void)
+{
+       i2c_register_board_info(1, pismo_i2c0_ina219_board_info,
+               ARRAY_SIZE(pismo_i2c0_ina219_board_info));
+
+       return 0;
+}
+
diff --git a/arch/arm/mach-tegra/board-pismo-sdhci.c b/arch/arm/mach-tegra/board-pismo-sdhci.c
new file mode 100644 (file)
index 0000000..3131006
--- /dev/null
@@ -0,0 +1,409 @@
+/*
+ * arch/arm/mach-tegra/board-pismo-sdhci.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2012 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/resource.h>
+#include <linux/platform_device.h>
+#include <linux/wlan_plat.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+#include <linux/mmc/host.h>
+#include <linux/wl12xx.h>
+#include <linux/platform_data/mmc-sdhci-tegra.h>
+
+#include <asm/mach-types.h>
+#include <mach/irqs.h>
+#include <mach/gpio-tegra.h>
+#include <mach/io_dpd.h>
+
+#include "gpio-names.h"
+#include "board.h"
+#include "board-pismo.h"
+#include "iomap.h"
+
+#define PISMO_WLAN_PWR TEGRA_GPIO_PCC5
+#define PISMO_WLAN_RST TEGRA_GPIO_PX7
+#define PISMO_WLAN_WOW TEGRA_GPIO_PU5
+#define PISMO_SD_CD            TEGRA_GPIO_PV2
+static void (*wifi_status_cb)(int card_present, void *dev_id);
+static void *wifi_status_cb_devid;
+static int pismo_wifi_status_register(void (*callback)(int , void *), void *);
+
+static int pismo_wifi_reset(int on);
+static int pismo_wifi_power(int on);
+static int pismo_wifi_set_carddetect(int val);
+
+static struct wifi_platform_data pismo_wifi_control = {
+       .set_power      = pismo_wifi_power,
+       .set_reset      = pismo_wifi_reset,
+       .set_carddetect = pismo_wifi_set_carddetect,
+};
+
+static struct resource wifi_resource[] = {
+       [0] = {
+               .name   = "bcm4329_wlan_irq",
+               .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
+                               | IORESOURCE_IRQ_SHAREABLE,
+       },
+};
+
+static struct platform_device pismo_wifi_device = {
+       .name           = "bcm4329_wlan",
+       .id             = 1,
+       .num_resources  = 1,
+       .resource       = wifi_resource,
+       .dev            = {
+               .platform_data = &pismo_wifi_control,
+       },
+};
+
+static struct resource sdhci_resource0[] = {
+       [0] = {
+               .start  = INT_SDMMC1,
+               .end    = INT_SDMMC1,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [1] = {
+               .start  = TEGRA_SDMMC1_BASE,
+               .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct resource sdhci_resource2[] = {
+       [0] = {
+               .start  = INT_SDMMC3,
+               .end    = INT_SDMMC3,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [1] = {
+               .start  = TEGRA_SDMMC3_BASE,
+               .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct resource sdhci_resource3[] = {
+       [0] = {
+               .start  = INT_SDMMC4,
+               .end    = INT_SDMMC4,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [1] = {
+               .start  = TEGRA_SDMMC4_BASE,
+               .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+static struct embedded_sdio_data embedded_sdio_data0 = {
+       .cccr   = {
+               .sdio_vsn       = 2,
+               .multi_block    = 1,
+               .low_speed      = 0,
+               .wide_bus       = 0,
+               .high_power     = 1,
+               .high_speed     = 1,
+       },
+       .cis  = {
+               .vendor  = 0x02d0,
+               .device  = 0x4329,
+       },
+};
+#endif
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
+       .mmc_data = {
+               .register_status_notify = pismo_wifi_status_register,
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+               .embedded_sdio = &embedded_sdio_data0,
+#endif
+               .built_in = 0,
+               .ocr_mask = MMC_OCR_1V8_MASK,
+       },
+#ifndef CONFIG_MMC_EMBEDDED_SDIO
+       .pm_flags = MMC_PM_KEEP_POWER,
+#endif
+       .cd_gpio = -1,
+       .wp_gpio = -1,
+       .power_gpio = -1,
+       .tap_delay = 0x2,
+       .trim_delay = 0x2,
+       .ddr_clk_limit = 41000000,
+       .uhs_mask = MMC_UHS_MASK_SDR104 |
+               MMC_UHS_MASK_DDR50,
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
+       .cd_gpio = PISMO_SD_CD,
+       .wp_gpio = -1,
+       .power_gpio = -1,
+       .tap_delay = 0x3,
+       .trim_delay = 0x3,
+       .ddr_clk_limit = 41000000,
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
+       .cd_gpio = -1,
+       .wp_gpio = -1,
+       .power_gpio = -1,
+       .is_8bit = 1,
+       .tap_delay = 0x5,
+       .trim_delay = 0x3,
+       .ddr_clk_limit = 41000000,
+       .mmc_data = {
+               .built_in = 1,
+               .ocr_mask = MMC_OCR_1V8_MASK,
+       }
+};
+
+static struct platform_device tegra_sdhci_device0 = {
+       .name           = "sdhci-tegra",
+       .id             = 0,
+       .resource       = sdhci_resource0,
+       .num_resources  = ARRAY_SIZE(sdhci_resource0),
+       .dev = {
+               .platform_data = &tegra_sdhci_platform_data0,
+       },
+};
+
+static struct platform_device tegra_sdhci_device2 = {
+       .name           = "sdhci-tegra",
+       .id             = 2,
+       .resource       = sdhci_resource2,
+       .num_resources  = ARRAY_SIZE(sdhci_resource2),
+       .dev = {
+               .platform_data = &tegra_sdhci_platform_data2,
+       },
+};
+
+static struct platform_device tegra_sdhci_device3 = {
+       .name           = "sdhci-tegra",
+       .id             = 3,
+       .resource       = sdhci_resource3,
+       .num_resources  = ARRAY_SIZE(sdhci_resource3),
+       .dev = {
+               .platform_data = &tegra_sdhci_platform_data3,
+       },
+};
+
+static int pismo_wifi_status_register(
+               void (*callback)(int card_present, void *dev_id),
+               void *dev_id)
+{
+       if (wifi_status_cb)
+               return -EAGAIN;
+       wifi_status_cb = callback;
+       wifi_status_cb_devid = dev_id;
+       return 0;
+}
+
+static int pismo_wifi_set_carddetect(int val)
+{
+       pr_debug("%s: %d\n", __func__, val);
+       if (wifi_status_cb)
+               wifi_status_cb(val, wifi_status_cb_devid);
+       else
+               pr_warning("%s: Nobody to notify\n", __func__);
+       return 0;
+}
+
+static struct regulator *pismo_vdd_com_3v3;
+static struct regulator *pismo_vddio_com_1v8;
+#define PISMO_VDD_WIFI_3V3 "vdd_wifi_3v3"
+#define PISMO_VDD_WIFI_1V8 "vddio_wifi_1v8"
+
+static int pismo_wifi_regulator_enable(void)
+{
+       int ret = 0;
+
+       /* Enable COM's vdd_com_3v3 regulator*/
+       if (IS_ERR_OR_NULL(pismo_vdd_com_3v3)) {
+               pismo_vdd_com_3v3 = regulator_get(&pismo_wifi_device.dev,
+                                                       PISMO_VDD_WIFI_3V3);
+               if (IS_ERR_OR_NULL(pismo_vdd_com_3v3)) {
+                       pr_err("Couldn't get regulator "
+                               PISMO_VDD_WIFI_3V3 "\n");
+                       return PTR_ERR(pismo_vdd_com_3v3);
+               }
+
+               ret = regulator_enable(pismo_vdd_com_3v3);
+               if (ret < 0) {
+                       pr_err("Couldn't enable regulator "
+                               PISMO_VDD_WIFI_3V3 "\n");
+                       regulator_put(pismo_vdd_com_3v3);
+                       pismo_vdd_com_3v3 = NULL;
+                       return ret;
+               }
+       }
+
+       /* Enable COM's vddio_com_1v8 regulator*/
+       if (IS_ERR_OR_NULL(pismo_vddio_com_1v8)) {
+               pismo_vddio_com_1v8 = regulator_get(&pismo_wifi_device.dev,
+                       PISMO_VDD_WIFI_1V8);
+               if (IS_ERR_OR_NULL(pismo_vddio_com_1v8)) {
+                       pr_err("Couldn't get regulator "
+                               PISMO_VDD_WIFI_1V8 "\n");
+                       regulator_disable(pismo_vdd_com_3v3);
+
+                       regulator_put(pismo_vdd_com_3v3);
+                       pismo_vdd_com_3v3 = NULL;
+                       return PTR_ERR(pismo_vddio_com_1v8);
+               }
+
+               ret = regulator_enable(pismo_vddio_com_1v8);
+               if (ret < 0) {
+                       pr_err("Couldn't enable regulator "
+                               PISMO_VDD_WIFI_1V8 "\n");
+                       regulator_put(pismo_vddio_com_1v8);
+                       pismo_vddio_com_1v8 = NULL;
+
+                       regulator_disable(pismo_vdd_com_3v3);
+                       regulator_put(pismo_vdd_com_3v3);
+                       pismo_vdd_com_3v3 = NULL;
+                       return ret;
+               }
+       }
+
+       return ret;
+}
+
+static void pismo_wifi_regulator_disable(void)
+{
+       /* Disable COM's vdd_com_3v3 regulator*/
+       if (!IS_ERR_OR_NULL(pismo_vdd_com_3v3)) {
+               regulator_disable(pismo_vdd_com_3v3);
+               regulator_put(pismo_vdd_com_3v3);
+               pismo_vdd_com_3v3 = NULL;
+       }
+
+       /* Disable COM's vddio_com_1v8 regulator*/
+       if (!IS_ERR_OR_NULL(pismo_vddio_com_1v8)) {
+               regulator_disable(pismo_vddio_com_1v8);
+               regulator_put(pismo_vddio_com_1v8);
+               pismo_vddio_com_1v8 = NULL;
+       }
+}
+
+static int pismo_wifi_power(int on)
+{
+       struct tegra_io_dpd *sd_dpd;
+       int ret = 0;
+
+       pr_debug("%s: %d\n", __func__, on);
+       /* Enable COM's regulators on wi-fi poer on*/
+       if (on == 1) {
+               ret = pismo_wifi_regulator_enable();
+               if (ret < 0) {
+                       pr_err("Failed to enable COM regulators\n");
+                       return ret;
+               }
+       }
+
+       /*
+        * FIXME : we need to revisit IO DPD code
+        * on how should multiple pins under DPD get controlled
+        *
+        * pismo GPIO WLAN enable is part of SDMMC3 pin group
+        */
+       sd_dpd = tegra_io_dpd_get(&tegra_sdhci_device2.dev);
+       if (sd_dpd) {
+               mutex_lock(&sd_dpd->delay_lock);
+               tegra_io_dpd_disable(sd_dpd);
+               mutex_unlock(&sd_dpd->delay_lock);
+       }
+       gpio_set_value(PISMO_WLAN_PWR, on);
+       mdelay(100);
+       gpio_set_value(PISMO_WLAN_RST, on);
+       mdelay(200);
+       if (sd_dpd) {
+               mutex_lock(&sd_dpd->delay_lock);
+               tegra_io_dpd_enable(sd_dpd);
+               mutex_unlock(&sd_dpd->delay_lock);
+       }
+
+       /* Disable COM's regulators on wi-fi poer off*/
+       if (on != 1) {
+               pr_debug("Disabling COM regulators\n");
+               pismo_wifi_regulator_disable();
+       }
+
+       return ret;
+}
+
+static int pismo_wifi_reset(int on)
+{
+       pr_debug("%s: do nothing\n", __func__);
+       return 0;
+}
+
+static int __init pismo_wifi_init(void)
+{
+       int rc;
+
+       rc = gpio_request(PISMO_WLAN_PWR, "wlan_power");
+       if (rc)
+               pr_err("WLAN_PWR gpio request failed:%d\n", rc);
+       rc = gpio_request(PISMO_WLAN_RST, "wlan_rst");
+       if (rc)
+               pr_err("WLAN_RST gpio request failed:%d\n", rc);
+       rc = gpio_request(PISMO_WLAN_WOW, "bcmsdh_sdmmc");
+       if (rc)
+               pr_err("WLAN_WOW gpio request failed:%d\n", rc);
+
+       rc = gpio_direction_output(PISMO_WLAN_PWR, 0);
+       if (rc)
+               pr_err("WLAN_PWR gpio direction configuration failed:%d\n", rc);
+       gpio_direction_output(PISMO_WLAN_RST, 0);
+       if (rc)
+               pr_err("WLAN_RST gpio direction configuration failed:%d\n", rc);
+       rc = gpio_direction_input(PISMO_WLAN_WOW);
+       if (rc)
+               pr_err("WLAN_WOW gpio direction configuration failed:%d\n", rc);
+
+       wifi_resource[0].start = wifi_resource[0].end =
+               gpio_to_irq(PISMO_WLAN_WOW);
+
+       platform_device_register(&pismo_wifi_device);
+       return 0;
+}
+
+#ifdef CONFIG_TEGRA_PREPOWER_WIFI
+static int __init pismo_wifi_prepower(void)
+{
+       if (!machine_is_pismo())
+               return 0;
+
+       pismo_wifi_power(1);
+
+       return 0;
+}
+
+subsys_initcall_sync(pismo_wifi_prepower);
+#endif
+
+int __init pismo_sdhci_init(void)
+{
+       platform_device_register(&tegra_sdhci_device3);
+       platform_device_register(&tegra_sdhci_device2);
+       platform_device_register(&tegra_sdhci_device0);
+       pismo_wifi_init();
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-pismo-sensors.c b/arch/arm/mach-tegra/board-pismo-sensors.c
new file mode 100644 (file)
index 0000000..97e2f16
--- /dev/null
@@ -0,0 +1,718 @@
+/*
+ * arch/arm/mach-tegra/board-pismo-sensors.c
+ *
+ * Copyright (c) 2012 NVIDIA CORPORATION, All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of NVIDIA CORPORATION nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/mpu.h>
+#include <linux/regulator/consumer.h>
+#include <linux/gpio.h>
+#include <linux/therm_est.h>
+#include <linux/nct1008.h>
+#include <mach/edp.h>
+
+#include <mach/gpio-tegra.h>
+#include <mach/pinmux-t11.h>
+#include <mach/pinmux.h>
+#include <media/imx091.h>
+#include <media/ov9772.h>
+#include <media/as364x.h>
+#include <media/ad5816.h>
+#include <generated/mach-types.h>
+#include <linux/power/sbs-battery.h>
+
+#include "gpio-names.h"
+#include "board.h"
+#include "board-common.h"
+#include "board-pismo.h"
+#include "cpu-tegra.h"
+#include "devices.h"
+#include "tegra-board-id.h"
+#include "dvfs.h"
+
+static struct nvc_gpio_pdata imx091_gpio_pdata[] = {
+       {IMX091_GPIO_RESET, CAM_RSTN, true, false},
+       {IMX091_GPIO_PWDN, CAM1_POWER_DWN_GPIO, true, false},
+       {IMX091_GPIO_GP1, CAM_GPIO1, true, false}
+};
+
+static struct balanced_throttle tj_throttle = {
+       .throt_tab_size = 19,
+       .throt_tab = {
+               {      0, 1000 },
+               {  51000, 1000 },
+               { 102000, 1000 },
+               { 204000, 1000 },
+               { 252000, 1000 },
+               { 288000, 1000 },
+               { 372000, 1000 },
+               { 468000, 1000 },
+               { 510000, 1000 },
+               { 612000, 1000 },
+               { 714000, 1050 },
+               { 816000, 1050 },
+               { 918000, 1050 },
+               {1020000, 1100 },
+               {1122000, 1100 },
+               {1224000, 1100 },
+               {1326000, 1100 },
+               {1428000, 1100 },
+               {1530000, 1100 },
+       },
+};
+
+static int __init pismo_throttle_init(void)
+{
+       if (machine_is_pismo())
+               balanced_throttle_register(&tj_throttle, "pismo-nct");
+       return 0;
+}
+module_init(pismo_throttle_init);
+
+static struct nct1008_platform_data pismo_nct1008_pdata = {
+       .supported_hwrev = true,
+       .ext_range = true,
+       .conv_rate = 0x08,
+       .offset = 0,
+       .shutdown_ext_limit = 85, /* C */
+       .shutdown_local_limit = 120, /* C */
+
+       .passive_delay = 2000,
+
+       .num_trips = 1,
+       .trips = {
+               /* Thermal Throttling */
+               [0] = {
+                       .cdev_type = "pismo-nct",
+                       .trip_temp = 75000,
+                       .trip_type = THERMAL_TRIP_PASSIVE,
+                       .state = THERMAL_NO_LIMIT,
+                       .hysteresis = 0,
+               },
+       },
+};
+
+static struct i2c_board_info pismo_i2c4_nct1008_board_info[] = {
+       {
+               I2C_BOARD_INFO("nct1008", 0x4C),
+               .platform_data = &pismo_nct1008_pdata,
+               .irq = -1,
+       }
+};
+
+#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
+       {                                                       \
+               .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
+               .func           = TEGRA_MUX_##_mux,             \
+               .pupd           = TEGRA_PUPD_##_pupd,           \
+               .tristate       = TEGRA_TRI_##_tri,             \
+               .io             = TEGRA_PIN_##_io,              \
+               .lock           = TEGRA_PIN_LOCK_##_lock,       \
+               .od             = TEGRA_PIN_OD_DEFAULT,         \
+               .ioreset        = TEGRA_PIN_IO_RESET_##_ioreset \
+}
+
+static int pismo_focuser_power_on(struct ad5816_power_rail *pw)
+{
+       int err;
+
+       if (unlikely(WARN_ON(!pw || !pw->vdd || !pw->vdd_i2c)))
+               return -EFAULT;
+
+       err = regulator_enable(pw->vdd_i2c);
+       if (unlikely(err))
+               goto ad5816_vdd_i2c_fail;
+
+       err = regulator_enable(pw->vdd);
+       if (unlikely(err))
+               goto ad5816_vdd_fail;
+
+       return 0;
+
+ad5816_vdd_fail:
+       regulator_disable(pw->vdd_i2c);
+
+ad5816_vdd_i2c_fail:
+       pr_err("%s FAILED\n", __func__);
+
+       return -ENODEV;
+}
+
+static int pismo_focuser_power_off(struct ad5816_power_rail *pw)
+{
+       if (unlikely(WARN_ON(!pw || !pw->vdd || !pw->vdd_i2c)))
+               return -EFAULT;
+
+       regulator_disable(pw->vdd);
+       regulator_disable(pw->vdd_i2c);
+
+       return 0;
+}
+
+static struct tegra_pingroup_config mclk_disable =
+       VI_PINMUX(CAM_MCLK, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
+
+static struct tegra_pingroup_config mclk_enable =
+       VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
+
+static struct tegra_pingroup_config pbb0_disable =
+       VI_PINMUX(GPIO_PBB0, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
+
+static struct tegra_pingroup_config pbb0_enable =
+       VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
+
+/*
+ * As a workaround, pismo_vcmvdd need to be allocated to activate the
+ * sensor devices. This is due to the focuser device(AD5816) will hook up
+ * the i2c bus if it is not powered up.
+*/
+static struct regulator *pismo_vcmvdd;
+
+static int pismo_get_vcmvdd(void)
+{
+       if (!pismo_vcmvdd) {
+               pismo_vcmvdd = regulator_get(NULL, "vdd_af_cam1");
+               if (unlikely(WARN_ON(IS_ERR(pismo_vcmvdd)))) {
+                       pr_err("%s: can't get regulator vcmvdd: %ld\n",
+                               __func__, PTR_ERR(pismo_vcmvdd));
+                       pismo_vcmvdd = NULL;
+                       return -ENODEV;
+               }
+       }
+       return 0;
+}
+
+static int pismo_imx091_power_on(struct nvc_regulator *vreg)
+{
+       int err;
+
+       if (unlikely(WARN_ON(!vreg)))
+               return -EFAULT;
+
+       if (pismo_get_vcmvdd())
+               goto imx091_poweron_fail;
+
+       gpio_set_value(CAM1_POWER_DWN_GPIO, 0);
+       usleep_range(10, 20);
+
+       err = regulator_enable(vreg[IMX091_VREG_AVDD].vreg);
+       if (err)
+               goto imx091_avdd_fail;
+
+       err = regulator_enable(vreg[IMX091_VREG_IOVDD].vreg);
+       if (err)
+               goto imx091_iovdd_fail;
+
+       usleep_range(1, 2);
+       gpio_set_value(CAM1_POWER_DWN_GPIO, 1);
+
+       err = regulator_enable(pismo_vcmvdd);
+       if (unlikely(err))
+               goto imx091_vcmvdd_fail;
+
+       tegra_pinmux_config_table(&mclk_enable, 1);
+       usleep_range(300, 310);
+
+       return 1;
+
+imx091_vcmvdd_fail:
+       regulator_disable(vreg[IMX091_VREG_IOVDD].vreg);
+
+imx091_iovdd_fail:
+       regulator_disable(vreg[IMX091_VREG_AVDD].vreg);
+
+imx091_avdd_fail:
+       gpio_set_value(CAM1_POWER_DWN_GPIO, 0);
+
+imx091_poweron_fail:
+       pr_err("%s FAILED\n", __func__);
+       return -ENODEV;
+}
+
+static int pismo_imx091_power_off(struct nvc_regulator *vreg)
+{
+       if (unlikely(WARN_ON(!vreg)))
+               return -EFAULT;
+
+       usleep_range(1, 2);
+       tegra_pinmux_config_table(&mclk_disable, 1);
+       gpio_set_value(CAM1_POWER_DWN_GPIO, 0);
+       usleep_range(1, 2);
+
+       regulator_disable(pismo_vcmvdd);
+       regulator_disable(vreg[IMX091_VREG_IOVDD].vreg);
+       regulator_disable(vreg[IMX091_VREG_AVDD].vreg);
+
+       return 1;
+}
+
+static struct nvc_imager_cap imx091_cap = {
+       .identifier             = "IMX091",
+       .sensor_nvc_interface   = 3,
+       .pixel_types[0]         = 0x100,
+       .orientation            = 0,
+       .direction              = 0,
+       .initial_clock_rate_khz = 6000,
+       .clock_profiles[0] = {
+               .external_clock_khz     = 24000,
+               .clock_multiplier       = 10416667, /* value / 1,000,000 */
+       },
+       .clock_profiles[1] = {
+               .external_clock_khz     = 0,
+               .clock_multiplier       = 0,
+       },
+       .h_sync_edge            = 0,
+       .v_sync_edge            = 0,
+       .mclk_on_vgp0           = 0,
+       .csi_port               = 0,
+       .data_lanes             = 4,
+       .virtual_channel_id     = 0,
+       .discontinuous_clk_mode = 1,
+       .cil_threshold_settle   = 0x0,
+       .min_blank_time_width   = 16,
+       .min_blank_time_height  = 16,
+       .preferred_mode_index   = 0,
+       .focuser_guid           = NVC_FOCUS_GUID(0),
+       .torch_guid             = NVC_TORCH_GUID(0),
+       .cap_version            = NVC_IMAGER_CAPABILITIES_VERSION2,
+};
+
+static struct imx091_platform_data imx091_pdata = {
+       .num                    = 0,
+       .sync                   = 0,
+       .dev_name               = "camera",
+       .gpio_count             = ARRAY_SIZE(imx091_gpio_pdata),
+       .gpio                   = imx091_gpio_pdata,
+       .flash_cap              = {
+               .sdo_trigger_enabled = 1,
+               .adjustable_flash_timing = 1,
+       },
+       .cap                    = &imx091_cap,
+       .power_on               = pismo_imx091_power_on,
+       .power_off              = pismo_imx091_power_off,
+};
+
+static struct sbs_platform_data sbs_pdata = {
+       .poll_retry_count = 100,
+       .i2c_retry_count = 2,
+};
+
+static int pismo_ov9772_power_on(struct ov9772_power_rail *pw)
+{
+       int err;
+
+       if (unlikely(!pw || !pw->avdd || !pw->dovdd))
+               return -EFAULT;
+
+       if (pismo_get_vcmvdd())
+               goto ov9772_get_vcmvdd_fail;
+
+       gpio_set_value(CAM2_POWER_DWN_GPIO, 0);
+       gpio_set_value(CAM_RSTN, 0);
+
+       err = regulator_enable(pw->avdd);
+       if (unlikely(err))
+               goto ov9772_avdd_fail;
+
+       err = regulator_enable(pw->dovdd);
+       if (unlikely(err))
+               goto ov9772_dovdd_fail;
+
+       gpio_set_value(CAM_RSTN, 1);
+       gpio_set_value(CAM2_POWER_DWN_GPIO, 1);
+
+       err = regulator_enable(pismo_vcmvdd);
+       if (unlikely(err))
+               goto ov9772_vcmvdd_fail;
+
+       tegra_pinmux_config_table(&pbb0_enable, 1);
+       usleep_range(340, 380);
+
+       /* return 1 to skip the in-driver power_on sequence */
+       return 1;
+
+ov9772_vcmvdd_fail:
+       regulator_disable(pw->dovdd);
+
+ov9772_dovdd_fail:
+       regulator_disable(pw->avdd);
+
+ov9772_avdd_fail:
+       gpio_set_value(CAM_RSTN, 0);
+       gpio_set_value(CAM2_POWER_DWN_GPIO, 0);
+
+ov9772_get_vcmvdd_fail:
+       pr_err("%s FAILED\n", __func__);
+       return -ENODEV;
+}
+
+static int pismo_ov9772_power_off(struct ov9772_power_rail *pw)
+{
+       if (unlikely(!pw || !pismo_vcmvdd || !pw->avdd || !pw->dovdd))
+               return -EFAULT;
+
+       usleep_range(21, 25);
+       tegra_pinmux_config_table(&pbb0_disable, 1);
+
+       gpio_set_value(CAM2_POWER_DWN_GPIO, 0);
+       gpio_set_value(CAM_RSTN, 0);
+
+       regulator_disable(pismo_vcmvdd);
+       regulator_disable(pw->dovdd);
+       regulator_disable(pw->avdd);
+
+       /* return 1 to skip the in-driver power_off sequence */
+       return 1;
+}
+
+static struct nvc_gpio_pdata ov9772_gpio_pdata[] = {
+       { OV9772_GPIO_TYPE_SHTDN, CAM2_POWER_DWN_GPIO, true, 0, },
+       { OV9772_GPIO_TYPE_PWRDN, CAM_RSTN, true, 0, },
+};
+
+static struct ov9772_platform_data pismo_ov9772_pdata = {
+       .num            = 1,
+       .dev_name       = "camera",
+       .gpio_count     = ARRAY_SIZE(ov9772_gpio_pdata),
+       .gpio           = ov9772_gpio_pdata,
+       .power_on       = pismo_ov9772_power_on,
+       .power_off      = pismo_ov9772_power_off,
+};
+
+static int pismo_as3648_power_on(struct as364x_power_rail *pw)
+{
+       int err = pismo_get_vcmvdd();
+
+       if (err)
+               return err;
+
+       return regulator_enable(pismo_vcmvdd);
+}
+
+static int pismo_as3648_power_off(struct as364x_power_rail *pw)
+{
+       if (!pismo_vcmvdd)
+               return -ENODEV;
+
+       return regulator_disable(pismo_vcmvdd);
+}
+
+static struct as364x_platform_data pismo_as3648_pdata = {
+       .config         = {
+               .max_total_current_mA = 1000,
+               .max_peak_current_mA = 600,
+               .vin_low_v_run_mV = 3070,
+               .strobe_type = 1,
+               },
+       .pinstate       = {
+               .mask   = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0),
+               .values = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0)
+               },
+       .dev_name       = "torch",
+       .type           = AS3648,
+       .gpio_strobe    = CAM_FLASH_STROBE,
+       .led_mask       = 3,
+
+       .power_on_callback = pismo_as3648_power_on,
+       .power_off_callback = pismo_as3648_power_off,
+};
+
+static struct ad5816_platform_data pismo_ad5816_pdata = {
+       .cfg = 0,
+       .num = 0,
+       .sync = 0,
+       .dev_name = "focuser",
+       .power_on = pismo_focuser_power_on,
+       .power_off = pismo_focuser_power_off,
+};
+
+static struct i2c_board_info pismo_i2c_board_info_e1625[] = {
+       {
+               I2C_BOARD_INFO("imx091", 0x36),
+               .platform_data = &imx091_pdata,
+       },
+       {
+               I2C_BOARD_INFO("ov9772", 0x10),
+               .platform_data = &pismo_ov9772_pdata,
+       },
+       {
+               I2C_BOARD_INFO("as3648", 0x30),
+               .platform_data = &pismo_as3648_pdata,
+       },
+       {
+               I2C_BOARD_INFO("ad5816", 0x0E),
+               .platform_data = &pismo_ad5816_pdata,
+       },
+};
+
+static int pismo_camera_init(void)
+{
+       tegra_pinmux_config_table(&mclk_disable, 1);
+       tegra_pinmux_config_table(&pbb0_disable, 1);
+
+       i2c_register_board_info(2, pismo_i2c_board_info_e1625,
+               ARRAY_SIZE(pismo_i2c_board_info_e1625));
+       return 0;
+}
+
+/* MPU board file definition   */
+static struct mpu_platform_data mpu9150_gyro_data = {
+       .int_config     = 0x10,
+       .level_shifter  = 0,
+       /* Located in board_[platformname].h */
+       .orientation    = MPU_GYRO_ORIENTATION,
+       .sec_slave_type = SECONDARY_SLAVE_TYPE_COMPASS,
+       .sec_slave_id   = COMPASS_ID_AK8975,
+       .secondary_i2c_addr     = MPU_COMPASS_ADDR,
+       .secondary_read_reg     = 0x06,
+       .secondary_orientation  = MPU_COMPASS_ORIENTATION,
+       .key            = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
+                          0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
+};
+
+#define TEGRA_CAMERA_GPIO(_gpio, _label, _value)               \
+       {                                                       \
+               .gpio = _gpio,                                  \
+               .label = _label,                                \
+               .value = _value,                                \
+       }
+
+static struct i2c_board_info pismo_i2c_board_info_cm3218[] = {
+       {
+               I2C_BOARD_INFO("cm3218", 0x48),
+       },
+};
+
+static struct i2c_board_info __initdata inv_mpu9150_i2c2_board_info[] = {
+       {
+               I2C_BOARD_INFO(MPU_GYRO_NAME, MPU_GYRO_ADDR),
+               .platform_data = &mpu9150_gyro_data,
+       },
+};
+
+static void mpuirq_init(void)
+{
+       int ret = 0;
+       unsigned gyro_irq_gpio = MPU_GYRO_IRQ_GPIO;
+       unsigned gyro_bus_num = MPU_GYRO_BUS_NUM;
+       char *gyro_name = MPU_GYRO_NAME;
+
+       pr_info("*** MPU START *** mpuirq_init...\n");
+
+       ret = gpio_request(gyro_irq_gpio, gyro_name);
+
+       if (ret < 0) {
+               pr_err("%s: gpio_request failed %d\n", __func__, ret);
+               return;
+       }
+
+       ret = gpio_direction_input(gyro_irq_gpio);
+       if (ret < 0) {
+               pr_err("%s: gpio_direction_input failed %d\n", __func__, ret);
+               gpio_free(gyro_irq_gpio);
+               return;
+       }
+       pr_info("*** MPU END *** mpuirq_init...\n");
+
+       inv_mpu9150_i2c2_board_info[0].irq = gpio_to_irq(MPU_GYRO_IRQ_GPIO);
+       i2c_register_board_info(gyro_bus_num, inv_mpu9150_i2c2_board_info,
+               ARRAY_SIZE(inv_mpu9150_i2c2_board_info));
+}
+
+static int pismo_nct1008_init(void)
+{
+       int nct1008_port = -1;
+       int ret = 0;
+
+       nct1008_port = TEGRA_GPIO_PX6;
+
+       if (nct1008_port >= 0) {
+               struct nct1008_platform_data *data = &pismo_nct1008_pdata;
+#ifdef CONFIG_TEGRA_EDP_LIMITS
+               const struct tegra_edp_limits *cpu_edp_limits;
+               int cpu_edp_limits_size;
+               int i;
+               int trip;
+               struct nct_trip_temp *trip_state;
+
+               /* edp capping */
+               tegra_get_cpu_edp_limits(&cpu_edp_limits, &cpu_edp_limits_size);
+
+               if (cpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
+                       BUG();
+
+               for (i = 0; i < cpu_edp_limits_size-1; i++) {
+                       trip = data->num_trips;
+                       trip_state = &data->trips[trip];
+
+                       trip_state->cdev_type = "edp";
+                       trip_state->trip_temp =
+                                       cpu_edp_limits[i].temperature * 1000;
+                       trip_state->trip_type = THERMAL_TRIP_ACTIVE;
+                       trip_state->state = i + 1;
+                       trip_state->hysteresis = 1000;
+
+                       data->num_trips++;
+
+                       if (data->num_trips > NCT_MAX_TRIPS)
+                               BUG();
+               }
+#endif
+               nct1008_add_cdev_trips(data, tegra_core_edp_get_cdev());
+               nct1008_add_cdev_trips(data, tegra_dvfs_get_cpu_dfll_cdev());
+
+               pismo_i2c4_nct1008_board_info[0].irq =
+                               gpio_to_irq(nct1008_port);
+               pr_info("%s: pismo nct1008 irq %d", __func__,
+                               pismo_i2c4_nct1008_board_info[0].irq);
+
+               ret = gpio_request(nct1008_port, "temp_alert");
+               if (ret < 0)
+                       return ret;
+
+               ret = gpio_direction_input(nct1008_port);
+               if (ret < 0) {
+                       pr_info("%s: calling gpio_free(nct1008_port)",
+                                       __func__);
+                       gpio_free(nct1008_port);
+               }
+       }
+
+       /* pismo has thermal sensor on GEN1-I2C i.e. instance 0 */
+       i2c_register_board_info(0, pismo_i2c4_nct1008_board_info,
+               ARRAY_SIZE(pismo_i2c4_nct1008_board_info));
+
+       return ret;
+}
+
+static struct i2c_board_info __initdata bq20z45_pdata[] = {
+       {
+               I2C_BOARD_INFO("sbs-battery", 0x0B),
+               .platform_data = &sbs_pdata,
+       },
+};
+
+#ifdef CONFIG_TEGRA_SKIN_THROTTLE
+static int tegra_skin_match(struct thermal_zone_device *thz, void *data)
+{
+       return strcmp((char *)data, thz->type) == 0;
+}
+
+static int tegra_skin_get_temp(void *data, long *temp)
+{
+       struct thermal_zone_device *thz;
+
+       thz = thermal_zone_device_find(data, tegra_skin_match);
+
+       if (!thz || thz->ops->get_temp(thz, temp))
+               *temp = 25000;
+
+       return 0;
+}
+
+static struct therm_est_data skin_data = {
+       .toffset = 9793,
+       .polling_period = 1100,
+       .ndevs = 2,
+       .devs = {
+                       {
+                               .dev_data = "nct_ext",
+                               .get_temp = tegra_skin_get_temp,
+                               .coeffs = {
+                                       2, 1, 1, 1,
+                                       1, 1, 1, 1,
+                                       1, 1, 1, 0,
+                                       1, 1, 0, 0,
+                                       0, 0, -1, -7
+                               },
+                       },
+                       {
+                               .dev_data = "nct_int",
+                               .get_temp = tegra_skin_get_temp,
+                               .coeffs = {
+                                       -11, -7, -5, -3,
+                                       -3, -2, -1, 0,
+                                       0, 0, 1, 1,
+                                       1, 2, 2, 3,
+                                       4, 6, 11, 18
+                               },
+                       },
+       },
+       .trip_temp = 43000,
+       .tc1 = 1,
+       .tc2 = 15,
+       .passive_delay = 15000,
+};
+
+static struct balanced_throttle skin_throttle = {
+       .throt_tab_size = 6,
+       .throt_tab = {
+               { 640000, 1200 },
+               { 640000, 1200 },
+               { 760000, 1200 },
+               { 760000, 1200 },
+               {1000000, 1200 },
+               {1000000, 1200 },
+       },
+};
+
+static int __init pismo_skin_init(void)
+{
+       struct thermal_cooling_device *skin_cdev;
+
+       skin_cdev = balanced_throttle_register(&skin_throttle, "pismo-skin");
+
+       skin_data.cdev = skin_cdev;
+       tegra_skin_therm_est_device.dev.platform_data = &skin_data;
+       platform_device_register(&tegra_skin_therm_est_device);
+
+       return 0;
+}
+late_initcall(pismo_skin_init);
+#endif
+
+int __init pismo_sensors_init(void)
+{
+       int err;
+
+       err = pismo_nct1008_init();
+       if (err)
+               return err;
+
+       pismo_camera_init();
+       mpuirq_init();
+
+       i2c_register_board_info(0, pismo_i2c_board_info_cm3218,
+               ARRAY_SIZE(pismo_i2c_board_info_cm3218));
+
+       i2c_register_board_info(0, bq20z45_pdata,
+               ARRAY_SIZE(bq20z45_pdata));
+
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-pismo.c b/arch/arm/mach-tegra/board-pismo.c
new file mode 100644 (file)
index 0000000..67d14a1
--- /dev/null
@@ -0,0 +1,829 @@
+/*
+ * arch/arm/mach-tegra/board-pismo.c
+ *
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/i2c-tegra.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/platform_data/tegra_usb.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/rm31080a_ts.h>
+#include <linux/tegra_uart.h>
+#include <linux/memblock.h>
+#include <linux/spi-tegra.h>
+#include <linux/nfc/pn544.h>
+#include <linux/rfkill-gpio.h>
+#include <linux/skbuff.h>
+#include <linux/ti_wilink_st.h>
+#include <linux/regulator/consumer.h>
+#include <linux/smb349-charger.h>
+#include <linux/max17048_battery.h>
+#include <linux/leds.h>
+#include <linux/i2c/at24.h>
+#include <linux/of_platform.h>
+#include <linux/edp.h>
+
+#include <asm/hardware/gic.h>
+
+#include <mach/clk.h>
+#include <mach/irqs.h>
+#include <mach/pinmux.h>
+#include <mach/pinmux-tegra30.h>
+#include <mach/io_dpd.h>
+#include <mach/i2s.h>
+#include <mach/tegra_asoc_pdata.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/usb_phy.h>
+#include <mach/gpio-tegra.h>
+#include <mach/tegra_fiq_debugger.h>
+#include <mach/tegra_usb_modem_power.h>
+
+#include "board-touch-raydium.h"
+#include "board.h"
+#include "board-common.h"
+#include "clock.h"
+#include "board-pismo.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "fuse.h"
+#include "pm.h"
+#include "pm-irq.h"
+#include "common.h"
+#include "tegra-board-id.h"
+#include "iomap.h"
+
+#ifdef CONFIG_BT_BLUESLEEP
+static struct rfkill_gpio_platform_data pismo_bt_rfkill_pdata = {
+               .name           = "bt_rfkill",
+               .shutdown_gpio  = TEGRA_GPIO_PQ7,
+               .reset_gpio     = TEGRA_GPIO_PQ6,
+               .type           = RFKILL_TYPE_BLUETOOTH,
+};
+
+static struct platform_device pismo_bt_rfkill_device = {
+       .name = "rfkill_gpio",
+       .id             = -1,
+       .dev = {
+               .platform_data = &pismo_bt_rfkill_pdata,
+       },
+};
+
+static struct resource pismo_bluesleep_resources[] = {
+       [0] = {
+               .name = "gpio_host_wake",
+                       .start  = TEGRA_GPIO_PU6,
+                       .end    = TEGRA_GPIO_PU6,
+                       .flags  = IORESOURCE_IO,
+       },
+       [1] = {
+               .name = "gpio_ext_wake",
+                       .start  = TEGRA_GPIO_PEE1,
+                       .end    = TEGRA_GPIO_PEE1,
+                       .flags  = IORESOURCE_IO,
+       },
+       [2] = {
+               .name = "host_wake",
+                       .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+       },
+};
+
+static struct platform_device pismo_bluesleep_device = {
+       .name           = "bluesleep",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(pismo_bluesleep_resources),
+       .resource       = pismo_bluesleep_resources,
+};
+
+static noinline void __init pismo_setup_bt_rfkill(void)
+{
+       platform_device_register(&pismo_bt_rfkill_device);
+}
+
+static noinline void __init pismo_setup_bluesleep(void)
+{
+       pismo_bluesleep_resources[2].start =
+               pismo_bluesleep_resources[2].end =
+                       gpio_to_irq(TEGRA_GPIO_PU6);
+       platform_device_register(&pismo_bluesleep_device);
+       return;
+}
+#elif defined CONFIG_BLUEDROID_PM
+static struct resource pismo_bluedroid_pm_resources[] = {
+       [0] = {
+               .name   = "shutdown_gpio",
+               .start  = TEGRA_GPIO_PQ7,
+               .end    = TEGRA_GPIO_PQ7,
+               .flags  = IORESOURCE_IO,
+       },
+       [1] = {
+               .name = "host_wake",
+               .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+       },
+       [2] = {
+               .name = "gpio_ext_wake",
+               .start  = TEGRA_GPIO_PEE1,
+               .end    = TEGRA_GPIO_PEE1,
+               .flags  = IORESOURCE_IO,
+       },
+       [3] = {
+               .name = "gpio_host_wake",
+               .start  = TEGRA_GPIO_PU6,
+               .end    = TEGRA_GPIO_PU6,
+               .flags  = IORESOURCE_IO,
+       },
+       [4] = {
+               .name = "reset_gpio",
+               .start  = TEGRA_GPIO_PQ6,
+               .end    = TEGRA_GPIO_PQ6,
+               .flags  = IORESOURCE_IO,
+       },
+};
+
+static struct platform_device pismo_bluedroid_pm_device = {
+       .name = "bluedroid_pm",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(pismo_bluedroid_pm_resources),
+       .resource       = pismo_bluedroid_pm_resources,
+};
+
+static noinline void __init pismo_setup_bluedroid_pm(void)
+{
+       pismo_bluedroid_pm_resources[1].start =
+               pismo_bluedroid_pm_resources[1].end =
+                               gpio_to_irq(TEGRA_GPIO_PU6);
+       platform_device_register(&pismo_bluedroid_pm_device);
+}
+#endif
+
+static __initdata struct tegra_clk_init_table pismo_clk_init_table[] = {
+       /* name         parent          rate            enabled */
+       { "pll_m",      NULL,           0,              false},
+       { "hda",        "pll_p",        108000000,      false},
+       { "hda2codec_2x", "pll_p",      48000000,       false},
+       { "pwm",        "pll_p",        3187500,        false},
+       { "blink",      "clk_32k",      32768,          true},
+       { "i2s1",       "pll_a_out0",   0,              false},
+       { "i2s3",       "pll_a_out0",   0,              false},
+       { "i2s4",       "pll_a_out0",   0,              false},
+       { "spdif_out",  "pll_a_out0",   0,              false},
+       { "d_audio",    "clk_m",        12000000,       false},
+       { "dam0",       "clk_m",        12000000,       false},
+       { "dam1",       "clk_m",        12000000,       false},
+       { "dam2",       "clk_m",        12000000,       false},
+       { "audio1",     "i2s1_sync",    0,              false},
+       { "audio3",     "i2s3_sync",    0,              false},
+       /* Setting vi_sensor-clk to true for validation purpose, will imapact
+        * power, later set to be false.*/
+       { "vi_sensor",  "pll_p",        150000000,      false},
+       { "cilab",      "pll_p",        150000000,      false},
+       { "cilcd",      "pll_p",        150000000,      false},
+       { "cile",       "pll_p",        150000000,      false},
+       { "i2c1",       "pll_p",        3200000,        false},
+       { "i2c2",       "pll_p",        3200000,        false},
+       { "i2c3",       "pll_p",        3200000,        false},
+       { "i2c4",       "pll_p",        3200000,        false},
+       { "i2c5",       "pll_p",        3200000,        false},
+       { NULL,         NULL,           0,              0},
+};
+
+static struct tegra_i2c_platform_data pismo_i2c1_platform_data = {
+       .adapter_nr     = 0,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 100000, 0 },
+       .scl_gpio               = {TEGRA_GPIO_I2C1_SCL, 0},
+       .sda_gpio               = {TEGRA_GPIO_I2C1_SDA, 0},
+       .arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data pismo_i2c2_platform_data = {
+       .adapter_nr     = 1,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 100000, 0 },
+       .is_clkon_always = true,
+       .scl_gpio               = {TEGRA_GPIO_I2C2_SCL, 0},
+       .sda_gpio               = {TEGRA_GPIO_I2C2_SDA, 0},
+       .arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data pismo_i2c3_platform_data = {
+       .adapter_nr     = 2,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 100000, 0 },
+       .scl_gpio               = {TEGRA_GPIO_I2C3_SCL, 0},
+       .sda_gpio               = {TEGRA_GPIO_I2C3_SDA, 0},
+       .arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data pismo_i2c4_platform_data = {
+       .adapter_nr     = 3,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 10000, 0 },
+       .scl_gpio               = {TEGRA_GPIO_I2C4_SCL, 0},
+       .sda_gpio               = {TEGRA_GPIO_I2C4_SDA, 0},
+       .arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data pismo_i2c5_platform_data = {
+       .adapter_nr     = 4,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 400000, 0 },
+       .scl_gpio               = {TEGRA_GPIO_I2C5_SCL, 0},
+       .sda_gpio               = {TEGRA_GPIO_I2C5_SDA, 0},
+       .arb_recovery = arb_lost_recovery,
+};
+
+static struct i2c_board_info __initdata rt5640_board_info = {
+       I2C_BOARD_INFO("rt5640", 0x1c),
+};
+
+static struct pn544_i2c_platform_data nfc_pdata = {
+       .irq_gpio = TEGRA_GPIO_PW2,
+       .ven_gpio = TEGRA_GPIO_PQ3,
+       .firm_gpio = TEGRA_GPIO_PH0,
+};
+
+static struct i2c_board_info __initdata nfc_board_info = {
+       I2C_BOARD_INFO("pn544", 0x28),
+       .platform_data = &nfc_pdata,
+};
+
+static void pismo_i2c_init(void)
+{
+
+       tegra11_i2c_device1.dev.platform_data = &pismo_i2c1_platform_data;
+       tegra11_i2c_device2.dev.platform_data = &pismo_i2c2_platform_data;
+       tegra11_i2c_device3.dev.platform_data = &pismo_i2c3_platform_data;
+       tegra11_i2c_device4.dev.platform_data = &pismo_i2c4_platform_data;
+       tegra11_i2c_device5.dev.platform_data = &pismo_i2c5_platform_data;
+
+       nfc_board_info.irq = gpio_to_irq(TEGRA_GPIO_PW2);
+       i2c_register_board_info(0, &nfc_board_info, 1);
+
+       platform_device_register(&tegra11_i2c_device5);
+       platform_device_register(&tegra11_i2c_device4);
+       platform_device_register(&tegra11_i2c_device3);
+       platform_device_register(&tegra11_i2c_device2);
+       platform_device_register(&tegra11_i2c_device1);
+
+       i2c_register_board_info(0, &rt5640_board_info, 1);
+}
+
+static struct platform_device *pismo_uart_devices[] __initdata = {
+       &tegra_uarta_device,
+       &tegra_uartb_device,
+       &tegra_uartc_device,
+       &tegra_uartd_device,
+};
+static struct uart_clk_parent uart_parent_clk[] = {
+       [0] = {.name = "clk_m"},
+       [1] = {.name = "pll_p"},
+#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
+       [2] = {.name = "pll_m"},
+#endif
+};
+
+static struct tegra_uart_platform_data pismo_uart_pdata;
+static struct tegra_uart_platform_data pismo_loopback_uart_pdata;
+
+static void __init uart_debug_init(void)
+{
+       int debug_port_id;
+
+       debug_port_id = uart_console_debug_init(3);
+       if (debug_port_id < 0)
+               return;
+
+       pismo_uart_devices[debug_port_id] = uart_console_debug_device;
+}
+
+static void __init pismo_uart_init(void)
+{
+       struct clk *c;
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
+               c = tegra_get_clock_by_name(uart_parent_clk[i].name);
+               if (IS_ERR_OR_NULL(c)) {
+                       pr_err("Not able to get the clock for %s\n",
+                                               uart_parent_clk[i].name);
+                       continue;
+               }
+               uart_parent_clk[i].parent_clk = c;
+               uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
+       }
+       pismo_uart_pdata.parent_clk_list = uart_parent_clk;
+       pismo_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
+       pismo_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
+       pismo_loopback_uart_pdata.parent_clk_count =
+                                               ARRAY_SIZE(uart_parent_clk);
+       pismo_loopback_uart_pdata.is_loopback = true;
+       tegra_uarta_device.dev.platform_data = &pismo_uart_pdata;
+       tegra_uartb_device.dev.platform_data = &pismo_uart_pdata;
+       tegra_uartc_device.dev.platform_data = &pismo_uart_pdata;
+       tegra_uartd_device.dev.platform_data = &pismo_uart_pdata;
+
+       /* Register low speed only if it is selected */
+       if (!is_tegra_debug_uartport_hs())
+               uart_debug_init();
+
+       platform_add_devices(pismo_uart_devices,
+                               ARRAY_SIZE(pismo_uart_devices));
+}
+
+static struct resource tegra_rtc_resources[] = {
+       [0] = {
+               .start = TEGRA_RTC_BASE,
+               .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start = INT_RTC,
+               .end = INT_RTC,
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device tegra_rtc_device = {
+       .name = "tegra_rtc",
+       .id   = -1,
+       .resource = tegra_rtc_resources,
+       .num_resources = ARRAY_SIZE(tegra_rtc_resources),
+};
+
+static struct tegra_asoc_platform_data pismo_audio_pdata = {
+       .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
+       .gpio_hp_det            = TEGRA_GPIO_HP_DET,
+       .gpio_hp_mute           = -1,
+       .gpio_int_mic_en        = TEGRA_GPIO_INT_MIC_EN,
+       .gpio_ext_mic_en        = TEGRA_GPIO_EXT_MIC_EN,
+       .gpio_ldo1_en           = TEGRA_GPIO_LDO1_EN,
+       .gpio_codec1 = TEGRA_GPIO_CODEC1_EN,
+       .gpio_codec2 = TEGRA_GPIO_CODEC2_EN,
+       .gpio_codec3 = TEGRA_GPIO_CODEC3_EN,
+       .i2s_param[HIFI_CODEC]  = {
+               .audio_port_id  = 1,
+               .is_i2s_master  = 1,
+               .i2s_mode       = TEGRA_DAIFMT_I2S,
+       },
+       .i2s_param[BT_SCO]      = {
+               .audio_port_id  = 3,
+               .is_i2s_master  = 1,
+               .i2s_mode       = TEGRA_DAIFMT_DSP_A,
+       },
+};
+
+static struct platform_device pismo_audio_device = {
+       .name   = "tegra-snd-rt5640",
+       .id     = 0,
+       .dev    = {
+               .platform_data = &pismo_audio_pdata,
+       },
+};
+
+static struct platform_device tegra_camera = {
+       .name = "tegra_camera",
+       .id = -1,
+};
+
+static struct platform_device *pismo_devices[] __initdata = {
+       &tegra_pmu_device,
+       &tegra_rtc_device,
+       &tegra_udc_device,
+#if defined(CONFIG_TEGRA_AVP)
+       &tegra_avp_device,
+#endif
+       &tegra_camera,
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
+       &tegra11_se_device,
+#endif
+       &tegra_ahub_device,
+       &tegra_dam_device0,
+       &tegra_dam_device1,
+       &tegra_dam_device2,
+       &tegra_i2s_device1,
+       &tegra_i2s_device3,
+       &tegra_i2s_device4,
+       &tegra_spdif_device,
+       &spdif_dit_device,
+       &bluetooth_dit_device,
+       &tegra_pcm_device,
+       &pismo_audio_device,
+       &tegra_hda_device,
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
+       &tegra_aes_device,
+#endif
+};
+
+#ifdef CONFIG_USB_SUPPORT
+static struct tegra_usb_platform_data tegra_udc_pdata = {
+       .port_otg = true,
+       .has_hostpc = true,
+       .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+       .op_mode = TEGRA_USB_OPMODE_DEVICE,
+       .u_data.dev = {
+               .vbus_pmu_irq = 0,
+               .vbus_gpio = -1,
+               .charging_supported = false,
+               .remote_wakeup_supported = false,
+       },
+       .u_cfg.utmi = {
+               .hssync_start_delay = 0,
+               .elastic_limit = 16,
+               .idle_wait_delay = 17,
+               .term_range_adj = 6,
+               .xcvr_setup = 8,
+               .xcvr_lsfslew = 2,
+               .xcvr_lsrslew = 2,
+               .xcvr_setup_offset = 0,
+               .xcvr_use_fuses = 1,
+       },
+};
+
+static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
+       .port_otg = true,
+       .has_hostpc = true,
+       .unaligned_dma_buf_supported = false,
+       .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+       .op_mode = TEGRA_USB_OPMODE_HOST,
+       .u_data.host = {
+               .vbus_gpio = -1,
+               .hot_plug = false,
+               .remote_wakeup_supported = true,
+               .power_off_on_suspend = true,
+       },
+       .u_cfg.utmi = {
+               .hssync_start_delay = 0,
+               .elastic_limit = 16,
+               .idle_wait_delay = 17,
+               .term_range_adj = 6,
+               .xcvr_setup = 15,
+               .xcvr_lsfslew = 2,
+               .xcvr_lsrslew = 2,
+               .xcvr_setup_offset = 0,
+               .xcvr_use_fuses = 1,
+               .vbus_oc_map = 0x4,
+       },
+};
+
+static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
+       .port_otg = false,
+       .has_hostpc = true,
+       .unaligned_dma_buf_supported = false,
+       .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+       .op_mode = TEGRA_USB_OPMODE_HOST,
+       .u_data.host = {
+               .vbus_gpio = -1,
+               .hot_plug = false,
+               .remote_wakeup_supported = true,
+               .power_off_on_suspend = true,
+       },
+       .u_cfg.utmi = {
+       .hssync_start_delay = 0,
+               .elastic_limit = 16,
+               .idle_wait_delay = 17,
+               .term_range_adj = 6,
+               .xcvr_setup = 8,
+               .xcvr_lsfslew = 2,
+               .xcvr_lsrslew = 2,
+               .xcvr_setup_offset = 0,
+               .xcvr_use_fuses = 1,
+               .vbus_oc_map = 0x5,
+       },
+};
+
+static struct tegra_usb_otg_data tegra_otg_pdata = {
+       .ehci_device = &tegra_ehci1_device,
+       .ehci_pdata = &tegra_ehci1_utmi_pdata,
+};
+
+static void pismo_usb_init(void)
+{
+       int usb_port_owner_info = tegra_get_usb_port_owner_info();
+
+       /* Set USB wake sources for pismo */
+       tegra_set_usb_wake_source();
+
+       if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
+               tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
+               platform_device_register(&tegra_otg_device);
+               /* Setup the udc platform data */
+               tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
+       }
+
+       if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
+               tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
+               platform_device_register(&tegra_ehci3_device);
+       }
+}
+
+static struct gpio modem_gpios[] = { /* Nemo modem */
+       {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"},
+       {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"},
+};
+
+static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = {
+       .port_otg = false,
+       .has_hostpc = true,
+       .unaligned_dma_buf_supported = false,
+       .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
+       .op_mode = TEGRA_USB_OPMODE_HOST,
+       .u_data.host = {
+               .vbus_gpio = -1,
+               .hot_plug = false,
+               .remote_wakeup_supported = true,
+               .power_off_on_suspend = true,
+       },
+};
+
+static int baseband_init(void)
+{
+       int ret;
+
+       ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios));
+       if (ret) {
+               pr_warn("%s:gpio request failed\n", __func__);
+               return ret;
+       }
+
+       /* enable pull-down for MDM_COLD_BOOT */
+       tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_KB_COL5,
+                                   TEGRA_PUPD_PULL_DOWN);
+
+       /* export GPIO for user space access through sysfs */
+       gpio_export(MDM_RST, false);
+
+       return 0;
+}
+
+static const struct tegra_modem_operations baseband_operations = {
+       .init = baseband_init,
+};
+
+static struct tegra_usb_modem_power_platform_data baseband_pdata = {
+       .ops = &baseband_operations,
+       .wake_gpio = -1,
+       .boot_gpio = MDM_COLDBOOT,
+       .boot_irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+       .autosuspend_delay = 2000,
+       .short_autosuspend_delay = 50,
+       .tegra_ehci_device = &tegra_ehci2_device,
+       .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata,
+};
+
+static struct platform_device icera_nemo_device = {
+       .name = "tegra_usb_modem_power",
+       .id = -1,
+       .dev = {
+               .platform_data = &baseband_pdata,
+       },
+};
+
+static void pismo_modem_init(void)
+{
+       int modem_id = tegra_get_modem_id();
+       int usb_port_owner_info = tegra_get_usb_port_owner_info();
+       switch (modem_id) {
+       case TEGRA_BB_NEMO: /* on board i500 HSIC */
+               if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB))
+                       platform_device_register(&icera_nemo_device);
+               break;
+       }
+}
+
+#else
+static void pismo_usb_init(void) { }
+static void pismo_modem_init(void) { }
+#endif
+
+static void pismo_audio_init(void)
+{
+       pismo_audio_pdata.codec_name = "rt5640.0-001c";
+       pismo_audio_pdata.codec_dai_name = "rt5640-aif1";
+}
+
+
+static struct platform_device *pismo_spi_devices[] __initdata = {
+       &tegra11_spi_device4,
+};
+
+struct spi_clk_parent spi_parent_clk_pismo[] = {
+       [0] = {.name = "pll_p"},
+#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
+       [1] = {.name = "pll_m"},
+       [2] = {.name = "clk_m"},
+#else
+       [1] = {.name = "clk_m"},
+#endif
+};
+
+static struct tegra_spi_platform_data pismo_spi_pdata = {
+       .is_dma_based           = false,
+       .max_dma_buffer         = 16 * 1024,
+       .is_clkon_always        = false,
+       .max_rate               = 25000000,
+};
+
+static void __init pismo_spi_init(void)
+{
+       int i;
+       struct clk *c;
+       struct board_info display_board_info;
+
+       tegra_get_display_board_info(&display_board_info);
+
+       for (i = 0; i < ARRAY_SIZE(spi_parent_clk_pismo); ++i) {
+               c = tegra_get_clock_by_name(spi_parent_clk_pismo[i].name);
+               if (IS_ERR_OR_NULL(c)) {
+                       pr_err("Not able to get the clock for %s\n",
+                                       spi_parent_clk_pismo[i].name);
+                       continue;
+               }
+               spi_parent_clk_pismo[i].parent_clk = c;
+               spi_parent_clk_pismo[i].fixed_clk_rate = clk_get_rate(c);
+       }
+       pismo_spi_pdata.parent_clk_list = spi_parent_clk_pismo;
+       pismo_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk_pismo);
+       tegra11_spi_device4.dev.platform_data = &pismo_spi_pdata;
+       platform_add_devices(pismo_spi_devices,
+                       ARRAY_SIZE(pismo_spi_devices));
+}
+
+static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
+       /* name         parent          rate            enabled */
+       { "extern2",    "pll_p",        41000000,       false},
+       { "clk_out_2",  "extern2",      40800000,       false},
+       { NULL,         NULL,           0,              0},
+};
+
+struct rm_spi_ts_platform_data rm31080ts_pismo_data = {
+       .gpio_reset = 0,
+       .config = 0,
+       .platform_id = RM_PLATFORM_D010,
+       .name_of_clock = "clk_out_2",
+};
+
+static struct tegra_spi_device_controller_data dev_cdata = {
+       .rx_clk_tap_delay = 0,
+       .tx_clk_tap_delay = 16,
+};
+
+struct spi_board_info rm31080a_pismo_spi_board[1] = {
+       {
+               .modalias = "rm_ts_spidev",
+               .bus_num = 3,
+               .chip_select = 2,
+               .max_speed_hz = 12 * 1000 * 1000,
+               .mode = SPI_MODE_0,
+               .controller_data = &dev_cdata,
+               .platform_data = &rm31080ts_pismo_data,
+       },
+};
+
+#ifdef CONFIG_EDP_FRAMEWORK
+static struct edp_manager battery_edp_manager = {
+       .name = "battery",
+       .imax = 2500
+};
+
+static void __init pismo_battery_edp_init(void)
+{
+       struct edp_governor *g;
+       int r;
+
+       r = edp_register_manager(&battery_edp_manager);
+       if (r)
+               goto err_ret;
+
+       /* start with priority governor */
+       g = edp_get_governor("priority");
+       if (!g) {
+               r = -EFAULT;
+               goto err_ret;
+       }
+
+       r = edp_set_governor(&battery_edp_manager, g);
+       if (r)
+               goto err_ret;
+
+       return;
+
+err_ret:
+       pr_err("Battery EDP init failed with error %d\n", r);
+       WARN_ON(1);
+}
+#else
+static inline void pismo_battery_edp_init(void) {}
+#endif
+static void __init tegra_pismo_init(void)
+{
+       struct board_info board_info;
+
+       tegra_get_display_board_info(&board_info);
+       pismo_battery_edp_init();
+       tegra_clk_init_from_table(pismo_clk_init_table);
+       tegra_clk_vefify_parents();
+       tegra_smmu_init();
+       tegra_soc_device_init("pismo");
+       tegra_enable_pinmux();
+       pismo_pinmux_init();
+       pismo_i2c_init();
+       pismo_spi_init();
+       pismo_usb_init();
+       pismo_uart_init();
+       pismo_audio_init();
+       platform_add_devices(pismo_devices, ARRAY_SIZE(pismo_devices));
+       tegra_ram_console_debug_init();
+       tegra_io_dpd_init();
+       pismo_regulator_init();
+       pismo_sdhci_init();
+       pismo_suspend_init();
+       pismo_emc_init();
+       pismo_edp_init();
+       pismo_panel_init();
+       pismo_pmon_init();
+#ifdef CONFIG_BT_BLUESLEEP
+       pismo_setup_bluesleep();
+       pismo_setup_bt_rfkill();
+#elif defined CONFIG_BLUEDROID_PM
+       pismo_setup_bluedroid_pm();
+#endif
+       tegra_release_bootloader_fb();
+       pismo_modem_init();
+#ifdef CONFIG_TEGRA_WDT_RECOVERY
+       tegra_wdt_recovery_init();
+#endif
+       tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
+       pismo_sensors_init();
+       pismo_soctherm_init();
+}
+
+static void __init pismo_ramconsole_reserve(unsigned long size)
+{
+       tegra_ram_console_debug_reserve(SZ_1M);
+}
+
+static void __init tegra_pismo_dt_init(void)
+{
+       tegra_pismo_init();
+
+#ifdef CONFIG_USE_OF
+       of_platform_populate(NULL,
+               of_default_bus_match_table, NULL, NULL);
+#endif
+}
+
+static void __init tegra_pismo_reserve(void)
+{
+#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
+       /* 1920*1200*4*2 = 18432000 bytes */
+       tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M);
+#else
+       tegra_reserve(SZ_128M, SZ_16M + SZ_2M, SZ_4M);
+#endif
+       pismo_ramconsole_reserve(SZ_1M);
+}
+
+static const char * const pismo_dt_board_compat[] = {
+       "nvidia,pismo",
+       NULL
+};
+
+MACHINE_START(PISMO, "pismo")
+       .atag_offset    = 0x100,
+       .soc            = &tegra_soc_desc,
+       .map_io         = tegra_map_common_io,
+       .reserve        = tegra_pismo_reserve,
+       .init_early     = tegra11x_init_early,
+       .init_irq       = tegra_dt_init_irq,
+       .handle_irq     = gic_handle_irq,
+       .timer          = &tegra_timer,
+       .init_machine   = tegra_pismo_dt_init,
+       .restart        = tegra_assert_system_reset,
+       .dt_compat      = pismo_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-pismo.h b/arch/arm/mach-tegra/board-pismo.h
new file mode 100644 (file)
index 0000000..4438015
--- /dev/null
@@ -0,0 +1,123 @@
+/*
+ * arch/arm/mach-tegra/board-pismo.h
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef _MACH_TEGRA_BOARD_PISMO_H
+#define _MACH_TEGRA_BOARD_PISMO_H
+
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+#include "gpio-names.h"
+
+/* External peripheral act as gpio */
+/* AS3720 GPIO */
+#define AS3720_GPIO_BASE        TEGRA_NR_GPIOS
+
+/* Hall Effect Sensor GPIO */
+#define TEGRA_GPIO_HALL                TEGRA_GPIO_PS0
+
+/* Audio-related GPIOs */
+#define TEGRA_GPIO_CDC_IRQ             TEGRA_GPIO_PW3
+#define TEGRA_GPIO_LDO1_EN             TEGRA_GPIO_PV3
+#define TEGRA_GPIO_CODEC1_EN   TEGRA_GPIO_PP3
+#define TEGRA_GPIO_CODEC2_EN   TEGRA_GPIO_PP1
+#define TEGRA_GPIO_CODEC3_EN   TEGRA_GPIO_PV0
+
+#define TEGRA_GPIO_SPKR_EN             -1
+#define TEGRA_GPIO_HP_DET              TEGRA_GPIO_PR7
+#define TEGRA_GPIO_INT_MIC_EN          TEGRA_GPIO_PK3
+#define TEGRA_GPIO_EXT_MIC_EN          -1
+
+#define TEGRA_GPIO_W_DISABLE           TEGRA_GPIO_PDD7
+#define TEGRA_GPIO_MODEM_RSVD1         TEGRA_GPIO_PV0
+#define TEGRA_GPIO_MODEM_RSVD2         TEGRA_GPIO_PH7
+
+/* External peripheral act as interrupt controller */
+/* AS3720 IRQs */
+#define AS3270_IRQ_BASE                TEGRA_NR_IRQS
+
+/* I2C related GPIOs */
+#define TEGRA_GPIO_I2C1_SCL            TEGRA_GPIO_PC4
+#define TEGRA_GPIO_I2C1_SDA             TEGRA_GPIO_PC5
+#define TEGRA_GPIO_I2C2_SCL             TEGRA_GPIO_PT5
+#define TEGRA_GPIO_I2C2_SDA             TEGRA_GPIO_PT6
+#define TEGRA_GPIO_I2C3_SCL             TEGRA_GPIO_PBB1
+#define TEGRA_GPIO_I2C3_SDA             TEGRA_GPIO_PBB2
+#define TEGRA_GPIO_I2C4_SCL             TEGRA_GPIO_PV4
+#define TEGRA_GPIO_I2C4_SDA             TEGRA_GPIO_PV5
+#define TEGRA_GPIO_I2C5_SCL             TEGRA_GPIO_PZ6
+#define TEGRA_GPIO_I2C5_SDA             TEGRA_GPIO_PZ7
+
+/* Camera related GPIOs */
+#define CAM_RSTN                       TEGRA_GPIO_PBB3
+#define CAM_FLASH_STROBE               TEGRA_GPIO_PBB4
+#define CAM1_POWER_DWN_GPIO            TEGRA_GPIO_PBB5
+#define CAM2_POWER_DWN_GPIO            TEGRA_GPIO_PBB6
+#define CAM_AF_PWDN                    TEGRA_GPIO_PBB7
+#define CAM_GPIO1                      TEGRA_GPIO_PCC1
+#define CAM_GPIO2                      TEGRA_GPIO_PCC2
+
+/* Touchscreen definitions */
+#define TOUCH_GPIO_IRQ_RAYDIUM_SPI      TEGRA_GPIO_PK2
+#define TOUCH_GPIO_RST_RAYDIUM_SPI      TEGRA_GPIO_PK4
+
+/* Invensense MPU Definitions */
+#define MPU_GYRO_NAME           "mpu9150"
+#define MPU_GYRO_IRQ_GPIO       TEGRA_GPIO_PR3
+#define MPU_GYRO_ADDR           0x69
+#define MPU_GYRO_BUS_NUM        0
+#define MPU_GYRO_ORIENTATION   { -1, 0, 0, 0, 1, 0, 0, 0, -1 }
+#define MPU_ACCEL_NAME          "kxtf9"
+#define MPU_ACCEL_IRQ_GPIO      0 /* DISABLE ACCELIRQ:  TEGRA_GPIO_PJ2 */
+#define MPU_ACCEL_ADDR          0x0F
+#define MPU_ACCEL_BUS_NUM       0
+#define MPU_ACCEL_ORIENTATION   { 0, 1, 0, -1, 0, 0, 0, 0, 1 }
+#define MPU_COMPASS_NAME        "ak8975"
+#define MPU_COMPASS_IRQ_GPIO    0
+#define MPU_COMPASS_ADDR        0x0D
+#define MPU_COMPASS_BUS_NUM     0
+#define MPU_COMPASS_ORIENTATION { 0, 1, 0, -1, 0, 0, 0, 0, 1 }
+
+/* Modem related GPIOs */
+#define MODEM_EN               TEGRA_GPIO_PP2
+#define MDM_RST                        TEGRA_GPIO_PP0
+#define MDM_COLDBOOT           TEGRA_GPIO_PQ5
+
+int pismo_regulator_init(void);
+int pismo_suspend_init(void);
+int pismo_sdhci_init(void);
+int pismo_pinmux_init(void);
+int pismo_sensors_init(void);
+int pismo_emc_init(void);
+int pismo_edp_init(void);
+int pismo_panel_init(void);
+int roth_panel_init(void);
+int pismo_kbc_init(void);
+int pismo_pmon_init(void);
+int pismo_soctherm_init(void);
+
+/* Baseband IDs */
+enum tegra_bb_type {
+       TEGRA_BB_NEMO = 1,
+};
+
+#define UTMI1_PORT_OWNER_XUSB  0x1
+#define UTMI2_PORT_OWNER_XUSB  0x2
+#define HSIC1_PORT_OWNER_XUSB  0x4
+
+#endif
index 37be21d..6e4a55a 100644 (file)
@@ -31,6 +31,7 @@
 #define BOARD_E1575   0x0627
 #define BOARD_P2454   0x0996
 #define BOARD_E1582   0x062E
+#define BOARD_PM347   0x015B
 
 /* Board Fab version */
 #define BOARD_FAB_A00                  0x0