ARM: socfpga: initial support for Altera's SOCFPGA platform
Dinh Nguyen [Wed, 18 Jul 2012 22:07:18 +0000 (16:07 -0600)]
Adding core definitions for Altera's SOCFPGA ARM platform.
Mininum support for Altera's SOCFPGA Cyclone 5 hardware.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

16 files changed:
MAINTAINERS
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/boot/dts/socfpga.dtsi [new file with mode: 0644]
arch/arm/boot/dts/socfpga_cyclone5.dts [new file with mode: 0644]
arch/arm/configs/socfpga_defconfig [new file with mode: 0644]
arch/arm/mach-socfpga/Makefile [new file with mode: 0644]
arch/arm/mach-socfpga/Makefile.boot [new file with mode: 0644]
arch/arm/mach-socfpga/include/mach/debug-macro.S [new file with mode: 0644]
arch/arm/mach-socfpga/include/mach/timex.h [new file with mode: 0644]
arch/arm/mach-socfpga/include/mach/uncompress.h [new file with mode: 0644]
arch/arm/mach-socfpga/socfpga.c [new file with mode: 0644]
drivers/clk/Makefile
drivers/clk/socfpga/Makefile [new file with mode: 0644]
drivers/clk/socfpga/clk.c [new file with mode: 0644]
include/linux/dw_apb_timer.h

index b8a65fb..ab55a78 100644 (file)
@@ -1111,6 +1111,16 @@ S:       Supported
 F:     arch/arm/mach-shmobile/
 F:     drivers/sh/
 
+ARM/SOCFPGA ARCHITECTURE
+M:     Dinh Nguyen <dinguyen@altera.com>
+S:     Maintained
+F:     arch/arm/mach-socfpga/
+
+ARM/SOCFPGA CLOCK FRAMEWORK SUPPORT
+M:     Dinh Nguyen <dinguyen@altera.com>
+S:     Maintained
+F:     drivers/clk/socfpga/
+
 ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
 M:     Lennert Buytenhek <kernel@wantstofly.org>
 L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
index 7e3d931..dfeca55 100644 (file)
@@ -250,6 +250,25 @@ choice
        prompt "ARM system type"
        default ARCH_VERSATILE
 
+config ARCH_SOCFPGA
+       bool "Altera SOCFPGA family"
+       select ARCH_WANT_OPTIONAL_GPIOLIB
+       select ARM_AMBA
+       select ARM_GIC
+       select CACHE_L2X0
+       select CLKDEV_LOOKUP
+       select COMMON_CLK
+       select CPU_V7
+       select DW_APB_TIMER
+       select DW_APB_TIMER_OF
+       select GENERIC_CLOCKEVENTS
+       select GPIO_PL061 if GPIOLIB
+       select HAVE_ARM_SCU
+       select SPARSE_IRQ
+       select USE_OF
+       help
+         This enables support for Altera SOCFPGA Cyclone V platform
+
 config ARCH_INTEGRATOR
        bool "ARM Ltd. Integrator family"
        select ARM_AMBA
index f1a1a71..4d6d311 100644 (file)
@@ -187,6 +187,7 @@ machine-$(CONFIG_ARCH_VEXPRESS)             := vexpress
 machine-$(CONFIG_ARCH_VT8500)          := vt8500
 machine-$(CONFIG_ARCH_W90X900)         := w90x900
 machine-$(CONFIG_FOOTBRIDGE)           := footbridge
+machine-$(CONFIG_ARCH_SOCFPGA)         := socfpga
 machine-$(CONFIG_MACH_SPEAR1310)       := spear13xx
 machine-$(CONFIG_MACH_SPEAR1340)       := spear13xx
 machine-$(CONFIG_MACH_SPEAR300)                := spear3xx
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
new file mode 100644 (file)
index 0000000..0772f57
--- /dev/null
@@ -0,0 +1,147 @@
+/*
+ *  Copyright (C) 2012 Altera <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       aliases {
+               ethernet0 = &gmac0;
+               serial0 = &uart0;
+               serial1 = &uart1;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       compatible = "arm,cortex-a9";
+                       device_type = "cpu";
+                       reg = <0>;
+                       next-level-cache = <&L2>;
+               };
+               cpu@1 {
+                       compatible = "arm,cortex-a9";
+                       device_type = "cpu";
+                       reg = <1>;
+                       next-level-cache = <&L2>;
+               };
+       };
+
+       intc: intc@fffed000 {
+               compatible = "arm,cortex-a9-gic";
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg = <0xfffed000 0x1000>,
+                     <0xfffec100 0x100>;
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               device_type = "soc";
+               interrupt-parent = <&intc>;
+               ranges;
+
+               amba {
+                       compatible = "arm,amba-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       pdma: pdma@ffe01000 {
+                               compatible = "arm,pl330", "arm,primecell";
+                               reg = <0xffe01000 0x1000>;
+                               interrupts = <0 180 4>;
+                       };
+               };
+
+               gmac0: stmmac@ff700000 {
+                       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+                       reg = <0xff700000 0x2000>;
+                       interrupts = <0 115 4>;
+                       interrupt-names = "macirq";
+                       mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+                       phy-mode = "gmii";
+               };
+
+               L2: l2-cache@fffef000 {
+                       compatible = "arm,pl310-cache";
+                       reg = <0xfffef000 0x1000>;
+                       interrupts = <0 38 0x04>;
+                       cache-unified;
+                       cache-level = <2>;
+               };
+
+               /* Local timer */
+               timer@fffec600 {
+                       compatible = "arm,cortex-a9-twd-timer";
+                       reg = <0xfffec600 0x100>;
+                       interrupts = <1 13 0xf04>;
+               };
+
+               timer0: timer@ffc08000 {
+                       compatible = "snps,dw-apb-timer-sp";
+                       interrupts = <0 167 4>;
+                       clock-frequency = <200000000>;
+                       reg = <0xffc08000 0x1000>;
+               };
+
+               timer1: timer@ffc09000 {
+                       compatible = "snps,dw-apb-timer-sp";
+                       interrupts = <0 168 4>;
+                       clock-frequency = <200000000>;
+                       reg = <0xffc09000 0x1000>;
+               };
+
+               timer2: timer@ffd00000 {
+                       compatible = "snps,dw-apb-timer-osc";
+                       interrupts = <0 169 4>;
+                       clock-frequency = <200000000>;
+                       reg = <0xffd00000 0x1000>;
+               };
+
+               timer3: timer@ffd01000 {
+                       compatible = "snps,dw-apb-timer-osc";
+                       interrupts = <0 170 4>;
+                       clock-frequency = <200000000>;
+                       reg = <0xffd01000 0x1000>;
+               };
+
+               uart0: uart@ffc02000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0xffc02000 0x1000>;
+                       clock-frequency = <7372800>;
+                       interrupts = <0 162 4>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+               };
+
+               uart1: uart@ffc03000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0xffc03000 0x1000>;
+                       clock-frequency = <7372800>;
+                       interrupts = <0 163 4>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+               };
+       };
+};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
new file mode 100644 (file)
index 0000000..ab7e4a9
--- /dev/null
@@ -0,0 +1,34 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+/include/ "socfpga.dtsi"
+
+/ {
+       model = "Altera SOCFPGA Cyclone V";
+       compatible = "altr,socfpga-cyclone5";
+
+       chosen {
+               bootargs = "console=ttyS0,57600";
+       };
+
+       memory {
+               name = "memory";
+               device_type = "memory";
+               reg = <0x0 0x10000000>; /* 256MB */
+       };
+};
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
new file mode 100644 (file)
index 0000000..0ac1293
--- /dev/null
@@ -0,0 +1,83 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_CPUSETS=y
+CONFIG_NAMESPACES=y
+CONFIG_EMBEDDED=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_MACH_SOCFPGA_CYCLONE5=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_VMSPLIT_2G=y
+CONFIG_NR_CPUS=2
+CONFIG_AEABI=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_SCSI=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_STMMAC_ETH=y
+# CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_DW=y
+# CONFIG_RTC_HCTOSYS is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_ENABLE_DEFAULT_TRACERS=y
+CONFIG_DEBUG_USER=y
+CONFIG_XZ_DEC=y
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
new file mode 100644 (file)
index 0000000..4fb9324
--- /dev/null
@@ -0,0 +1,5 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-y                                  := socfpga.o
diff --git a/arch/arm/mach-socfpga/Makefile.boot b/arch/arm/mach-socfpga/Makefile.boot
new file mode 100644 (file)
index 0000000..dae9661
--- /dev/null
@@ -0,0 +1 @@
+zreladdr-y     := 0x00008000
diff --git a/arch/arm/mach-socfpga/include/mach/debug-macro.S b/arch/arm/mach-socfpga/include/mach/debug-macro.S
new file mode 100644 (file)
index 0000000..d6f26d2
--- /dev/null
@@ -0,0 +1,16 @@
+/*
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+               .macro  addruart, rp, rv, tmp
+               mov     \rp, #DEBUG_LL_UART_OFFSET
+               orr     \rp, \rp, #0x00c00000
+               orr     \rv, \rp, #0xfe000000   @ virtual base
+               orr     \rp, \rp, #0xff000000   @ physical base
+               .endm
+
diff --git a/arch/arm/mach-socfpga/include/mach/timex.h b/arch/arm/mach-socfpga/include/mach/timex.h
new file mode 100644 (file)
index 0000000..43df435
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define CLOCK_TICK_RATE                (50000000 / 16)
diff --git a/arch/arm/mach-socfpga/include/mach/uncompress.h b/arch/arm/mach-socfpga/include/mach/uncompress.h
new file mode 100644 (file)
index 0000000..bbe20e6
--- /dev/null
@@ -0,0 +1,9 @@
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#define putc(c)
+#define flush()
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
new file mode 100644 (file)
index 0000000..f01e1eb
--- /dev/null
@@ -0,0 +1,62 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/dw_apb_timer.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+
+extern void socfpga_init_clocks(void);
+
+const static struct of_device_id irq_match[] = {
+       { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+       {}
+};
+
+static void __init gic_init_irq(void)
+{
+       of_irq_init(irq_match);
+}
+
+static void socfpga_cyclone5_restart(char mode, const char *cmd)
+{
+       /* TODO: */
+}
+
+static void __init socfpga_cyclone5_init(void)
+{
+       l2x0_of_init(0, ~0UL);
+       of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+       socfpga_init_clocks();
+}
+
+static const char *altera_dt_match[] = {
+       "altr,socfpga",
+       "altr,socfpga-cyclone5",
+       NULL
+};
+
+DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
+       .init_irq       = gic_init_irq,
+       .handle_irq     = gic_handle_irq,
+       .timer          = &dw_apb_timer,
+       .init_machine   = socfpga_cyclone5_init,
+       .restart        = socfpga_cyclone5_restart,
+       .dt_compat      = altera_dt_match,
+MACHINE_END
index b9a5158..96014e8 100644 (file)
@@ -4,4 +4,5 @@ obj-$(CONFIG_COMMON_CLK)        += clk.o clk-fixed-rate.o clk-gate.o \
                                   clk-mux.o clk-divider.o clk-fixed-factor.o
 # SoCs specific
 obj-$(CONFIG_ARCH_MXS)         += mxs/
+obj-$(CONFIG_ARCH_SOCFPGA)     += socfpga/
 obj-$(CONFIG_PLAT_SPEAR)       += spear/
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
new file mode 100644 (file)
index 0000000..0303c0b
--- /dev/null
@@ -0,0 +1 @@
+obj-y += clk.o
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
new file mode 100644 (file)
index 0000000..2c855a6
--- /dev/null
@@ -0,0 +1,51 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+
+#define SOCFPGA_OSC1_CLK       10000000
+#define SOCFPGA_MPU_CLK                800000000
+#define SOCFPGA_MAIN_QSPI_CLK          432000000
+#define SOCFPGA_MAIN_NAND_SDMMC_CLK    250000000
+#define SOCFPGA_S2F_USR_CLK            125000000
+
+void __init socfpga_init_clocks(void)
+{
+       struct clk *clk;
+
+       clk = clk_register_fixed_rate(NULL, "osc1_clk", NULL, CLK_IS_ROOT, SOCFPGA_OSC1_CLK);
+       clk_register_clkdev(clk, "osc1_clk", NULL);
+
+       clk = clk_register_fixed_rate(NULL, "mpu_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK);
+       clk_register_clkdev(clk, "mpu_clk", NULL);
+
+       clk = clk_register_fixed_rate(NULL, "main_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
+       clk_register_clkdev(clk, "main_clk", NULL);
+
+       clk = clk_register_fixed_rate(NULL, "dbg_base_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
+       clk_register_clkdev(clk, "dbg_base_clk", NULL);
+
+       clk = clk_register_fixed_rate(NULL, "main_qspi_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_QSPI_CLK);
+       clk_register_clkdev(clk, "main_qspi_clk", NULL);
+
+       clk = clk_register_fixed_rate(NULL, "main_nand_sdmmc_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_NAND_SDMMC_CLK);
+       clk_register_clkdev(clk, "main_nand_sdmmc_clk", NULL);
+
+       clk = clk_register_fixed_rate(NULL, "s2f_usr_clk", NULL, CLK_IS_ROOT, SOCFPGA_S2F_USR_CLK);
+       clk_register_clkdev(clk, "s2f_usr_clk", NULL);
+}
index 07261d5..1148575 100644 (file)
@@ -53,4 +53,5 @@ void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs);
 cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs);
 void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs);
 
+extern struct sys_timer dw_apb_timer;
 #endif /* __DW_APB_TIMER_H__ */