ARM: tegra: ardbeg: Mask HS200,SDR104,SDR50 modes
Pavan Kunapuli [Wed, 26 Jun 2013 12:37:26 +0000 (17:37 +0530)]
Masking HS200, SDR104, SDR50 modes. These modes will be enabled once
the validation on silicon is done.
Remove default pm_flags settings for SDMMC1. The Wifi client driver
would set the required flags during suspend.
Pass card detect pin for SDMMC3 through platform data.
Updating SDIO1, SDIO3 drive strengths

Change-Id: I8a776b7f5f4e448e5f2b751ecda965e4bd01bf21
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/242428
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

arch/arm/mach-tegra/board-ardbeg-pinmux.c
arch/arm/mach-tegra/board-ardbeg-sdhci.c

index 203f091..2b73dc2 100644 (file)
@@ -216,11 +216,11 @@ static __initdata struct tegra_drive_pingroup_config ardbeg_drive_pinmux[] = {
        /*Set DAP2 drive (required for Codec Master Mode)*/
        SET_DRIVE(DAP2, DISABLE, ENABLE, DIV_1, 51, 51, FASTEST, FASTEST),
 
-       /* FIXME: update settings for t124 ardbeg */
-       SET_DRIVE(SDIO1, ENABLE, DISABLE, DIV_1, 36, 20, SLOW, SLOW),
+       /* SDMMC1 */
+       SET_DRIVE(SDIO1, ENABLE, DISABLE, DIV_1, 54, 70, FASTEST, FASTEST),
 
        /* SDMMC3 */
-       SET_DRIVE(SDIO3, ENABLE, DISABLE, DIV_1, 54, 70, FASTEST, FASTEST),
+       SET_DRIVE(SDIO3, ENABLE, DISABLE, DIV_1, 20, 42, FASTEST, FASTEST),
 
        /* SDMMC4 */
        SET_DRIVE_WITH_TYPE(GMA, ENABLE, DISABLE, DIV_1, 1, 2, FASTEST,
index 8e7df7e..6ce7826 100644 (file)
@@ -140,26 +140,24 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
                .built_in = 0,
                .ocr_mask = MMC_OCR_1V8_MASK,
        },
-#ifndef CONFIG_MMC_EMBEDDED_SDIO
-       .pm_flags = MMC_PM_KEEP_POWER,
-#endif
        .cd_gpio = -1,
        .wp_gpio = -1,
        .power_gpio = -1,
-       .tap_delay = 0x3,
-       .trim_delay = 0xA,
+       .tap_delay = 0,
+       .trim_delay = 0x2,
        .ddr_clk_limit = 41000000,
-       /* FIXME remove uhs_mask for T148 silicon */
        .uhs_mask = MMC_UHS_MASK_SDR104 |
-               MMC_UHS_MASK_DDR50,
+               MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
-       .cd_gpio = -1,
+       .cd_gpio = ARDBEG_SD_CD,
        .wp_gpio = -1,
        .power_gpio = -1,
        .tap_delay = 0,
        .trim_delay = 0x3,
+       .uhs_mask = MMC_UHS_MASK_SDR104 |
+               MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50,
 /*     .max_clk = 12000000, */
 };
 
@@ -173,7 +171,8 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
        .mmc_data = {
                .built_in = 1,
                .ocr_mask = MMC_OCR_1V8_MASK,
-       }
+       },
+       .uhs_mask = MMC_MASK_HS200,
 /*     .max_clk = 12000000, */
 };