asoc:tegra: fix dam cif programming
Dara Ramesh [Mon, 11 Feb 2013 08:23:14 +0000 (13:23 +0530)]
Change-Id: Ifb838ea81cd0b0f0864494b7a70e36569d934d15

Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Change-Id: I144c9994447affdca6a2b7ef8145d37826559895
Reviewed-on: http://git-master/r/200630
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Gaurav Sarode <gsarode@nvidia.com>

sound/soc/tegra/tegra_max98090.c

index dab4bea..25c1c23 100644 (file)
@@ -196,19 +196,33 @@ static int tegra_max98090_set_dam_cif(int dam_ifc, int srate,
                                srate);
        tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN1,
                                srate);
+#ifndef CONFIG_ARCH_TEGRA_3x_SOC
+       tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1,
+               channels, bit_size, channels,
+                               32);
+       tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
+               channels, bit_size, channels,
+                               32);
+#else
        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1,
                channels, bit_size, channels,
                                bit_size);
        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
                channels, bit_size, channels,
                                bit_size);
+#endif
 
        if (src_on) {
                tegra30_dam_set_gain(dam_ifc, TEGRA30_DAM_CHIN0_SRC, 0x1000);
                tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
                        src_srate);
+#ifndef CONFIG_ARCH_TEGRA_3x_SOC
+               tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
+                       src_channels, src_bit_size, 1, 32);
+#else
                tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
                        src_channels, src_bit_size, 1, 16);
+#endif
        }
 
        return 0;