ARM: tegra: clock: Lock DFLL 1st during cluster switch
Alex Frid [Tue, 15 Oct 2013 03:09:39 +0000 (20:09 -0700)]
During LP=>G CPU cluster switch lock DFLL in closed loop mode first,
and then disable LP CPU clock. This order change allowed to reduce
delay for G CPU to reach its target frequency.

Change-Id: If47779e2172cec8ccf9d66d74bbc2b219f7ddda2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/299683
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c
arch/arm/mach-tegra/tegra12_clocks.c
arch/arm/mach-tegra/tegra14_clocks.c

index 5994e44..74a864a 100644 (file)
@@ -1488,16 +1488,6 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
                goto abort;
        }
 
-       /* Disabling old parent scales old mode voltage rail */
-       if (c->refcnt)
-               clk_disable(c->parent);
-       if (p_source_old) {
-               clk_disable(p->parent);
-               clk_disable(p_source_old);
-       }
-
-       clk_reparent(c, p);
-
        /*
         * Lock DFLL now (resume closed loop VDD_CPU control).
         * G CPU operations are resumed on DFLL if it was the last G CPU
@@ -1514,6 +1504,16 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
                }
        }
 
+       /* Disabling old parent scales old mode voltage rail */
+       if (c->refcnt)
+               clk_disable(c->parent);
+       if (p_source_old) {
+               clk_disable(p->parent);
+               clk_disable(p_source_old);
+       }
+
+       clk_reparent(c, p);
+
        tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        return 0;
 
index 8420341..2e006ce 100644 (file)
@@ -1580,16 +1580,6 @@ static int tegra12_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
                goto abort;
        }
 
-       /* Disabling old parent scales old mode voltage rail */
-       if (c->refcnt)
-               clk_disable(c->parent);
-       if (p_source_old) {
-               clk_disable(p->parent);
-               clk_disable(p_source_old);
-       }
-
-       clk_reparent(c, p);
-
        /*
         * Lock DFLL now (resume closed loop VDD_CPU control).
         * G CPU operations are resumed on DFLL if it was the last G CPU
@@ -1606,6 +1596,16 @@ static int tegra12_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
                }
        }
 
+       /* Disabling old parent scales old mode voltage rail */
+       if (c->refcnt)
+               clk_disable(c->parent);
+       if (p_source_old) {
+               clk_disable(p->parent);
+               clk_disable(p_source_old);
+       }
+
+       clk_reparent(c, p);
+
        tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        return 0;
 
index 960f247..769cba9 100644 (file)
@@ -1441,16 +1441,6 @@ static int tegra14_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
                goto abort;
        }
 
-       /* Disabling old parent scales old mode voltage rail */
-       if (c->refcnt)
-               clk_disable(c->parent);
-       if (p_source_old) {
-               clk_disable(p->parent);
-               clk_disable(p_source_old);
-       }
-
-       clk_reparent(c, p);
-
        /*
         * Lock DFLL now (resume closed loop VDD_CPU control).
         * G CPU operations are resumed on DFLL if it was the last G CPU
@@ -1467,6 +1457,16 @@ static int tegra14_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
                }
        }
 
+       /* Disabling old parent scales old mode voltage rail */
+       if (c->refcnt)
+               clk_disable(c->parent);
+       if (p_source_old) {
+               clk_disable(p->parent);
+               clk_disable(p_source_old);
+       }
+
+       clk_reparent(c, p);
+
        tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        return 0;