ARM: tegra11: clock: Update PLLE spread spectrum setting
Alex Frid [Sat, 23 Feb 2013 04:42:41 +0000 (20:42 -0800)]
Bug 1167739

Change-Id: Ie97ca1e70189fb27ca476cae8cf34e5f16b2eff5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/203567
(cherry picked from commit 0aa10b64ccf9ddc506862481b5e3f209f6285866)
Reviewed-on: http://git-master/r/207906
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c

index 86533d5..b500f88 100644 (file)
 #define        PLLE_SS_INCINTRV_MASK           (0x3f<<PLLE_SS_INCINTRV_SHIFT)
 #define        PLLE_SS_INC_SHIFT               16
 #define        PLLE_SS_INC_MASK                (0xff<<PLLE_SS_INC_SHIFT)
+#define        PLLE_SS_CNTL_INVERT             (0x1 << 15)
+#define        PLLE_SS_CNTL_CENTER             (0x1 << 14)
 #define        PLLE_SS_CNTL_SSC_BYP            (0x1 << 12)
 #define        PLLE_SS_CNTL_INTERP_RESET       (0x1 << 11)
 #define        PLLE_SS_CNTL_BYPASS_SS          (0x1 << 10)
@@ -3457,6 +3459,7 @@ static int tegra11_plle_clk_enable(struct clk *c)
                c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
 #if USE_PLLE_SS
        val = clk_readl(PLLE_SS_CTRL);
+       val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
        val &= ~PLLE_SS_COEFFICIENTS_MASK;
        val |= PLLE_SS_COEFFICIENTS_VAL;
        clk_writel(val, PLLE_SS_CTRL);