ARM: tegra12: dvfs: Add core rail Vmax trip-points
Alex Frid [Fri, 8 Nov 2013 06:30:02 +0000 (22:30 -0800)]
Added core rail Vmax trip-points to PLL thermal zone on Tegra12
platforms. Made sure pid governor is installed in PLL zone (for
consistency with all other SOC-THERM zones, and to avoid incorrect
cooling device state reporting by default step-wise governor).

Bug 1413311

Change-Id: Ib06fd98ab39dc9a4411b571778600569d801b242
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/335923
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

arch/arm/mach-tegra/board-ardbeg-power.c
arch/arm/mach-tegra/board-ardbeg-sensors.c
arch/arm/mach-tegra/board-common.c
arch/arm/mach-tegra/board-common.h
arch/arm/mach-tegra/board-laguna-power.c
arch/arm/mach-tegra/board-loki-power.c
arch/arm/mach-tegra/board-loki-sensors.c

index f7f6200..4efac57 100644 (file)
@@ -1381,6 +1381,7 @@ static struct soctherm_platform_data ardbeg_soctherm_data = {
                },
                [THERM_PLL] = {
                        .zone_enable = true,
+                       .tzp = &soctherm_tzp,
                },
        },
        .throttle = {
@@ -1427,6 +1428,9 @@ int __init ardbeg_soctherm_init(void)
                tegra_add_vc_trips(
                        ardbeg_soctherm_data.therm[THERM_CPU].trips,
                        &ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
+               tegra_add_tpll_trips(
+                       ardbeg_soctherm_data.therm[THERM_PLL].trips,
+                       &ardbeg_soctherm_data.therm[THERM_PLL].num_trips);
        }
 
        tegra_get_pmu_board_info(&pmu_board_info);
index adc3d83..eec6a8b 100644 (file)
@@ -1440,6 +1440,8 @@ static int ardbeg_nct72_init(void)
                                     &ardbeg_nct72_pdata.num_trips);
                tegra_add_vc_trips(ardbeg_nct72_pdata.trips,
                                     &ardbeg_nct72_pdata.num_trips);
+               tegra_add_tpll_trips(ardbeg_nct72_pdata.trips,
+                                    &ardbeg_nct72_pdata.num_trips);
        }
 
        tegra_add_cdev_trips(ardbeg_nct72_pdata.trips,
index f379203..4580bf3 100644 (file)
@@ -190,3 +190,8 @@ void tegra_add_vc_trips(struct thermal_trip_info *trips, int *num_trips)
 {
        tegra_add_trip_points(trips, num_trips, tegra_vc_get_cdev());
 }
+void tegra_add_tpll_trips(struct thermal_trip_info *trips, int *num_trips)
+{
+       tegra_add_trip_points(trips, num_trips,
+                             tegra_dvfs_get_core_vmax_cdev());
+}
index db13f90..cd8efbd 100644 (file)
@@ -31,5 +31,6 @@ void tegra_add_cdev_trips(struct thermal_trip_info *trips, int *num_trips);
 void tegra_add_tj_trips(struct thermal_trip_info *trips, int *num_trips);
 void tegra_add_tgpu_trips(struct thermal_trip_info *trips, int *num_trips);
 void tegra_add_vc_trips(struct thermal_trip_info *trips, int *num_trips);
+void tegra_add_tpll_trips(struct thermal_trip_info *trips, int *num_trips);
 
 #endif
index 71c98f4..c9a7607 100644 (file)
@@ -932,6 +932,7 @@ static struct soctherm_platform_data laguna_soctherm_data = {
                },
                [THERM_PLL] = {
                        .zone_enable = true,
+                       .tzp = &soctherm_tzp,
                },
        },
        .throttle = {
@@ -966,6 +967,8 @@ int __init laguna_soctherm_init(void)
                        &laguna_soctherm_data.therm[THERM_GPU].num_trips);
        tegra_add_vc_trips(laguna_soctherm_data.therm[THERM_CPU].trips,
                        &laguna_soctherm_data.therm[THERM_CPU].num_trips);
+       tegra_add_tpll_trips(laguna_soctherm_data.therm[THERM_PLL].trips,
+                       &laguna_soctherm_data.therm[THERM_PLL].num_trips);
 
        return tegra11_soctherm_init(&laguna_soctherm_data);
 }
index c6e90a0..98471de 100644 (file)
@@ -955,6 +955,7 @@ static struct soctherm_platform_data loki_soctherm_data = {
                },
                [THERM_PLL] = {
                        .zone_enable = true,
+                       .tzp = &soctherm_tzp,
                },
        },
        .throttle = {
@@ -1015,6 +1016,9 @@ int __init loki_soctherm_init(void)
                tegra_add_vc_trips(
                        loki_soctherm_data.therm[THERM_CPU].trips,
                        &loki_soctherm_data.therm[THERM_CPU].num_trips);
+               tegra_add_tpll_trips(
+                       loki_soctherm_data.therm[THERM_PLL].trips,
+                       &loki_soctherm_data.therm[THERM_PLL].num_trips);
        }
 
        return tegra11_soctherm_init(&loki_soctherm_data);
index cda886f..d3fb90c 100644 (file)
@@ -462,6 +462,8 @@ static int loki_nct72_init(void)
                                     &loki_nct72_pdata.num_trips);
                tegra_add_vc_trips(loki_nct72_pdata.trips,
                                     &loki_nct72_pdata.num_trips);
+               tegra_add_tpll_trips(loki_nct72_pdata.trips,
+                                    &loki_nct72_pdata.num_trips);
        }