ARM: tegra12: clock: Fix system bus clock rounding
Kaz Fukuoka [Wed, 25 Sep 2013 23:42:51 +0000 (16:42 -0700)]
Made sure system bus clock (SCLK) round rate operation follows the
same policy on fractional divisors as set rate operation - either both
operations allow fractions, or both does not support them (otherwise,
clock rate stats are confused).

Ported from Tegra11 Change-Id: I3814d66905c01f2ff84b0402be9b9a3d0b113fd6

Change-Id: If4b0eed9be2ce8967c5597ac7471325d0043a38f
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/298504
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

arch/arm/mach-tegra/tegra12_clocks.c

index 7e43bb9..1a07d9b 100644 (file)
@@ -1780,7 +1780,10 @@ static long tegra12_sbus_cmplx_round_updown(struct clk *c, unsigned long rate,
 
        round_rate = source_rate * 2 / (divider + 2);
        if (round_rate > c->max_rate) {
-               divider = max(2, (divider + 1));
+               divider += new_parent->flags & DIV_U71_INT ? 2 : 1;
+#if !DIVIDER_1_5_ALLOWED
+               divider = max(2, divider);
+#endif
                round_rate = source_rate * 2 / (divider + 2);
        }