Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Linus Torvalds [Thu, 4 Oct 2012 06:29:23 +0000 (23:29 -0700)]
Pull drm merge (part 1) from Dave Airlie:
 "So first of all my tree and uapi stuff has a conflict mess, its my
  fault as the nouveau stuff didn't hit -next as were trying to rebase
  regressions out of it before we merged.

  Highlights:
   - SH mobile modesetting driver and associated helpers
   - some DRM core documentation
   - i915 modesetting rework, haswell hdmi, haswell and vlv fixes, write
     combined pte writing, ilk rc6 support,
   - nouveau: major driver rework into a hw core driver, makes features
     like SLI a lot saner to implement,
   - psb: add eDP/DP support for Cedarview
   - radeon: 2 layer page tables, async VM pte updates, better PLL
     selection for > 2 screens, better ACPI interactions

  The rest is general grab bag of fixes.

  So why part 1? well I have the exynos pull req which came in a bit
  late but was waiting for me to do something they shouldn't have and it
  looks fairly safe, and David Howells has some more header cleanups
  he'd like me to pull, that seem like a good idea, but I'd like to get
  this merge out of the way so -next dosen't get blocked."

Tons of conflicts mostly due to silly include line changes, but mostly
mindless.  A few other small semantic conflicts too, noted from Dave's
pre-merged branch.

* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (447 commits)
  drm/nv98/crypt: fix fuc build with latest envyas
  drm/nouveau/devinit: fixup various issues with subdev ctor/init ordering
  drm/nv41/vm: fix and enable use of "real" pciegart
  drm/nv44/vm: fix and enable use of "real" pciegart
  drm/nv04/dmaobj: fixup vm target handling in preparation for nv4x pcie
  drm/nouveau: store supported dma mask in vmmgr
  drm/nvc0/ibus: initial implementation of subdev
  drm/nouveau/therm: add support for fan-control modes
  drm/nouveau/hwmon: rename pwm0* to pmw1* to follow hwmon's rules
  drm/nouveau/therm: calculate the pwm divisor on nv50+
  drm/nouveau/fan: rewrite the fan tachometer driver to get more precision, faster
  drm/nouveau/therm: move thermal-related functions to the therm subdev
  drm/nouveau/bios: parse the pwm divisor from the perf table
  drm/nouveau/therm: use the EXTDEV table to detect i2c monitoring devices
  drm/nouveau/therm: rework thermal table parsing
  drm/nouveau/gpio: expose the PWM/TOGGLE parameter found in the gpio vbios table
  drm/nouveau: fix pm initialization order
  drm/nouveau/bios: check that fixed tvdac gpio data is valid before using it
  drm/nouveau: log channel debug/error messages from client object rather than drm client
  drm/nouveau: have drm debugging macros build on top of core macros
  ...

148 files changed:
1  2 
drivers/gpu/drm/ast/ast_drv.h
drivers/gpu/drm/ast/ast_mode.c
drivers/gpu/drm/cirrus/cirrus_drv.h
drivers/gpu/drm/drm_cache.c
drivers/gpu/drm/drm_crtc.c
drivers/gpu/drm/drm_drv.c
drivers/gpu/drm/drm_edid.c
drivers/gpu/drm/drm_edid_load.c
drivers/gpu/drm/drm_edid_modes.h
drivers/gpu/drm/drm_fb_helper.c
drivers/gpu/drm/drm_irq.c
drivers/gpu/drm/drm_vm.c
drivers/gpu/drm/exynos/exynos_drm_connector.c
drivers/gpu/drm/exynos/exynos_drm_fbdev.c
drivers/gpu/drm/exynos/exynos_drm_vidi.c
drivers/gpu/drm/gma500/cdv_device.c
drivers/gpu/drm/gma500/cdv_intel_dp.c
drivers/gpu/drm/gma500/gem.c
drivers/gpu/drm/gma500/intel_bios.c
drivers/gpu/drm/gma500/mid_bios.c
drivers/gpu/drm/gma500/psb_device.c
drivers/gpu/drm/gma500/psb_drv.h
drivers/gpu/drm/gma500/psb_intel_sdvo.c
drivers/gpu/drm/i915/dvo.h
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_context.c
drivers/gpu/drm/i915/i915_gem_dmabuf.c
drivers/gpu/drm/i915/i915_gem_evict.c
drivers/gpu/drm/i915/i915_gem_execbuffer.c
drivers/gpu/drm/i915/i915_gem_gtt.c
drivers/gpu/drm/i915/i915_gem_tiling.c
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/intel_crt.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_dvo.c
drivers/gpu/drm/i915/intel_hdmi.c
drivers/gpu/drm/i915/intel_lvds.c
drivers/gpu/drm/i915/intel_modes.c
drivers/gpu/drm/i915/intel_opregion.c
drivers/gpu/drm/i915/intel_overlay.c
drivers/gpu/drm/i915/intel_ringbuffer.c
drivers/gpu/drm/i915/intel_sdvo.c
drivers/gpu/drm/i915/intel_tv.c
drivers/gpu/drm/mgag200/mgag200_drv.h
drivers/gpu/drm/mgag200/mgag200_mode.c
drivers/gpu/drm/nouveau/core/subdev/gpio/base.c
drivers/gpu/drm/nouveau/nouveau_acpi.c
drivers/gpu/drm/nouveau/nouveau_bios.c
drivers/gpu/drm/nouveau/nouveau_calc.c
drivers/gpu/drm/nouveau/nouveau_connector.c
drivers/gpu/drm/nouveau/nouveau_connector.h
drivers/gpu/drm/nouveau/nouveau_display.c
drivers/gpu/drm/nouveau/nouveau_dp.c
drivers/gpu/drm/nouveau/nouveau_drm.c
drivers/gpu/drm/nouveau/nouveau_drm.h
drivers/gpu/drm/nouveau/nouveau_encoder.h
drivers/gpu/drm/nouveau/nouveau_fbcon.c
drivers/gpu/drm/nouveau/nouveau_fbcon.h
drivers/gpu/drm/nouveau/nouveau_fence.c
drivers/gpu/drm/nouveau/nouveau_gem.c
drivers/gpu/drm/nouveau/nouveau_gem.h
drivers/gpu/drm/nouveau/nouveau_hdmi.c
drivers/gpu/drm/nouveau/nouveau_hw.c
drivers/gpu/drm/nouveau/nouveau_hw.h
drivers/gpu/drm/nouveau/nouveau_ioc32.c
drivers/gpu/drm/nouveau/nouveau_perf.c
drivers/gpu/drm/nouveau/nouveau_pm.c
drivers/gpu/drm/nouveau/nouveau_prime.c
drivers/gpu/drm/nouveau/nouveau_vga.c
drivers/gpu/drm/nouveau/nouveau_volt.c
drivers/gpu/drm/nouveau/nv04_crtc.c
drivers/gpu/drm/nouveau/nv04_cursor.c
drivers/gpu/drm/nouveau/nv04_dac.c
drivers/gpu/drm/nouveau/nv04_dfp.c
drivers/gpu/drm/nouveau/nv04_display.c
drivers/gpu/drm/nouveau/nv04_pm.c
drivers/gpu/drm/nouveau/nv04_tv.c
drivers/gpu/drm/nouveau/nv17_tv.c
drivers/gpu/drm/nouveau/nv17_tv_modes.c
drivers/gpu/drm/nouveau/nv40_pm.c
drivers/gpu/drm/nouveau/nv50_crtc.c
drivers/gpu/drm/nouveau/nv50_cursor.c
drivers/gpu/drm/nouveau/nv50_dac.c
drivers/gpu/drm/nouveau/nv50_display.c
drivers/gpu/drm/nouveau/nv50_evo.c
drivers/gpu/drm/nouveau/nv50_pm.c
drivers/gpu/drm/nouveau/nv50_sor.c
drivers/gpu/drm/nouveau/nva3_pm.c
drivers/gpu/drm/nouveau/nvd0_display.c
drivers/gpu/drm/radeon/atombios_dp.c
drivers/gpu/drm/radeon/atombios_encoders.c
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/evergreen_cs.c
drivers/gpu/drm/radeon/ni.c
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r300.c
drivers/gpu/drm/radeon/r520.c
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/r600_blit.c
drivers/gpu/drm/radeon/r600_blit_kms.c
drivers/gpu/drm/radeon/r600_cs.c
drivers/gpu/drm/radeon/r600_hdmi.c
drivers/gpu/drm/radeon/radeon_acpi.c
drivers/gpu/drm/radeon/radeon_atombios.c
drivers/gpu/drm/radeon/radeon_combios.c
drivers/gpu/drm/radeon/radeon_connectors.c
drivers/gpu/drm/radeon/radeon_cs.c
drivers/gpu/drm/radeon/radeon_drv.c
drivers/gpu/drm/radeon/radeon_encoders.c
drivers/gpu/drm/radeon/radeon_fb.c
drivers/gpu/drm/radeon/radeon_fence.c
drivers/gpu/drm/radeon/radeon_gart.c
drivers/gpu/drm/radeon/radeon_gem.c
drivers/gpu/drm/radeon/radeon_ioc32.c
drivers/gpu/drm/radeon/radeon_irq_kms.c
drivers/gpu/drm/radeon/radeon_kms.c
drivers/gpu/drm/radeon/radeon_legacy_encoders.c
drivers/gpu/drm/radeon/radeon_mode.h
drivers/gpu/drm/radeon/radeon_object.c
drivers/gpu/drm/radeon/radeon_pm.c
drivers/gpu/drm/radeon/radeon_ring.c
drivers/gpu/drm/radeon/radeon_sa.c
drivers/gpu/drm/radeon/rs600.c
drivers/gpu/drm/radeon/rs690.c
drivers/gpu/drm/radeon/rv515.c
drivers/gpu/drm/radeon/rv770.c
drivers/gpu/drm/radeon/si.c
drivers/gpu/drm/savage/savage_bci.c
drivers/gpu/drm/ttm/ttm_bo_util.c
drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
drivers/gpu/drm/ttm/ttm_tt.c
drivers/gpu/drm/udl/udl_connector.c
drivers/gpu/drm/udl/udl_encoder.c
drivers/gpu/drm/udl/udl_fb.c
drivers/gpu/drm/udl/udl_gem.c
drivers/gpu/drm/udl/udl_main.c
drivers/gpu/drm/udl/udl_modeset.c
drivers/gpu/drm/udl/udl_transfer.c
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
include/drm/drmP.h
include/drm/drm_crtc.h
include/drm/drm_sarea.h
include/drm/i915_drm.h

Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
index 0000000,c9abc06..e3a3978
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,1951 +1,1950 @@@
+ /*
+  * Copyright © 2012 Intel Corporation
+  *
+  * Permission is hereby granted, free of charge, to any person obtaining a
+  * copy of this software and associated documentation files (the "Software"),
+  * to deal in the Software without restriction, including without limitation
+  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+  * and/or sell copies of the Software, and to permit persons to whom the
+  * Software is furnished to do so, subject to the following conditions:
+  *
+  * The above copyright notice and this permission notice (including the next
+  * paragraph) shall be included in all copies or substantial portions of the
+  * Software.
+  *
+  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+  * IN THE SOFTWARE.
+  *
+  * Authors:
+  *    Keith Packard <keithp@keithp.com>
+  *
+  */
+ #include <linux/i2c.h>
+ #include <linux/slab.h>
 -#include "drmP.h"
 -#include "drm.h"
 -#include "drm_crtc.h"
 -#include "drm_crtc_helper.h"
++#include <drm/drmP.h>
++#include <drm/drm_crtc.h>
++#include <drm/drm_crtc_helper.h>
+ #include "psb_drv.h"
+ #include "psb_intel_drv.h"
+ #include "psb_intel_reg.h"
 -#include "drm_dp_helper.h"
++#include <drm/drm_dp_helper.h>
+ #define _wait_for(COND, MS, W) ({ \
+         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);       \
+         int ret__ = 0;                                                  \
+         while (! (COND)) {                                              \
+                 if (time_after(jiffies, timeout__)) {                   \
+                         ret__ = -ETIMEDOUT;                             \
+                         break;                                          \
+                 }                                                       \
+                 if (W && !in_dbg_master()) msleep(W);                   \
+         }                                                               \
+         ret__;                                                          \
+ })      
+ #define wait_for(COND, MS) _wait_for(COND, MS, 1)
+ #define DP_LINK_STATUS_SIZE   6
+ #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
+ #define DP_LINK_CONFIGURATION_SIZE    9
+ #define CDV_FAST_LINK_TRAIN   1
+ struct cdv_intel_dp {
+       uint32_t output_reg;
+       uint32_t DP;
+       uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
+       bool has_audio;
+       int force_audio;
+       uint32_t color_range;
+       uint8_t link_bw;
+       uint8_t lane_count;
+       uint8_t dpcd[4];
+       struct psb_intel_encoder *encoder;
+       struct i2c_adapter adapter;
+       struct i2c_algo_dp_aux_data algo;
+       uint8_t train_set[4];
+       uint8_t link_status[DP_LINK_STATUS_SIZE];
+       int panel_power_up_delay;
+       int panel_power_down_delay;
+       int panel_power_cycle_delay;
+       int backlight_on_delay;
+       int backlight_off_delay;
+       struct drm_display_mode *panel_fixed_mode;  /* for eDP */
+       bool panel_on;
+ };
+ struct ddi_regoff {
+       uint32_t        PreEmph1;
+       uint32_t        PreEmph2;
+       uint32_t        VSwing1;
+       uint32_t        VSwing2;
+       uint32_t        VSwing3;
+       uint32_t        VSwing4;
+       uint32_t        VSwing5;
+ };
+ static struct ddi_regoff ddi_DP_train_table[] = {
+       {.PreEmph1 = 0x812c, .PreEmph2 = 0x8124, .VSwing1 = 0x8154,
+       .VSwing2 = 0x8148, .VSwing3 = 0x814C, .VSwing4 = 0x8150,
+       .VSwing5 = 0x8158,},
+       {.PreEmph1 = 0x822c, .PreEmph2 = 0x8224, .VSwing1 = 0x8254,
+       .VSwing2 = 0x8248, .VSwing3 = 0x824C, .VSwing4 = 0x8250,
+       .VSwing5 = 0x8258,},
+ };
+ static uint32_t dp_vswing_premph_table[] = {
+         0x55338954,   0x4000,
+         0x554d8954,   0x2000,
+         0x55668954,   0,
+         0x559ac0d4,   0x6000,
+ };
+ /**
+  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
+  * @intel_dp: DP struct
+  *
+  * If a CPU or PCH DP output is attached to an eDP panel, this function
+  * will return true, and false otherwise.
+  */
+ static bool is_edp(struct psb_intel_encoder *encoder)
+ {
+       return encoder->type == INTEL_OUTPUT_EDP;
+ }
+ static void cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder);
+ static void cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder);
+ static void cdv_intel_dp_link_down(struct psb_intel_encoder *encoder);
+ static int
+ cdv_intel_dp_max_lane_count(struct psb_intel_encoder *encoder)
+ {
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       int max_lane_count = 4;
+       if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
+               max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
+               switch (max_lane_count) {
+               case 1: case 2: case 4:
+                       break;
+               default:
+                       max_lane_count = 4;
+               }
+       }
+       return max_lane_count;
+ }
+ static int
+ cdv_intel_dp_max_link_bw(struct psb_intel_encoder *encoder)
+ {
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
+       switch (max_link_bw) {
+       case DP_LINK_BW_1_62:
+       case DP_LINK_BW_2_7:
+               break;
+       default:
+               max_link_bw = DP_LINK_BW_1_62;
+               break;
+       }
+       return max_link_bw;
+ }
+ static int
+ cdv_intel_dp_link_clock(uint8_t link_bw)
+ {
+       if (link_bw == DP_LINK_BW_2_7)
+               return 270000;
+       else
+               return 162000;
+ }
+ static int
+ cdv_intel_dp_link_required(int pixel_clock, int bpp)
+ {
+       return (pixel_clock * bpp + 7) / 8;
+ }
+ static int
+ cdv_intel_dp_max_data_rate(int max_link_clock, int max_lanes)
+ {
+       return (max_link_clock * max_lanes * 19) / 20;
+ }
+ static void cdv_intel_edp_panel_vdd_on(struct psb_intel_encoder *intel_encoder)
+ {
+       struct drm_device *dev = intel_encoder->base.dev;
+       struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+       u32 pp;
+       if (intel_dp->panel_on) {
+               DRM_DEBUG_KMS("Skip VDD on because of panel on\n");
+               return;
+       }       
+       DRM_DEBUG_KMS("\n");
+       pp = REG_READ(PP_CONTROL);
+       pp |= EDP_FORCE_VDD;
+       REG_WRITE(PP_CONTROL, pp);
+       REG_READ(PP_CONTROL);
+       msleep(intel_dp->panel_power_up_delay);
+ }
+ static void cdv_intel_edp_panel_vdd_off(struct psb_intel_encoder *intel_encoder)
+ {
+       struct drm_device *dev = intel_encoder->base.dev;
+       u32 pp;
+       DRM_DEBUG_KMS("\n");
+       pp = REG_READ(PP_CONTROL);
+       pp &= ~EDP_FORCE_VDD;
+       REG_WRITE(PP_CONTROL, pp);
+       REG_READ(PP_CONTROL);
+ }
+ /* Returns true if the panel was already on when called */
+ static bool cdv_intel_edp_panel_on(struct psb_intel_encoder *intel_encoder)
+ {
+       struct drm_device *dev = intel_encoder->base.dev;
+       struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+       u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_NONE;
+       if (intel_dp->panel_on)
+               return true;
+       DRM_DEBUG_KMS("\n");
+       pp = REG_READ(PP_CONTROL);
+       pp &= ~PANEL_UNLOCK_MASK;
+       pp |= (PANEL_UNLOCK_REGS | POWER_TARGET_ON);
+       REG_WRITE(PP_CONTROL, pp);
+       REG_READ(PP_CONTROL);
+       if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) {
+               DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS));
+               intel_dp->panel_on = false;
+       } else
+               intel_dp->panel_on = true;      
+       msleep(intel_dp->panel_power_up_delay);
+       return false;
+ }
+ static void cdv_intel_edp_panel_off (struct psb_intel_encoder *intel_encoder)
+ {
+       struct drm_device *dev = intel_encoder->base.dev;
+       u32 pp, idle_off_mask = PP_ON ;
+       struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+       DRM_DEBUG_KMS("\n");
+       pp = REG_READ(PP_CONTROL);
+       if ((pp & POWER_TARGET_ON) == 0) 
+               return;
+       intel_dp->panel_on = false;
+       pp &= ~PANEL_UNLOCK_MASK;
+       /* ILK workaround: disable reset around power sequence */
+       pp &= ~POWER_TARGET_ON;
+       pp &= ~EDP_FORCE_VDD;
+       pp &= ~EDP_BLC_ENABLE;
+       REG_WRITE(PP_CONTROL, pp);
+       REG_READ(PP_CONTROL);
+       DRM_DEBUG_KMS("PP_STATUS %x\n", REG_READ(PP_STATUS));
+       if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) {
+               DRM_DEBUG_KMS("Error in turning off Panel\n");  
+       }
+       msleep(intel_dp->panel_power_cycle_delay);
+       DRM_DEBUG_KMS("Over\n");
+ }
+ static void cdv_intel_edp_backlight_on (struct psb_intel_encoder *intel_encoder)
+ {
+       struct drm_device *dev = intel_encoder->base.dev;
+       u32 pp;
+       DRM_DEBUG_KMS("\n");
+       /*
+        * If we enable the backlight right away following a panel power
+        * on, we may see slight flicker as the panel syncs with the eDP
+        * link.  So delay a bit to make sure the image is solid before
+        * allowing it to appear.
+        */
+       msleep(300);
+       pp = REG_READ(PP_CONTROL);
+       pp |= EDP_BLC_ENABLE;
+       REG_WRITE(PP_CONTROL, pp);
+       gma_backlight_enable(dev);
+ }
+ static void cdv_intel_edp_backlight_off (struct psb_intel_encoder *intel_encoder)
+ {
+       struct drm_device *dev = intel_encoder->base.dev;
+       struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+       u32 pp;
+       DRM_DEBUG_KMS("\n");
+       gma_backlight_disable(dev);
+       msleep(10);
+       pp = REG_READ(PP_CONTROL);
+       pp &= ~EDP_BLC_ENABLE;
+       REG_WRITE(PP_CONTROL, pp);
+       msleep(intel_dp->backlight_off_delay);
+ }
+ static int
+ cdv_intel_dp_mode_valid(struct drm_connector *connector,
+                   struct drm_display_mode *mode)
+ {
+       struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       int max_link_clock = cdv_intel_dp_link_clock(cdv_intel_dp_max_link_bw(encoder));
+       int max_lanes = cdv_intel_dp_max_lane_count(encoder);
+       struct drm_psb_private *dev_priv = connector->dev->dev_private;
+       if (is_edp(encoder) && intel_dp->panel_fixed_mode) {
+               if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
+                       return MODE_PANEL;
+               if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
+                       return MODE_PANEL;
+       }
+       /* only refuse the mode on non eDP since we have seen some weird eDP panels
+          which are outside spec tolerances but somehow work by magic */
+       if (!is_edp(encoder) &&
+           (cdv_intel_dp_link_required(mode->clock, dev_priv->edp.bpp)
+            > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes)))
+               return MODE_CLOCK_HIGH;
+       if (is_edp(encoder)) {
+           if (cdv_intel_dp_link_required(mode->clock, 24)
+               > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes))
+               return MODE_CLOCK_HIGH;
+               
+       }
+       if (mode->clock < 10000)
+               return MODE_CLOCK_LOW;
+       return MODE_OK;
+ }
+ static uint32_t
+ pack_aux(uint8_t *src, int src_bytes)
+ {
+       int     i;
+       uint32_t v = 0;
+       if (src_bytes > 4)
+               src_bytes = 4;
+       for (i = 0; i < src_bytes; i++)
+               v |= ((uint32_t) src[i]) << ((3-i) * 8);
+       return v;
+ }
+ static void
+ unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
+ {
+       int i;
+       if (dst_bytes > 4)
+               dst_bytes = 4;
+       for (i = 0; i < dst_bytes; i++)
+               dst[i] = src >> ((3-i) * 8);
+ }
+ static int
+ cdv_intel_dp_aux_ch(struct psb_intel_encoder *encoder,
+               uint8_t *send, int send_bytes,
+               uint8_t *recv, int recv_size)
+ {
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       uint32_t output_reg = intel_dp->output_reg;
+       struct drm_device *dev = encoder->base.dev;
+       uint32_t ch_ctl = output_reg + 0x10;
+       uint32_t ch_data = ch_ctl + 4;
+       int i;
+       int recv_bytes;
+       uint32_t status;
+       uint32_t aux_clock_divider;
+       int try, precharge;
+       /* The clock divider is based off the hrawclk,
+        * and would like to run at 2MHz. So, take the
+        * hrawclk value and divide by 2 and use that
+        * On CDV platform it uses 200MHz as hrawclk.
+        *
+        */
+       aux_clock_divider = 200 / 2;
+       precharge = 4;
+       if (is_edp(encoder))
+               precharge = 10;
+       if (REG_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
+               DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
+                         REG_READ(ch_ctl));
+               return -EBUSY;
+       }
+       /* Must try at least 3 times according to DP spec */
+       for (try = 0; try < 5; try++) {
+               /* Load the send data into the aux channel data registers */
+               for (i = 0; i < send_bytes; i += 4)
+                       REG_WRITE(ch_data + i,
+                                  pack_aux(send + i, send_bytes - i));
+       
+               /* Send the command and wait for it to complete */
+               REG_WRITE(ch_ctl,
+                          DP_AUX_CH_CTL_SEND_BUSY |
+                          DP_AUX_CH_CTL_TIME_OUT_400us |
+                          (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+                          (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
+                          (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
+                          DP_AUX_CH_CTL_DONE |
+                          DP_AUX_CH_CTL_TIME_OUT_ERROR |
+                          DP_AUX_CH_CTL_RECEIVE_ERROR);
+               for (;;) {
+                       status = REG_READ(ch_ctl);
+                       if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
+                               break;
+                       udelay(100);
+               }
+       
+               /* Clear done status and any errors */
+               REG_WRITE(ch_ctl,
+                          status |
+                          DP_AUX_CH_CTL_DONE |
+                          DP_AUX_CH_CTL_TIME_OUT_ERROR |
+                          DP_AUX_CH_CTL_RECEIVE_ERROR);
+               if (status & DP_AUX_CH_CTL_DONE)
+                       break;
+       }
+       if ((status & DP_AUX_CH_CTL_DONE) == 0) {
+               DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
+               return -EBUSY;
+       }
+       /* Check for timeout or receive error.
+        * Timeouts occur when the sink is not connected
+        */
+       if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
+               DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
+               return -EIO;
+       }
+       /* Timeouts occur when the device isn't connected, so they're
+        * "normal" -- don't fill the kernel log with these */
+       if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
+               DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
+               return -ETIMEDOUT;
+       }
+       /* Unload any bytes sent back from the other side */
+       recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
+                     DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
+       if (recv_bytes > recv_size)
+               recv_bytes = recv_size;
+       
+       for (i = 0; i < recv_bytes; i += 4)
+               unpack_aux(REG_READ(ch_data + i),
+                          recv + i, recv_bytes - i);
+       return recv_bytes;
+ }
+ /* Write data to the aux channel in native mode */
+ static int
+ cdv_intel_dp_aux_native_write(struct psb_intel_encoder *encoder,
+                         uint16_t address, uint8_t *send, int send_bytes)
+ {
+       int ret;
+       uint8_t msg[20];
+       int msg_bytes;
+       uint8_t ack;
+       if (send_bytes > 16)
+               return -1;
+       msg[0] = AUX_NATIVE_WRITE << 4;
+       msg[1] = address >> 8;
+       msg[2] = address & 0xff;
+       msg[3] = send_bytes - 1;
+       memcpy(&msg[4], send, send_bytes);
+       msg_bytes = send_bytes + 4;
+       for (;;) {
+               ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes, &ack, 1);
+               if (ret < 0)
+                       return ret;
+               if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
+                       break;
+               else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
+                       udelay(100);
+               else
+                       return -EIO;
+       }
+       return send_bytes;
+ }
+ /* Write a single byte to the aux channel in native mode */
+ static int
+ cdv_intel_dp_aux_native_write_1(struct psb_intel_encoder *encoder,
+                           uint16_t address, uint8_t byte)
+ {
+       return cdv_intel_dp_aux_native_write(encoder, address, &byte, 1);
+ }
+ /* read bytes from a native aux channel */
+ static int
+ cdv_intel_dp_aux_native_read(struct psb_intel_encoder *encoder,
+                        uint16_t address, uint8_t *recv, int recv_bytes)
+ {
+       uint8_t msg[4];
+       int msg_bytes;
+       uint8_t reply[20];
+       int reply_bytes;
+       uint8_t ack;
+       int ret;
+       msg[0] = AUX_NATIVE_READ << 4;
+       msg[1] = address >> 8;
+       msg[2] = address & 0xff;
+       msg[3] = recv_bytes - 1;
+       msg_bytes = 4;
+       reply_bytes = recv_bytes + 1;
+       for (;;) {
+               ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes,
+                                     reply, reply_bytes);
+               if (ret == 0)
+                       return -EPROTO;
+               if (ret < 0)
+                       return ret;
+               ack = reply[0];
+               if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
+                       memcpy(recv, reply + 1, ret - 1);
+                       return ret - 1;
+               }
+               else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
+                       udelay(100);
+               else
+                       return -EIO;
+       }
+ }
+ static int
+ cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
+                   uint8_t write_byte, uint8_t *read_byte)
+ {
+       struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+       struct cdv_intel_dp *intel_dp = container_of(adapter,
+                                               struct cdv_intel_dp,
+                                               adapter);
+       struct psb_intel_encoder *encoder = intel_dp->encoder;
+       uint16_t address = algo_data->address;
+       uint8_t msg[5];
+       uint8_t reply[2];
+       unsigned retry;
+       int msg_bytes;
+       int reply_bytes;
+       int ret;
+       /* Set up the command byte */
+       if (mode & MODE_I2C_READ)
+               msg[0] = AUX_I2C_READ << 4;
+       else
+               msg[0] = AUX_I2C_WRITE << 4;
+       if (!(mode & MODE_I2C_STOP))
+               msg[0] |= AUX_I2C_MOT << 4;
+       msg[1] = address >> 8;
+       msg[2] = address;
+       switch (mode) {
+       case MODE_I2C_WRITE:
+               msg[3] = 0;
+               msg[4] = write_byte;
+               msg_bytes = 5;
+               reply_bytes = 1;
+               break;
+       case MODE_I2C_READ:
+               msg[3] = 0;
+               msg_bytes = 4;
+               reply_bytes = 2;
+               break;
+       default:
+               msg_bytes = 3;
+               reply_bytes = 1;
+               break;
+       }
+       for (retry = 0; retry < 5; retry++) {
+               ret = cdv_intel_dp_aux_ch(encoder,
+                                     msg, msg_bytes,
+                                     reply, reply_bytes);
+               if (ret < 0) {
+                       DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
+                       return ret;
+               }
+               switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
+               case AUX_NATIVE_REPLY_ACK:
+                       /* I2C-over-AUX Reply field is only valid
+                        * when paired with AUX ACK.
+                        */
+                       break;
+               case AUX_NATIVE_REPLY_NACK:
+                       DRM_DEBUG_KMS("aux_ch native nack\n");
+                       return -EREMOTEIO;
+               case AUX_NATIVE_REPLY_DEFER:
+                       udelay(100);
+                       continue;
+               default:
+                       DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
+                                 reply[0]);
+                       return -EREMOTEIO;
+               }
+               switch (reply[0] & AUX_I2C_REPLY_MASK) {
+               case AUX_I2C_REPLY_ACK:
+                       if (mode == MODE_I2C_READ) {
+                               *read_byte = reply[1];
+                       }
+                       return reply_bytes - 1;
+               case AUX_I2C_REPLY_NACK:
+                       DRM_DEBUG_KMS("aux_i2c nack\n");
+                       return -EREMOTEIO;
+               case AUX_I2C_REPLY_DEFER:
+                       DRM_DEBUG_KMS("aux_i2c defer\n");
+                       udelay(100);
+                       break;
+               default:
+                       DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
+                       return -EREMOTEIO;
+               }
+       }
+       DRM_ERROR("too many retries, giving up\n");
+       return -EREMOTEIO;
+ }
+ static int
+ cdv_intel_dp_i2c_init(struct psb_intel_connector *connector, struct psb_intel_encoder *encoder, const char *name)
+ {
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       int ret;
+       DRM_DEBUG_KMS("i2c_init %s\n", name);
+       intel_dp->algo.running = false;
+       intel_dp->algo.address = 0;
+       intel_dp->algo.aux_ch = cdv_intel_dp_i2c_aux_ch;
+       memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
+       intel_dp->adapter.owner = THIS_MODULE;
+       intel_dp->adapter.class = I2C_CLASS_DDC;
+       strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
+       intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
+       intel_dp->adapter.algo_data = &intel_dp->algo;
+       intel_dp->adapter.dev.parent = &connector->base.kdev;
+       if (is_edp(encoder))
+               cdv_intel_edp_panel_vdd_on(encoder);
+       ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
+       if (is_edp(encoder))
+               cdv_intel_edp_panel_vdd_off(encoder);
+       
+       return ret;
+ }
+ void cdv_intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
+       struct drm_display_mode *adjusted_mode)
+ {
+       adjusted_mode->hdisplay = fixed_mode->hdisplay;
+       adjusted_mode->hsync_start = fixed_mode->hsync_start;
+       adjusted_mode->hsync_end = fixed_mode->hsync_end;
+       adjusted_mode->htotal = fixed_mode->htotal;
+       adjusted_mode->vdisplay = fixed_mode->vdisplay;
+       adjusted_mode->vsync_start = fixed_mode->vsync_start;
+       adjusted_mode->vsync_end = fixed_mode->vsync_end;
+       adjusted_mode->vtotal = fixed_mode->vtotal;
+       adjusted_mode->clock = fixed_mode->clock;
+       drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
+ }
+ static bool
+ cdv_intel_dp_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode,
+                   struct drm_display_mode *adjusted_mode)
+ {
+       struct drm_psb_private *dev_priv = encoder->dev->dev_private;
+       struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
+       struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+       int lane_count, clock;
+       int max_lane_count = cdv_intel_dp_max_lane_count(intel_encoder);
+       int max_clock = cdv_intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
+       static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
+       int refclock = mode->clock;
+       int bpp = 24;
+       if (is_edp(intel_encoder) && intel_dp->panel_fixed_mode) {
+               cdv_intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
+               refclock = intel_dp->panel_fixed_mode->clock;
+               bpp = dev_priv->edp.bpp;
+       }
+       for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
+               for (clock = max_clock; clock >= 0; clock--) {
+                       int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count);
+                       if (cdv_intel_dp_link_required(refclock, bpp) <= link_avail) {
+                               intel_dp->link_bw = bws[clock];
+                               intel_dp->lane_count = lane_count;
+                               adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
+                               DRM_DEBUG_KMS("Display port link bw %02x lane "
+                                               "count %d clock %d\n",
+                                      intel_dp->link_bw, intel_dp->lane_count,
+                                      adjusted_mode->clock);
+                               return true;
+                       }
+               }
+       }
+       if (is_edp(intel_encoder)) {
+               /* okay we failed just pick the highest */
+               intel_dp->lane_count = max_lane_count;
+               intel_dp->link_bw = bws[max_clock];
+               adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
+               DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
+                             "count %d clock %d\n",
+                             intel_dp->link_bw, intel_dp->lane_count,
+                             adjusted_mode->clock);
+               return true;
+       }
+       return false;
+ }
+ struct cdv_intel_dp_m_n {
+       uint32_t        tu;
+       uint32_t        gmch_m;
+       uint32_t        gmch_n;
+       uint32_t        link_m;
+       uint32_t        link_n;
+ };
+ static void
+ cdv_intel_reduce_ratio(uint32_t *num, uint32_t *den)
+ {
+       /*
+       while (*num > 0xffffff || *den > 0xffffff) {
+               *num >>= 1;
+               *den >>= 1;
+       }*/
+       uint64_t value, m;
+       m = *num;
+       value = m * (0x800000);
+       m = do_div(value, *den);
+       *num = value;
+       *den = 0x800000;
+ }
+ static void
+ cdv_intel_dp_compute_m_n(int bpp,
+                    int nlanes,
+                    int pixel_clock,
+                    int link_clock,
+                    struct cdv_intel_dp_m_n *m_n)
+ {
+       m_n->tu = 64;
+       m_n->gmch_m = (pixel_clock * bpp + 7) >> 3;
+       m_n->gmch_n = link_clock * nlanes;
+       cdv_intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
+       m_n->link_m = pixel_clock;
+       m_n->link_n = link_clock;
+       cdv_intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
+ }
+ void
+ cdv_intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
+                struct drm_display_mode *adjusted_mode)
+ {
+       struct drm_device *dev = crtc->dev;
+       struct drm_psb_private *dev_priv = dev->dev_private;
+       struct drm_mode_config *mode_config = &dev->mode_config;
+       struct drm_encoder *encoder;
+       struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
+       int lane_count = 4, bpp = 24;
+       struct cdv_intel_dp_m_n m_n;
+       int pipe = intel_crtc->pipe;
+       /*
+        * Find the lane count in the intel_encoder private
+        */
+       list_for_each_entry(encoder, &mode_config->encoder_list, head) {
+               struct psb_intel_encoder *intel_encoder;
+               struct cdv_intel_dp *intel_dp;
+               if (encoder->crtc != crtc)
+                       continue;
+               intel_encoder = to_psb_intel_encoder(encoder);
+               intel_dp = intel_encoder->dev_priv;
+               if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
+                       lane_count = intel_dp->lane_count;
+                       break;
+               } else if (is_edp(intel_encoder)) {
+                       lane_count = intel_dp->lane_count;
+                       bpp = dev_priv->edp.bpp;
+                       break;
+               }
+       }
+       /*
+        * Compute the GMCH and Link ratios. The '3' here is
+        * the number of bytes_per_pixel post-LUT, which we always
+        * set up for 8-bits of R/G/B, or 3 bytes total.
+        */
+       cdv_intel_dp_compute_m_n(bpp, lane_count,
+                            mode->clock, adjusted_mode->clock, &m_n);
+       {
+               REG_WRITE(PIPE_GMCH_DATA_M(pipe),
+                          ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
+                          m_n.gmch_m);
+               REG_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
+               REG_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
+               REG_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
+       }
+ }
+ static void
+ cdv_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
+                 struct drm_display_mode *adjusted_mode)
+ {
+       struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
+       struct drm_crtc *crtc = encoder->crtc;
+       struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
+       struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+       struct drm_device *dev = encoder->dev;
+       intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
+       intel_dp->DP |= intel_dp->color_range;
+       if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+               intel_dp->DP |= DP_SYNC_HS_HIGH;
+       if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+               intel_dp->DP |= DP_SYNC_VS_HIGH;
+       intel_dp->DP |= DP_LINK_TRAIN_OFF;
+       switch (intel_dp->lane_count) {
+       case 1:
+               intel_dp->DP |= DP_PORT_WIDTH_1;
+               break;
+       case 2:
+               intel_dp->DP |= DP_PORT_WIDTH_2;
+               break;
+       case 4:
+               intel_dp->DP |= DP_PORT_WIDTH_4;
+               break;
+       }
+       if (intel_dp->has_audio)
+               intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
+       memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
+       intel_dp->link_configuration[0] = intel_dp->link_bw;
+       intel_dp->link_configuration[1] = intel_dp->lane_count;
+       /*
+        * Check for DPCD version > 1.1 and enhanced framing support
+        */
+       if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
+           (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
+               intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+               intel_dp->DP |= DP_ENHANCED_FRAMING;
+       }
+       /* CPT DP's pipe select is decided in TRANS_DP_CTL */
+       if (intel_crtc->pipe == 1)
+               intel_dp->DP |= DP_PIPEB_SELECT;
+       REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));
+       DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);
+       if (is_edp(intel_encoder)) {
+               uint32_t pfit_control;
+               cdv_intel_edp_panel_on(intel_encoder);
+               if (mode->hdisplay != adjusted_mode->hdisplay ||
+                           mode->vdisplay != adjusted_mode->vdisplay)
+                       pfit_control = PFIT_ENABLE;
+               else
+                       pfit_control = 0;
+               pfit_control |= intel_crtc->pipe << PFIT_PIPE_SHIFT;
+               REG_WRITE(PFIT_CONTROL, pfit_control);
+       }
+ }
+ /* If the sink supports it, try to set the power state appropriately */
+ static void cdv_intel_dp_sink_dpms(struct psb_intel_encoder *encoder, int mode)
+ {
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       int ret, i;
+       /* Should have a valid DPCD by this point */
+       if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
+               return;
+       if (mode != DRM_MODE_DPMS_ON) {
+               ret = cdv_intel_dp_aux_native_write_1(encoder, DP_SET_POWER,
+                                                 DP_SET_POWER_D3);
+               if (ret != 1)
+                       DRM_DEBUG_DRIVER("failed to write sink power state\n");
+       } else {
+               /*
+                * When turning on, we need to retry for 1ms to give the sink
+                * time to wake up.
+                */
+               for (i = 0; i < 3; i++) {
+                       ret = cdv_intel_dp_aux_native_write_1(encoder,
+                                                         DP_SET_POWER,
+                                                         DP_SET_POWER_D0);
+                       if (ret == 1)
+                               break;
+                       udelay(1000);
+               }
+       }
+ }
+ static void cdv_intel_dp_prepare(struct drm_encoder *encoder)
+ {
+       struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
+       int edp = is_edp(intel_encoder);
+       if (edp) {
+               cdv_intel_edp_backlight_off(intel_encoder);
+               cdv_intel_edp_panel_off(intel_encoder);
+               cdv_intel_edp_panel_vdd_on(intel_encoder);
+         }
+       /* Wake up the sink first */
+       cdv_intel_dp_sink_dpms(intel_encoder, DRM_MODE_DPMS_ON);
+       cdv_intel_dp_link_down(intel_encoder);
+       if (edp)
+               cdv_intel_edp_panel_vdd_off(intel_encoder);
+ }
+ static void cdv_intel_dp_commit(struct drm_encoder *encoder)
+ {
+       struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
+       int edp = is_edp(intel_encoder);
+       if (edp)
+               cdv_intel_edp_panel_on(intel_encoder);
+       cdv_intel_dp_start_link_train(intel_encoder);
+       cdv_intel_dp_complete_link_train(intel_encoder);
+       if (edp)
+               cdv_intel_edp_backlight_on(intel_encoder);
+ }
+ static void
+ cdv_intel_dp_dpms(struct drm_encoder *encoder, int mode)
+ {
+       struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
+       struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+       struct drm_device *dev = encoder->dev;
+       uint32_t dp_reg = REG_READ(intel_dp->output_reg);
+       int edp = is_edp(intel_encoder);
+       if (mode != DRM_MODE_DPMS_ON) {
+               if (edp) {
+                       cdv_intel_edp_backlight_off(intel_encoder);
+                       cdv_intel_edp_panel_vdd_on(intel_encoder);
+               }
+               cdv_intel_dp_sink_dpms(intel_encoder, mode);
+               cdv_intel_dp_link_down(intel_encoder);
+               if (edp) {
+                       cdv_intel_edp_panel_vdd_off(intel_encoder);
+                       cdv_intel_edp_panel_off(intel_encoder);
+               }
+       } else {
+               if (edp)
+                       cdv_intel_edp_panel_on(intel_encoder);
+               cdv_intel_dp_sink_dpms(intel_encoder, mode);
+               if (!(dp_reg & DP_PORT_EN)) {
+                       cdv_intel_dp_start_link_train(intel_encoder);
+                       cdv_intel_dp_complete_link_train(intel_encoder);
+               }
+               if (edp)
+                       cdv_intel_edp_backlight_on(intel_encoder);
+       }
+ }
+ /*
+  * Native read with retry for link status and receiver capability reads for
+  * cases where the sink may still be asleep.
+  */
+ static bool
+ cdv_intel_dp_aux_native_read_retry(struct psb_intel_encoder *encoder, uint16_t address,
+                              uint8_t *recv, int recv_bytes)
+ {
+       int ret, i;
+       /*
+        * Sinks are *supposed* to come up within 1ms from an off state,
+        * but we're also supposed to retry 3 times per the spec.
+        */
+       for (i = 0; i < 3; i++) {
+               ret = cdv_intel_dp_aux_native_read(encoder, address, recv,
+                                              recv_bytes);
+               if (ret == recv_bytes)
+                       return true;
+               udelay(1000);
+       }
+       return false;
+ }
+ /*
+  * Fetch AUX CH registers 0x202 - 0x207 which contain
+  * link status information
+  */
+ static bool
+ cdv_intel_dp_get_link_status(struct psb_intel_encoder *encoder)
+ {
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       return cdv_intel_dp_aux_native_read_retry(encoder,
+                                             DP_LANE0_1_STATUS,
+                                             intel_dp->link_status,
+                                             DP_LINK_STATUS_SIZE);
+ }
+ static uint8_t
+ cdv_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
+                    int r)
+ {
+       return link_status[r - DP_LANE0_1_STATUS];
+ }
+ static uint8_t
+ cdv_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
+                                int lane)
+ {
+       int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
+       int         s = ((lane & 1) ?
+                        DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
+                        DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
+       uint8_t l = cdv_intel_dp_link_status(link_status, i);
+       return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
+ }
+ static uint8_t
+ cdv_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
+                                     int lane)
+ {
+       int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
+       int         s = ((lane & 1) ?
+                        DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
+                        DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
+       uint8_t l = cdv_intel_dp_link_status(link_status, i);
+       return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
+ }
+ #if 0
+ static char   *voltage_names[] = {
+       "0.4V", "0.6V", "0.8V", "1.2V"
+ };
+ static char   *pre_emph_names[] = {
+       "0dB", "3.5dB", "6dB", "9.5dB"
+ };
+ static char   *link_train_names[] = {
+       "pattern 1", "pattern 2", "idle", "off"
+ };
+ #endif
+ #define CDV_DP_VOLTAGE_MAX        DP_TRAIN_VOLTAGE_SWING_1200
+ /*
+ static uint8_t
+ cdv_intel_dp_pre_emphasis_max(uint8_t voltage_swing)
+ {
+       switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+       case DP_TRAIN_VOLTAGE_SWING_400:
+               return DP_TRAIN_PRE_EMPHASIS_6;
+       case DP_TRAIN_VOLTAGE_SWING_600:
+               return DP_TRAIN_PRE_EMPHASIS_6;
+       case DP_TRAIN_VOLTAGE_SWING_800:
+               return DP_TRAIN_PRE_EMPHASIS_3_5;
+       case DP_TRAIN_VOLTAGE_SWING_1200:
+       default:
+               return DP_TRAIN_PRE_EMPHASIS_0;
+       }
+ }
+ */
+ static void
+ cdv_intel_get_adjust_train(struct psb_intel_encoder *encoder)
+ {
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       uint8_t v = 0;
+       uint8_t p = 0;
+       int lane;
+       for (lane = 0; lane < intel_dp->lane_count; lane++) {
+               uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane);
+               uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
+               if (this_v > v)
+                       v = this_v;
+               if (this_p > p)
+                       p = this_p;
+       }
+       
+       if (v >= CDV_DP_VOLTAGE_MAX)
+               v = CDV_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
+       if (p == DP_TRAIN_PRE_EMPHASIS_MASK)
+               p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+               
+       for (lane = 0; lane < 4; lane++)
+               intel_dp->train_set[lane] = v | p;
+ }
+ static uint8_t
+ cdv_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
+                     int lane)
+ {
+       int i = DP_LANE0_1_STATUS + (lane >> 1);
+       int s = (lane & 1) * 4;
+       uint8_t l = cdv_intel_dp_link_status(link_status, i);
+       return (l >> s) & 0xf;
+ }
+ /* Check for clock recovery is done on all channels */
+ static bool
+ cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
+ {
+       int lane;
+       uint8_t lane_status;
+       for (lane = 0; lane < lane_count; lane++) {
+               lane_status = cdv_intel_get_lane_status(link_status, lane);
+               if ((lane_status & DP_LANE_CR_DONE) == 0)
+                       return false;
+       }
+       return true;
+ }
+ /* Check to see if channel eq is done on all channels */
+ #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
+                        DP_LANE_CHANNEL_EQ_DONE|\
+                        DP_LANE_SYMBOL_LOCKED)
+ static bool
+ cdv_intel_channel_eq_ok(struct psb_intel_encoder *encoder)
+ {
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       uint8_t lane_align;
+       uint8_t lane_status;
+       int lane;
+       lane_align = cdv_intel_dp_link_status(intel_dp->link_status,
+                                         DP_LANE_ALIGN_STATUS_UPDATED);
+       if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
+               return false;
+       for (lane = 0; lane < intel_dp->lane_count; lane++) {
+               lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);
+               if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
+                       return false;
+       }
+       return true;
+ }
+ static bool
+ cdv_intel_dp_set_link_train(struct psb_intel_encoder *encoder,
+                       uint32_t dp_reg_value,
+                       uint8_t dp_train_pat)
+ {
+       
+       struct drm_device *dev = encoder->base.dev;
+       int ret;
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       REG_WRITE(intel_dp->output_reg, dp_reg_value);
+       REG_READ(intel_dp->output_reg);
+       ret = cdv_intel_dp_aux_native_write_1(encoder,
+                                   DP_TRAINING_PATTERN_SET,
+                                   dp_train_pat);
+       if (ret != 1) {
+               DRM_DEBUG_KMS("Failure in setting link pattern %x\n",
+                               dp_train_pat);
+               return false;
+       }
+       return true;
+ }
+ static bool
+ cdv_intel_dplink_set_level(struct psb_intel_encoder *encoder,
+                       uint8_t dp_train_pat)
+ {
+       
+       int ret;
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       ret = cdv_intel_dp_aux_native_write(encoder,
+                                       DP_TRAINING_LANE0_SET,
+                                       intel_dp->train_set,
+                                       intel_dp->lane_count);
+       if (ret != intel_dp->lane_count) {
+               DRM_DEBUG_KMS("Failure in setting level %d, lane_cnt= %d\n",
+                               intel_dp->train_set[0], intel_dp->lane_count);
+               return false;
+       }
+       return true;
+ }
+ static void
+ cdv_intel_dp_set_vswing_premph(struct psb_intel_encoder *encoder, uint8_t signal_level)
+ {
+       struct drm_device *dev = encoder->base.dev;
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       struct ddi_regoff *ddi_reg;
+       int vswing, premph, index;
+       if (intel_dp->output_reg == DP_B)
+               ddi_reg = &ddi_DP_train_table[0];
+       else
+               ddi_reg = &ddi_DP_train_table[1];
+       vswing = (signal_level & DP_TRAIN_VOLTAGE_SWING_MASK);
+       premph = ((signal_level & DP_TRAIN_PRE_EMPHASIS_MASK)) >>
+                               DP_TRAIN_PRE_EMPHASIS_SHIFT;
+       if (vswing + premph > 3)
+               return;
+ #ifdef CDV_FAST_LINK_TRAIN
+       return;
+ #endif
+       DRM_DEBUG_KMS("Test2\n");
+       //return ;
+       cdv_sb_reset(dev);
+       /* ;Swing voltage programming
+         ;gfx_dpio_set_reg(0xc058, 0x0505313A) */
+       cdv_sb_write(dev, ddi_reg->VSwing5, 0x0505313A);
+       /* ;gfx_dpio_set_reg(0x8154, 0x43406055) */
+       cdv_sb_write(dev, ddi_reg->VSwing1, 0x43406055);
+       /* ;gfx_dpio_set_reg(0x8148, 0x55338954)
+        * The VSwing_PreEmph table is also considered based on the vswing/premp
+        */
+       index = (vswing + premph) * 2;
+       if (premph == 1 && vswing == 1) {
+               cdv_sb_write(dev, ddi_reg->VSwing2, 0x055738954);
+       } else
+               cdv_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]);
+       /* ;gfx_dpio_set_reg(0x814c, 0x40802040) */
+       if ((vswing + premph) == DP_TRAIN_VOLTAGE_SWING_1200)
+               cdv_sb_write(dev, ddi_reg->VSwing3, 0x70802040);
+       else
+               cdv_sb_write(dev, ddi_reg->VSwing3, 0x40802040);
+       /* ;gfx_dpio_set_reg(0x8150, 0x2b405555) */
+       /* cdv_sb_write(dev, ddi_reg->VSwing4, 0x2b405555); */
+       /* ;gfx_dpio_set_reg(0x8154, 0xc3406055) */
+       cdv_sb_write(dev, ddi_reg->VSwing1, 0xc3406055);
+       /* ;Pre emphasis programming
+        * ;gfx_dpio_set_reg(0xc02c, 0x1f030040)
+        */
+       cdv_sb_write(dev, ddi_reg->PreEmph1, 0x1f030040);
+       /* ;gfx_dpio_set_reg(0x8124, 0x00004000) */
+       index = 2 * premph + 1;
+       cdv_sb_write(dev, ddi_reg->PreEmph2, dp_vswing_premph_table[index]);
+       return; 
+ }
+ /* Enable corresponding port and start training pattern 1 */
+ static void
+ cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder)
+ {
+       struct drm_device *dev = encoder->base.dev;
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       int i;
+       uint8_t voltage;
+       bool clock_recovery = false;
+       int tries;
+       u32 reg;
+       uint32_t DP = intel_dp->DP;
+       DP |= DP_PORT_EN;
+       DP &= ~DP_LINK_TRAIN_MASK;
+               
+       reg = DP;       
+       reg |= DP_LINK_TRAIN_PAT_1;
+       /* Enable output, wait for it to become active */
+       REG_WRITE(intel_dp->output_reg, reg);
+       REG_READ(intel_dp->output_reg);
+       psb_intel_wait_for_vblank(dev);
+       DRM_DEBUG_KMS("Link config\n");
+       /* Write the link configuration data */
+       cdv_intel_dp_aux_native_write(encoder, DP_LINK_BW_SET,
+                                 intel_dp->link_configuration,
+                                 2);
+       memset(intel_dp->train_set, 0, 4);
+       voltage = 0;
+       tries = 0;
+       clock_recovery = false;
+       DRM_DEBUG_KMS("Start train\n");
+               reg = DP | DP_LINK_TRAIN_PAT_1;
+       for (;;) {
+               /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
+               DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
+                               intel_dp->train_set[0],
+                               intel_dp->link_configuration[0],
+                               intel_dp->link_configuration[1]);
+               if (!cdv_intel_dp_set_link_train(encoder, reg, DP_TRAINING_PATTERN_1)) {
+                       DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 1\n");
+               }
+               cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
+               /* Set training pattern 1 */
+               cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_1);
+               udelay(200);
+               if (!cdv_intel_dp_get_link_status(encoder))
+                       break;
+               DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
+                               intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],
+                               intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);
+               if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
+                       DRM_DEBUG_KMS("PT1 train is done\n");
+                       clock_recovery = true;
+                       break;
+               }
+               /* Check to see if we've tried the max voltage */
+               for (i = 0; i < intel_dp->lane_count; i++)
+                       if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
+                               break;
+               if (i == intel_dp->lane_count)
+                       break;
+               /* Check to see if we've tried the same voltage 5 times */
+               if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
+                       ++tries;
+                       if (tries == 5)
+                               break;
+               } else
+                       tries = 0;
+               voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
+               /* Compute new intel_dp->train_set as requested by target */
+               cdv_intel_get_adjust_train(encoder);
+       }
+       if (!clock_recovery) {
+               DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp->train_set[0]);
+       }
+       
+       intel_dp->DP = DP;
+ }
+ static void
+ cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder)
+ {
+       struct drm_device *dev = encoder->base.dev;
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       bool channel_eq = false;
+       int tries, cr_tries;
+       u32 reg;
+       uint32_t DP = intel_dp->DP;
+       /* channel equalization */
+       tries = 0;
+       cr_tries = 0;
+       channel_eq = false;
+       DRM_DEBUG_KMS("\n");
+               reg = DP | DP_LINK_TRAIN_PAT_2;
+       for (;;) {
+               DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
+                               intel_dp->train_set[0],
+                               intel_dp->link_configuration[0],
+                               intel_dp->link_configuration[1]);
+               /* channel eq pattern */
+               if (!cdv_intel_dp_set_link_train(encoder, reg,
+                                            DP_TRAINING_PATTERN_2)) {
+                       DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 2\n");
+               }
+               /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
+               if (cr_tries > 5) {
+                       DRM_ERROR("failed to train DP, aborting\n");
+                       cdv_intel_dp_link_down(encoder);
+                       break;
+               }
+               cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
+               cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_2);
+               udelay(1000);
+               if (!cdv_intel_dp_get_link_status(encoder))
+                       break;
+               DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
+                               intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],
+                               intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);
+               /* Make sure clock is still ok */
+               if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
+                       cdv_intel_dp_start_link_train(encoder);
+                       cr_tries++;
+                       continue;
+               }
+               if (cdv_intel_channel_eq_ok(encoder)) {
+                       DRM_DEBUG_KMS("PT2 train is done\n");
+                       channel_eq = true;
+                       break;
+               }
+               /* Try 5 times, then try clock recovery if that fails */
+               if (tries > 5) {
+                       cdv_intel_dp_link_down(encoder);
+                       cdv_intel_dp_start_link_train(encoder);
+                       tries = 0;
+                       cr_tries++;
+                       continue;
+               }
+               /* Compute new intel_dp->train_set as requested by target */
+               cdv_intel_get_adjust_train(encoder);
+               ++tries;
+       }
+       reg = DP | DP_LINK_TRAIN_OFF;
+       REG_WRITE(intel_dp->output_reg, reg);
+       REG_READ(intel_dp->output_reg);
+       cdv_intel_dp_aux_native_write_1(encoder,
+                                   DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
+ }
+ static void
+ cdv_intel_dp_link_down(struct psb_intel_encoder *encoder)
+ {
+       struct drm_device *dev = encoder->base.dev;
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       uint32_t DP = intel_dp->DP;
+       if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
+               return;
+       DRM_DEBUG_KMS("\n");
+       {
+               DP &= ~DP_LINK_TRAIN_MASK;
+               REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
+       }
+       REG_READ(intel_dp->output_reg);
+       msleep(17);
+       REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
+       REG_READ(intel_dp->output_reg);
+ }
+ static enum drm_connector_status
+ cdv_dp_detect(struct psb_intel_encoder *encoder)
+ {
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       enum drm_connector_status status;
+       status = connector_status_disconnected;
+       if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd,
+                                    sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
+       {
+               if (intel_dp->dpcd[DP_DPCD_REV] != 0)
+                       status = connector_status_connected;
+       }
+       if (status == connector_status_connected)
+               DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n",
+                       intel_dp->dpcd[0], intel_dp->dpcd[1],
+                       intel_dp->dpcd[2], intel_dp->dpcd[3]);
+       return status;
+ }
+ /**
+  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
+  *
+  * \return true if DP port is connected.
+  * \return false if DP port is disconnected.
+  */
+ static enum drm_connector_status
+ cdv_intel_dp_detect(struct drm_connector *connector, bool force)
+ {
+       struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       enum drm_connector_status status;
+       struct edid *edid = NULL;
+       int edp = is_edp(encoder);
+       intel_dp->has_audio = false;
+       if (edp)
+               cdv_intel_edp_panel_vdd_on(encoder);
+       status = cdv_dp_detect(encoder);
+       if (status != connector_status_connected) {
+               if (edp)
+                       cdv_intel_edp_panel_vdd_off(encoder);
+               return status;
+         }
+       if (intel_dp->force_audio) {
+               intel_dp->has_audio = intel_dp->force_audio > 0;
+       } else {
+               edid = drm_get_edid(connector, &intel_dp->adapter);
+               if (edid) {
+                       intel_dp->has_audio = drm_detect_monitor_audio(edid);
+                       kfree(edid);
+               }
+       }
+       if (edp)
+               cdv_intel_edp_panel_vdd_off(encoder);
+       return connector_status_connected;
+ }
+ static int cdv_intel_dp_get_modes(struct drm_connector *connector)
+ {
+       struct psb_intel_encoder *intel_encoder = psb_intel_attached_encoder(connector);
+       struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+       struct edid *edid = NULL;
+       int ret = 0;
+       int edp = is_edp(intel_encoder);
+       edid = drm_get_edid(connector, &intel_dp->adapter);
+       if (edid) {
+               drm_mode_connector_update_edid_property(connector, edid);
+               ret = drm_add_edid_modes(connector, edid);
+               kfree(edid);
+       }
+       if (is_edp(intel_encoder)) {
+               struct drm_device *dev = connector->dev;
+               struct drm_psb_private *dev_priv = dev->dev_private;
+               
+               cdv_intel_edp_panel_vdd_off(intel_encoder);
+               if (ret) {
+                       if (edp && !intel_dp->panel_fixed_mode) {
+                               struct drm_display_mode *newmode;
+                               list_for_each_entry(newmode, &connector->probed_modes,
+                                           head) {
+                                       if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
+                                               intel_dp->panel_fixed_mode =
+                                                       drm_mode_duplicate(dev, newmode);
+                                               break;
+                                       }
+                               }
+                       }
+                       return ret;
+               }
+               if (!intel_dp->panel_fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
+                       intel_dp->panel_fixed_mode =
+                               drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
+                       if (intel_dp->panel_fixed_mode) {
+                               intel_dp->panel_fixed_mode->type |=
+                                       DRM_MODE_TYPE_PREFERRED;
+                       }
+               }
+               if (intel_dp->panel_fixed_mode != NULL) {
+                       struct drm_display_mode *mode;
+                       mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
+                       drm_mode_probed_add(connector, mode);
+                       return 1;
+               }
+       }
+       return ret;
+ }
+ static bool
+ cdv_intel_dp_detect_audio(struct drm_connector *connector)
+ {
+       struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       struct edid *edid;
+       bool has_audio = false;
+       int edp = is_edp(encoder);
+       if (edp)
+               cdv_intel_edp_panel_vdd_on(encoder);
+       edid = drm_get_edid(connector, &intel_dp->adapter);
+       if (edid) {
+               has_audio = drm_detect_monitor_audio(edid);
+               kfree(edid);
+       }
+       if (edp)
+               cdv_intel_edp_panel_vdd_off(encoder);
+       return has_audio;
+ }
+ static int
+ cdv_intel_dp_set_property(struct drm_connector *connector,
+                     struct drm_property *property,
+                     uint64_t val)
+ {
+       struct drm_psb_private *dev_priv = connector->dev->dev_private;
+       struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
+       struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+       int ret;
+       ret = drm_connector_property_set_value(connector, property, val);
+       if (ret)
+               return ret;
+       if (property == dev_priv->force_audio_property) {
+               int i = val;
+               bool has_audio;
+               if (i == intel_dp->force_audio)
+                       return 0;
+               intel_dp->force_audio = i;
+               if (i == 0)
+                       has_audio = cdv_intel_dp_detect_audio(connector);
+               else
+                       has_audio = i > 0;
+               if (has_audio == intel_dp->has_audio)
+                       return 0;
+               intel_dp->has_audio = has_audio;
+               goto done;
+       }
+       if (property == dev_priv->broadcast_rgb_property) {
+               if (val == !!intel_dp->color_range)
+                       return 0;
+               intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
+               goto done;
+       }
+       return -EINVAL;
+ done:
+       if (encoder->base.crtc) {
+               struct drm_crtc *crtc = encoder->base.crtc;
+               drm_crtc_helper_set_mode(crtc, &crtc->mode,
+                                        crtc->x, crtc->y,
+                                        crtc->fb);
+       }
+       return 0;
+ }
+ static void
+ cdv_intel_dp_destroy(struct drm_connector *connector)
+ {
+       struct psb_intel_encoder *psb_intel_encoder =
+                                       psb_intel_attached_encoder(connector);
+       struct cdv_intel_dp *intel_dp = psb_intel_encoder->dev_priv;
+       if (is_edp(psb_intel_encoder)) {
+       /*      cdv_intel_panel_destroy_backlight(connector->dev); */
+               if (intel_dp->panel_fixed_mode) {
+                       kfree(intel_dp->panel_fixed_mode);
+                       intel_dp->panel_fixed_mode = NULL;
+               }
+       }
+       i2c_del_adapter(&intel_dp->adapter);
+       drm_sysfs_connector_remove(connector);
+       drm_connector_cleanup(connector);
+       kfree(connector);
+ }
+ static void cdv_intel_dp_encoder_destroy(struct drm_encoder *encoder)
+ {
+       drm_encoder_cleanup(encoder);
+ }
+ static const struct drm_encoder_helper_funcs cdv_intel_dp_helper_funcs = {
+       .dpms = cdv_intel_dp_dpms,
+       .mode_fixup = cdv_intel_dp_mode_fixup,
+       .prepare = cdv_intel_dp_prepare,
+       .mode_set = cdv_intel_dp_mode_set,
+       .commit = cdv_intel_dp_commit,
+ };
+ static const struct drm_connector_funcs cdv_intel_dp_connector_funcs = {
+       .dpms = drm_helper_connector_dpms,
+       .detect = cdv_intel_dp_detect,
+       .fill_modes = drm_helper_probe_single_connector_modes,
+       .set_property = cdv_intel_dp_set_property,
+       .destroy = cdv_intel_dp_destroy,
+ };
+ static const struct drm_connector_helper_funcs cdv_intel_dp_connector_helper_funcs = {
+       .get_modes = cdv_intel_dp_get_modes,
+       .mode_valid = cdv_intel_dp_mode_valid,
+       .best_encoder = psb_intel_best_encoder,
+ };
+ static const struct drm_encoder_funcs cdv_intel_dp_enc_funcs = {
+       .destroy = cdv_intel_dp_encoder_destroy,
+ };
+ static void cdv_intel_dp_add_properties(struct drm_connector *connector)
+ {
+       cdv_intel_attach_force_audio_property(connector);
+       cdv_intel_attach_broadcast_rgb_property(connector);
+ }
+ /* check the VBT to see whether the eDP is on DP-D port */
+ static bool cdv_intel_dpc_is_edp(struct drm_device *dev)
+ {
+       struct drm_psb_private *dev_priv = dev->dev_private;
+       struct child_device_config *p_child;
+       int i;
+       if (!dev_priv->child_dev_num)
+               return false;
+       for (i = 0; i < dev_priv->child_dev_num; i++) {
+               p_child = dev_priv->child_dev + i;
+               if (p_child->dvo_port == PORT_IDPC &&
+                   p_child->device_type == DEVICE_TYPE_eDP)
+                       return true;
+       }
+       return false;
+ }
+ /* Cedarview display clock gating
+    We need this disable dot get correct behaviour while enabling
+    DP/eDP. TODO - investigate if we can turn it back to normality
+    after enabling */
+ static void cdv_disable_intel_clock_gating(struct drm_device *dev)
+ {
+       u32 reg_value;
+       reg_value = REG_READ(DSPCLK_GATE_D);
+       reg_value |= (DPUNIT_PIPEB_GATE_DISABLE |
+                       DPUNIT_PIPEA_GATE_DISABLE |
+                       DPCUNIT_CLOCK_GATE_DISABLE |
+                       DPLSUNIT_CLOCK_GATE_DISABLE |
+                       DPOUNIT_CLOCK_GATE_DISABLE |
+                       DPIOUNIT_CLOCK_GATE_DISABLE);   
+       REG_WRITE(DSPCLK_GATE_D, reg_value);
+       udelay(500);            
+ }
+ void
+ cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg)
+ {
+       struct psb_intel_encoder *psb_intel_encoder;
+       struct psb_intel_connector *psb_intel_connector;
+       struct drm_connector *connector;
+       struct drm_encoder *encoder;
+       struct cdv_intel_dp *intel_dp;
+       const char *name = NULL;
+       int type = DRM_MODE_CONNECTOR_DisplayPort;
+       psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL);
+       if (!psb_intel_encoder)
+               return;
+         psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL);
+         if (!psb_intel_connector)
+                 goto err_connector;
+       intel_dp = kzalloc(sizeof(struct cdv_intel_dp), GFP_KERNEL);
+       if (!intel_dp)
+               goto err_priv;
+       if ((output_reg == DP_C) && cdv_intel_dpc_is_edp(dev))
+               type = DRM_MODE_CONNECTOR_eDP;
+       connector = &psb_intel_connector->base;
+       encoder = &psb_intel_encoder->base;
+       drm_connector_init(dev, connector, &cdv_intel_dp_connector_funcs, type);
+       drm_encoder_init(dev, encoder, &cdv_intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS);
+       psb_intel_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
+       if (type == DRM_MODE_CONNECTOR_DisplayPort)
+               psb_intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
+         else
+               psb_intel_encoder->type = INTEL_OUTPUT_EDP;
+       psb_intel_encoder->dev_priv=intel_dp;
+       intel_dp->encoder = psb_intel_encoder;
+       intel_dp->output_reg = output_reg;
+       
+       drm_encoder_helper_add(encoder, &cdv_intel_dp_helper_funcs);
+       drm_connector_helper_add(connector, &cdv_intel_dp_connector_helper_funcs);
+       connector->polled = DRM_CONNECTOR_POLL_HPD;
+       connector->interlace_allowed = false;
+       connector->doublescan_allowed = false;
+       drm_sysfs_connector_add(connector);
+       /* Set up the DDC bus. */
+       switch (output_reg) {
+               case DP_B:
+                       name = "DPDDC-B";
+                       psb_intel_encoder->ddi_select = (DP_MASK | DDI0_SELECT);
+                       break;
+               case DP_C:
+                       name = "DPDDC-C";
+                       psb_intel_encoder->ddi_select = (DP_MASK | DDI1_SELECT);
+                       break;
+       }
+       cdv_disable_intel_clock_gating(dev);
+       cdv_intel_dp_i2c_init(psb_intel_connector, psb_intel_encoder, name);
+         /* FIXME:fail check */
+       cdv_intel_dp_add_properties(connector);
+       if (is_edp(psb_intel_encoder)) {
+               int ret;
+               struct edp_power_seq cur;
+                 u32 pp_on, pp_off, pp_div;
+               u32 pwm_ctrl;
+               pp_on = REG_READ(PP_CONTROL);
+               pp_on &= ~PANEL_UNLOCK_MASK;
+               pp_on |= PANEL_UNLOCK_REGS;
+               
+               REG_WRITE(PP_CONTROL, pp_on);
+               pwm_ctrl = REG_READ(BLC_PWM_CTL2);
+               pwm_ctrl |= PWM_PIPE_B;
+               REG_WRITE(BLC_PWM_CTL2, pwm_ctrl);
+                 pp_on = REG_READ(PP_ON_DELAYS);
+                 pp_off = REG_READ(PP_OFF_DELAYS);
+                 pp_div = REG_READ(PP_DIVISOR);
+       
+               /* Pull timing values out of registers */
+                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
+                         PANEL_POWER_UP_DELAY_SHIFT;
+                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
+                         PANEL_LIGHT_ON_DELAY_SHIFT;
+                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
+                         PANEL_LIGHT_OFF_DELAY_SHIFT;
+                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
+                         PANEL_POWER_DOWN_DELAY_SHIFT;
+                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
+                                PANEL_POWER_CYCLE_DELAY_SHIFT);
+                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
+                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
+               intel_dp->panel_power_up_delay = cur.t1_t3 / 10;
+                 intel_dp->backlight_on_delay = cur.t8 / 10;
+                 intel_dp->backlight_off_delay = cur.t9 / 10;
+                 intel_dp->panel_power_down_delay = cur.t10 / 10;
+                 intel_dp->panel_power_cycle_delay = (cur.t11_t12 - 1) * 100;
+                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
+                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
+                               intel_dp->panel_power_cycle_delay);
+                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
+                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
+               cdv_intel_edp_panel_vdd_on(psb_intel_encoder);
+               ret = cdv_intel_dp_aux_native_read(psb_intel_encoder, DP_DPCD_REV,
+                                              intel_dp->dpcd,
+                                              sizeof(intel_dp->dpcd));
+               cdv_intel_edp_panel_vdd_off(psb_intel_encoder);
+               if (ret == 0) {
+                       /* if this fails, presume the device is a ghost */
+                       DRM_INFO("failed to retrieve link info, disabling eDP\n");
+                       cdv_intel_dp_encoder_destroy(encoder);
+                       cdv_intel_dp_destroy(connector);
+                       goto err_priv;
+               } else {
+                       DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n",
+                               intel_dp->dpcd[0], intel_dp->dpcd[1], 
+                               intel_dp->dpcd[2], intel_dp->dpcd[3]);
+                       
+               }
+               /* The CDV reference driver moves pnale backlight setup into the displays that
+                  have a backlight: this is a good idea and one we should probably adopt, however
+                  we need to migrate all the drivers before we can do that */
+                 /*cdv_intel_panel_setup_backlight(dev); */
+       }
+       return;
+ err_priv:
+       kfree(psb_intel_connector);
+ err_connector:
+       kfree(psb_intel_encoder);
+ }
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  #include <linux/kref.h>
  
  #include <drm/drmP.h>
 -#include "drm_global.h"
 -#include "gma_drm.h"
 +#include <drm/drm_global.h>
- #include "gem_glue.h"
 +#include <drm/gma_drm.h>
  #include "psb_reg.h"
  #include "psb_intel_drv.h"
+ #include "intel_bios.h"
  #include "gtt.h"
  #include "power.h"
  #include "opregion.h"
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  #include <linux/i2c.h>
  #include <linux/slab.h>
  #include <linux/export.h>
 -#include "drmP.h"
 -#include "drm.h"
 -#include "drm_crtc.h"
 -#include "drm_crtc_helper.h"
 -#include "drm_edid.h"
 +#include <drm/drmP.h>
 +#include <drm/drm_crtc.h>
 +#include <drm/drm_crtc_helper.h>
 +#include <drm/drm_edid.h>
  #include "intel_drv.h"
 -#include "i915_drm.h"
 +#include <drm/i915_drm.h>
  #include "i915_drv.h"
- #include <drm/drm_dp_helper.h>
  
- #define DP_RECEIVER_CAP_SIZE  0xf
  #define DP_LINK_STATUS_SIZE   6
  #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
  
  #define __INTEL_DRV_H__
  
  #include <linux/i2c.h>
 -#include "i915_drm.h"
 +#include <drm/i915_drm.h>
  #include "i915_drv.h"
 -#include "drm_crtc.h"
 -#include "drm_crtc_helper.h"
 -#include "drm_fb_helper.h"
 -#include "drm_dp_helper.h"
 +#include <drm/drm_crtc.h>
 +#include <drm/drm_crtc_helper.h>
 +#include <drm/drm_fb_helper.h>
++#include <drm/drm_dp_helper.h>
  
  #define _wait_for(COND, MS, W) ({ \
        unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);       \
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index 0000000,abb135f..acf818c
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,271 +1,271 @@@
+ /*
+  * Copyright 2011 Red Hat Inc.
+  *
+  * Permission is hereby granted, free of charge, to any person obtaining a
+  * copy of this software and associated documentation files (the "Software"),
+  * to deal in the Software without restriction, including without limitation
+  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+  * and/or sell copies of the Software, and to permit persons to whom the
+  * Software is furnished to do so, subject to the following conditions:
+  *
+  * The above copyright notice and this permission notice shall be included in
+  * all copies or substantial portions of the Software.
+  *
+  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+  * OTHER DEALINGS IN THE SOFTWARE.
+  *
+  * Authors: Ben Skeggs
+  */
+ #include <subdev/gpio.h>
+ #include <subdev/bios.h>
+ #include <subdev/bios/gpio.h>
+ static int
+ nouveau_gpio_drive(struct nouveau_gpio *gpio,
+                  int idx, int line, int dir, int out)
+ {
+       return gpio->drive ? gpio->drive(gpio, line, dir, out) : -ENODEV;
+ }
+ static int
+ nouveau_gpio_sense(struct nouveau_gpio *gpio, int idx, int line)
+ {
+       return gpio->sense ? gpio->sense(gpio, line) : -ENODEV;
+ }
+ static int
+ nouveau_gpio_find(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line,
+                 struct dcb_gpio_func *func)
+ {
+       if (line == 0xff && tag == 0xff)
+               return -EINVAL;
+       if (!dcb_gpio_parse(nouveau_bios(gpio), idx, tag, line, func))
+               return 0;
+       /* Apple iMac G4 NV18 */
+       if (nv_device_match(nv_object(gpio), 0x0189, 0x10de, 0x0010)) {
+               if (tag == DCB_GPIO_TVDAC0) {
+                       *func = (struct dcb_gpio_func) {
+                               .func = DCB_GPIO_TVDAC0,
+                               .line = 4,
+                               .log[0] = 0,
+                               .log[1] = 1,
+                       };
+                       return 0;
+               }
+       }
+       return -EINVAL;
+ }
+ static int
+ nouveau_gpio_set(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line, int state)
+ {
+       struct dcb_gpio_func func;
+       int ret;
+       ret = nouveau_gpio_find(gpio, idx, tag, line, &func);
+       if (ret == 0) {
+               int dir = !!(func.log[state] & 0x02);
+               int out = !!(func.log[state] & 0x01);
+               ret = nouveau_gpio_drive(gpio, idx, func.line, dir, out);
+       }
+       return ret;
+ }
+ static int
+ nouveau_gpio_get(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line)
+ {
+       struct dcb_gpio_func func;
+       int ret;
+       ret = nouveau_gpio_find(gpio, idx, tag, line, &func);
+       if (ret == 0) {
+               ret = nouveau_gpio_sense(gpio, idx, func.line);
+               if (ret >= 0)
+                       ret = (ret == (func.log[1] & 1));
+       }
+       return ret;
+ }
+ static int
+ nouveau_gpio_irq(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line, bool on)
+ {
+       struct dcb_gpio_func func;
+       int ret;
+       ret = nouveau_gpio_find(gpio, idx, tag, line, &func);
+       if (ret == 0) {
+               if (idx == 0 && gpio->irq_enable)
+                       gpio->irq_enable(gpio, func.line, on);
+               else
+                       ret = -ENODEV;
+       }
+       return ret;
+ }
+ struct gpio_isr {
+       struct nouveau_gpio *gpio;
+       struct list_head head;
+       struct work_struct work;
+       int idx;
+       struct dcb_gpio_func func;
+       void (*handler)(void *, int);
+       void *data;
+       bool inhibit;
+ };
+ static void
+ nouveau_gpio_isr_bh(struct work_struct *work)
+ {
+       struct gpio_isr *isr = container_of(work, struct gpio_isr, work);
+       struct nouveau_gpio *gpio = isr->gpio;
+       unsigned long flags;
+       int state;
+       state = nouveau_gpio_get(gpio, isr->idx, isr->func.func,
+                                                isr->func.line);
+       if (state >= 0)
+               isr->handler(isr->data, state);
+       spin_lock_irqsave(&gpio->lock, flags);
+       isr->inhibit = false;
+       spin_unlock_irqrestore(&gpio->lock, flags);
+ }
+ static void
+ nouveau_gpio_isr_run(struct nouveau_gpio *gpio, int idx, u32 line_mask)
+ {
+       struct gpio_isr *isr;
+       if (idx != 0)
+               return;
+       spin_lock(&gpio->lock);
+       list_for_each_entry(isr, &gpio->isr, head) {
+               if (line_mask & (1 << isr->func.line)) {
+                       if (isr->inhibit)
+                               continue;
+                       isr->inhibit = true;
+                       schedule_work(&isr->work);
+               }
+       }
+       spin_unlock(&gpio->lock);
+ }
+ static int
+ nouveau_gpio_isr_add(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line,
+                    void (*handler)(void *, int), void *data)
+ {
+       struct gpio_isr *isr;
+       unsigned long flags;
+       int ret;
+       isr = kzalloc(sizeof(*isr), GFP_KERNEL);
+       if (!isr)
+               return -ENOMEM;
+       ret = nouveau_gpio_find(gpio, idx, tag, line, &isr->func);
+       if (ret) {
+               kfree(isr);
+               return ret;
+       }
+       INIT_WORK(&isr->work, nouveau_gpio_isr_bh);
+       isr->gpio = gpio;
+       isr->handler = handler;
+       isr->data = data;
+       isr->idx = idx;
+       spin_lock_irqsave(&gpio->lock, flags);
+       list_add(&isr->head, &gpio->isr);
+       spin_unlock_irqrestore(&gpio->lock, flags);
+       return 0;
+ }
+ static void
+ nouveau_gpio_isr_del(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line,
+                    void (*handler)(void *, int), void *data)
+ {
+       struct gpio_isr *isr, *tmp;
+       struct dcb_gpio_func func;
+       unsigned long flags;
+       LIST_HEAD(tofree);
+       int ret;
+       ret = nouveau_gpio_find(gpio, idx, tag, line, &func);
+       if (ret == 0) {
+               spin_lock_irqsave(&gpio->lock, flags);
+               list_for_each_entry_safe(isr, tmp, &gpio->isr, head) {
+                       if (memcmp(&isr->func, &func, sizeof(func)) ||
+                           isr->idx != idx ||
+                           isr->handler != handler || isr->data != data)
+                               continue;
+                       list_move_tail(&isr->head, &tofree);
+               }
+               spin_unlock_irqrestore(&gpio->lock, flags);
+               list_for_each_entry_safe(isr, tmp, &tofree, head) {
 -                      flush_work_sync(&isr->work);
++                      flush_work(&isr->work);
+                       kfree(isr);
+               }
+       }
+ }
+ int
+ nouveau_gpio_create_(struct nouveau_object *parent,
+                    struct nouveau_object *engine,
+                    struct nouveau_oclass *oclass, int length, void **pobject)
+ {
+       struct nouveau_gpio *gpio;
+       int ret;
+       ret = nouveau_subdev_create_(parent, engine, oclass, 0, "GPIO", "gpio",
+                                    length, pobject);
+       gpio = *pobject;
+       if (ret)
+               return ret;
+       gpio->find = nouveau_gpio_find;
+       gpio->set  = nouveau_gpio_set;
+       gpio->get  = nouveau_gpio_get;
+       gpio->irq  = nouveau_gpio_irq;
+       gpio->isr_run = nouveau_gpio_isr_run;
+       gpio->isr_add = nouveau_gpio_isr_add;
+       gpio->isr_del = nouveau_gpio_isr_del;
+       INIT_LIST_HEAD(&gpio->isr);
+       spin_lock_init(&gpio->lock);
+       return 0;
+ }
+ static struct dmi_system_id gpio_reset_ids[] = {
+       {
+               .ident = "Apple Macbook 10,1",
+               .matches = {
+                       DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
+                       DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro10,1"),
+               }
+       },
+       { }
+ };
+ int
+ nouveau_gpio_init(struct nouveau_gpio *gpio)
+ {
+       int ret = nouveau_subdev_init(&gpio->base);
+       if (ret == 0 && gpio->reset) {
+               if (dmi_check_system(gpio_reset_ids))
+                       gpio->reset(gpio);
+       }
+       return ret;
+ }
@@@ -7,15 -7,13 +7,13 @@@
  #include <acpi/acpi.h>
  #include <linux/mxm-wmi.h>
  
- #include <drm/drmP.h>
- #include <drm/drm_crtc_helper.h>
- #include "nouveau_drv.h"
- #include <drm/nouveau_drm.h>
- #include "nv50_display.h"
- #include "nouveau_connector.h"
  #include <linux/vga_switcheroo.h>
  
 -#include "drm_edid.h"
++#include <drm/drm_edid.h>
+ #include "nouveau_drm.h"
+ #include "nouveau_acpi.h"
  #define NOUVEAU_DSM_LED 0x02
  #define NOUVEAU_DSM_LED_STATE 0x00
  #define NOUVEAU_DSM_LED_OFF 0x10
   * SOFTWARE.
   */
  
+ #include <subdev/bios.h>
 -#include "drmP.h"
 +#include <drm/drmP.h>
- #define NV_DEBUG_NOTRACE
- #include "nouveau_drv.h"
++
+ #include "nouveau_drm.h"
+ #include "nouveau_reg.h"
  #include "nouveau_hw.h"
  #include "nouveau_encoder.h"
- #include "nouveau_gpio.h"
  
  #include <linux/io-mapping.h>
  #include <linux/firmware.h>
   * SOFTWARE.
   */
  
 -#include "drmP.h"
 +#include <drm/drmP.h>
- #include "nouveau_drv.h"
++
+ #include "nouveau_drm.h"
+ #include "nouveau_reg.h"
  #include "nouveau_hw.h"
  
  /****************************************************************************\
  
  #include <acpi/button.h>
  
 -#include "drmP.h"
 -#include "drm_edid.h"
 -#include "drm_crtc_helper.h"
 +#include <drm/drmP.h>
 +#include <drm/drm_edid.h>
 +#include <drm/drm_crtc_helper.h>
  
  #include "nouveau_reg.h"
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
+ #include "nouveau_hw.h"
+ #include "nouveau_acpi.h"
+ #include "nouveau_display.h"
+ #include "nouveau_connector.h"
  #include "nouveau_encoder.h"
  #include "nouveau_crtc.h"
- #include "nouveau_connector.h"
- #include "nouveau_gpio.h"
- #include "nouveau_hw.h"
+ #include <subdev/i2c.h>
+ #include <subdev/gpio.h>
+ MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
+ static int nouveau_tv_disable = 0;
+ module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
+ MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
+ static int nouveau_ignorelid = 0;
+ module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
+ MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (default: enabled)");
+ static int nouveau_duallink = 1;
+ module_param_named(duallink, nouveau_duallink, int, 0400);
  
  static void nouveau_connector_hotplug(void *, int);
  
@@@ -27,8 -27,9 +27,9 @@@
  #ifndef __NOUVEAU_CONNECTOR_H__
  #define __NOUVEAU_CONNECTOR_H__
  
 -#include "drm_edid.h"
 +#include <drm/drm_edid.h>
- #include "nouveau_i2c.h"
+ struct nouveau_i2c_port;
  
  enum nouveau_underscan_type {
        UNDERSCAN_OFF,
   *
   */
  
 -#include "drmP.h"
 -#include "drm_crtc_helper.h"
 +#include <drm/drmP.h>
 +#include <drm/drm_crtc_helper.h>
- #include "nouveau_drv.h"
- #include "nouveau_fb.h"
  #include "nouveau_fbcon.h"
  #include "nouveau_hw.h"
  #include "nouveau_crtc.h"
   * Authors: Ben Skeggs
   */
  
 -#include "drmP.h"
 -#include "drm_dp_helper.h"
 +#include <drm/drmP.h>
++#include <drm/drm_dp_helper.h>
  
- #include "nouveau_drv.h"
- #include "nouveau_i2c.h"
+ #include "nouveau_drm.h"
  #include "nouveau_connector.h"
  #include "nouveau_encoder.h"
  #include "nouveau_crtc.h"
index 0000000,e96507e..ccae8c2
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,693 +1,693 @@@
+ /*
+  * Copyright 2012 Red Hat Inc.
+  *
+  * Permission is hereby granted, free of charge, to any person obtaining a
+  * copy of this software and associated documentation files (the "Software"),
+  * to deal in the Software without restriction, including without limitation
+  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+  * and/or sell copies of the Software, and to permit persons to whom the
+  * Software is furnished to do so, subject to the following conditions:
+  *
+  * The above copyright notice and this permission notice shall be included in
+  * all copies or substantial portions of the Software.
+  *
+  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+  * OTHER DEALINGS IN THE SOFTWARE.
+  *
+  * Authors: Ben Skeggs
+  */
+ #include <linux/console.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+ #include <core/device.h>
+ #include <core/client.h>
+ #include <core/gpuobj.h>
+ #include <core/class.h>
+ #include <subdev/device.h>
+ #include <subdev/vm.h>
+ #include "nouveau_drm.h"
+ #include "nouveau_irq.h"
+ #include "nouveau_dma.h"
+ #include "nouveau_ttm.h"
+ #include "nouveau_gem.h"
+ #include "nouveau_agp.h"
+ #include "nouveau_vga.h"
+ #include "nouveau_pm.h"
+ #include "nouveau_acpi.h"
+ #include "nouveau_bios.h"
+ #include "nouveau_ioctl.h"
+ #include "nouveau_abi16.h"
+ #include "nouveau_fbcon.h"
+ #include "nouveau_fence.h"
+ #include "nouveau_ttm.h"
+ MODULE_PARM_DESC(config, "option string to pass to driver core");
+ static char *nouveau_config;
+ module_param_named(config, nouveau_config, charp, 0400);
+ MODULE_PARM_DESC(debug, "debug string to pass to driver core");
+ static char *nouveau_debug;
+ module_param_named(debug, nouveau_debug, charp, 0400);
+ MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
+ static int nouveau_noaccel = 0;
+ module_param_named(noaccel, nouveau_noaccel, int, 0400);
+ MODULE_PARM_DESC(modeset, "enable driver");
+ static int nouveau_modeset = -1;
+ module_param_named(modeset, nouveau_modeset, int, 0400);
+ static struct drm_driver driver;
+ static u64
+ nouveau_name(struct pci_dev *pdev)
+ {
+       u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
+       name |= pdev->bus->number << 16;
+       name |= PCI_SLOT(pdev->devfn) << 8;
+       return name | PCI_FUNC(pdev->devfn);
+ }
+ static int
+ nouveau_cli_create(struct pci_dev *pdev, const char *name,
+                  int size, void **pcli)
+ {
+       struct nouveau_cli *cli;
+       int ret;
+       ret = nouveau_client_create_(name, nouveau_name(pdev), nouveau_config,
+                                    nouveau_debug, size, pcli);
+       cli = *pcli;
+       if (ret)
+               return ret;
+       mutex_init(&cli->mutex);
+       return 0;
+ }
+ static void
+ nouveau_cli_destroy(struct nouveau_cli *cli)
+ {
+       struct nouveau_object *client = nv_object(cli);
+       nouveau_vm_ref(NULL, &cli->base.vm, NULL);
+       nouveau_client_fini(&cli->base, false);
+       atomic_set(&client->refcount, 1);
+       nouveau_object_ref(NULL, &client);
+ }
+ static void
+ nouveau_accel_fini(struct nouveau_drm *drm)
+ {
+       nouveau_gpuobj_ref(NULL, &drm->notify);
+       nouveau_channel_del(&drm->channel);
+       nouveau_channel_del(&drm->cechan);
+       if (drm->fence)
+               nouveau_fence(drm)->dtor(drm);
+ }
+ static void
+ nouveau_accel_init(struct nouveau_drm *drm)
+ {
+       struct nouveau_device *device = nv_device(drm->device);
+       struct nouveau_object *object;
+       u32 arg0, arg1;
+       int ret;
+       if (nouveau_noaccel)
+               return;
+       /* initialise synchronisation routines */
+       if      (device->card_type < NV_10) ret = nv04_fence_create(drm);
+       else if (device->chipset   <  0x84) ret = nv10_fence_create(drm);
+       else if (device->card_type < NV_C0) ret = nv84_fence_create(drm);
+       else                                ret = nvc0_fence_create(drm);
+       if (ret) {
+               NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
+               nouveau_accel_fini(drm);
+               return;
+       }
+       if (device->card_type >= NV_E0) {
+               ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE,
+                                         NVDRM_CHAN + 1,
+                                         NVE0_CHANNEL_IND_ENGINE_CE0 |
+                                         NVE0_CHANNEL_IND_ENGINE_CE1, 0,
+                                         &drm->cechan);
+               if (ret)
+                       NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
+               arg0 = NVE0_CHANNEL_IND_ENGINE_GR;
+               arg1 = 0;
+       } else {
+               arg0 = NvDmaFB;
+               arg1 = NvDmaTT;
+       }
+       ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE, NVDRM_CHAN,
+                                 arg0, arg1, &drm->channel);
+       if (ret) {
+               NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
+               nouveau_accel_fini(drm);
+               return;
+       }
+       if (device->card_type < NV_C0) {
+               ret = nouveau_gpuobj_new(drm->device, NULL, 32, 0, 0,
+                                       &drm->notify);
+               if (ret) {
+                       NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
+                       nouveau_accel_fini(drm);
+                       return;
+               }
+               ret = nouveau_object_new(nv_object(drm),
+                                        drm->channel->handle, NvNotify0,
+                                        0x003d, &(struct nv_dma_class) {
+                                               .flags = NV_DMA_TARGET_VRAM |
+                                                        NV_DMA_ACCESS_RDWR,
+                                               .start = drm->notify->addr,
+                                               .limit = drm->notify->addr + 31
+                                               }, sizeof(struct nv_dma_class),
+                                        &object);
+               if (ret) {
+                       nouveau_accel_fini(drm);
+                       return;
+               }
+       }
+       nouveau_bo_move_init(drm);
+ }
+ static int __devinit
+ nouveau_drm_probe(struct pci_dev *pdev, const struct pci_device_id *pent)
+ {
+       struct nouveau_device *device;
+       struct apertures_struct *aper;
+       bool boot = false;
+       int ret;
+       /* remove conflicting drivers (vesafb, efifb etc) */
+       aper = alloc_apertures(3);
+       if (!aper)
+               return -ENOMEM;
+       aper->ranges[0].base = pci_resource_start(pdev, 1);
+       aper->ranges[0].size = pci_resource_len(pdev, 1);
+       aper->count = 1;
+       if (pci_resource_len(pdev, 2)) {
+               aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
+               aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
+               aper->count++;
+       }
+       if (pci_resource_len(pdev, 3)) {
+               aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
+               aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
+               aper->count++;
+       }
+ #ifdef CONFIG_X86
+       boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
+ #endif
+       remove_conflicting_framebuffers(aper, "nouveaufb", boot);
+       ret = nouveau_device_create(pdev, nouveau_name(pdev), pci_name(pdev),
+                                   nouveau_config, nouveau_debug, &device);
+       if (ret)
+               return ret;
+       pci_set_master(pdev);
+       ret = drm_get_pci_dev(pdev, pent, &driver);
+       if (ret) {
+               nouveau_object_ref(NULL, (struct nouveau_object **)&device);
+               return ret;
+       }
+       return 0;
+ }
+ static int
+ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
+ {
+       struct pci_dev *pdev = dev->pdev;
+       struct nouveau_device *device;
+       struct nouveau_drm *drm;
+       int ret;
+       ret = nouveau_cli_create(pdev, "DRM", sizeof(*drm), (void**)&drm);
+       if (ret)
+               return ret;
+       dev->dev_private = drm;
+       drm->dev = dev;
+       INIT_LIST_HEAD(&drm->clients);
+       spin_lock_init(&drm->tile.lock);
+       /* make sure AGP controller is in a consistent state before we
+        * (possibly) execute vbios init tables (see nouveau_agp.h)
+        */
+       if (drm_pci_device_is_agp(dev) && dev->agp) {
+               /* dummy device object, doesn't init anything, but allows
+                * agp code access to registers
+                */
+               ret = nouveau_object_new(nv_object(drm), NVDRM_CLIENT,
+                                        NVDRM_DEVICE, 0x0080,
+                                        &(struct nv_device_class) {
+                                               .device = ~0,
+                                               .disable =
+                                                ~(NV_DEVICE_DISABLE_MMIO |
+                                                  NV_DEVICE_DISABLE_IDENTIFY),
+                                               .debug0 = ~0,
+                                        }, sizeof(struct nv_device_class),
+                                        &drm->device);
+               if (ret)
+                       goto fail_device;
+               nouveau_agp_reset(drm);
+               nouveau_object_del(nv_object(drm), NVDRM_CLIENT, NVDRM_DEVICE);
+       }
+       ret = nouveau_object_new(nv_object(drm), NVDRM_CLIENT, NVDRM_DEVICE,
+                                0x0080, &(struct nv_device_class) {
+                                       .device = ~0,
+                                       .disable = 0,
+                                       .debug0 = 0,
+                                }, sizeof(struct nv_device_class),
+                                &drm->device);
+       if (ret)
+               goto fail_device;
+       /* workaround an odd issue on nvc1 by disabling the device's
+        * nosnoop capability.  hopefully won't cause issues until a
+        * better fix is found - assuming there is one...
+        */
+       device = nv_device(drm->device);
+       if (nv_device(drm->device)->chipset == 0xc1)
+               nv_mask(device, 0x00088080, 0x00000800, 0x00000000);
+       nouveau_vga_init(drm);
+       nouveau_agp_init(drm);
+       if (device->card_type >= NV_50) {
+               ret = nouveau_vm_new(nv_device(drm->device), 0, (1ULL << 40),
+                                    0x1000, &drm->client.base.vm);
+               if (ret)
+                       goto fail_device;
+       }
+       ret = nouveau_ttm_init(drm);
+       if (ret)
+               goto fail_ttm;
+       ret = nouveau_bios_init(dev);
+       if (ret)
+               goto fail_bios;
+       ret = nouveau_irq_init(dev);
+       if (ret)
+               goto fail_irq;
+       ret = nouveau_display_create(dev);
+       if (ret)
+               goto fail_dispctor;
+       if (dev->mode_config.num_crtc) {
+               ret = nouveau_display_init(dev);
+               if (ret)
+                       goto fail_dispinit;
+       }
+       nouveau_pm_init(dev);
+       nouveau_accel_init(drm);
+       nouveau_fbcon_init(dev);
+       return 0;
+ fail_dispinit:
+       nouveau_display_destroy(dev);
+ fail_dispctor:
+       nouveau_irq_fini(dev);
+ fail_irq:
+       nouveau_bios_takedown(dev);
+ fail_bios:
+       nouveau_ttm_fini(drm);
+ fail_ttm:
+       nouveau_agp_fini(drm);
+       nouveau_vga_fini(drm);
+ fail_device:
+       nouveau_cli_destroy(&drm->client);
+       return ret;
+ }
+ static int
+ nouveau_drm_unload(struct drm_device *dev)
+ {
+       struct nouveau_drm *drm = nouveau_drm(dev);
+       nouveau_fbcon_fini(dev);
+       nouveau_accel_fini(drm);
+       nouveau_pm_fini(dev);
+       nouveau_display_fini(dev);
+       nouveau_display_destroy(dev);
+       nouveau_irq_fini(dev);
+       nouveau_bios_takedown(dev);
+       nouveau_ttm_fini(drm);
+       nouveau_agp_fini(drm);
+       nouveau_vga_fini(drm);
+       nouveau_cli_destroy(&drm->client);
+       return 0;
+ }
+ static void
+ nouveau_drm_remove(struct pci_dev *pdev)
+ {
+       struct drm_device *dev = pci_get_drvdata(pdev);
+       struct nouveau_drm *drm = nouveau_drm(dev);
+       struct nouveau_object *device;
+       device = drm->client.base.device;
+       drm_put_dev(dev);
+       nouveau_object_ref(NULL, &device);
+       nouveau_object_debug();
+ }
+ int
+ nouveau_drm_suspend(struct pci_dev *pdev, pm_message_t pm_state)
+ {
+       struct drm_device *dev = pci_get_drvdata(pdev);
+       struct nouveau_drm *drm = nouveau_drm(dev);
+       struct nouveau_cli *cli;
+       int ret;
+       if (dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
+           pm_state.event == PM_EVENT_PRETHAW)
+               return 0;
+       NV_INFO(drm, "suspending fbcon...\n");
+       nouveau_fbcon_set_suspend(dev, 1);
+       NV_INFO(drm, "suspending display...\n");
+       ret = nouveau_display_suspend(dev);
+       if (ret)
+               return ret;
+       NV_INFO(drm, "evicting buffers...\n");
+       ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
+       if (drm->fence && nouveau_fence(drm)->suspend) {
+               if (!nouveau_fence(drm)->suspend(drm))
+                       return -ENOMEM;
+       }
+       NV_INFO(drm, "suspending client object trees...\n");
+       list_for_each_entry(cli, &drm->clients, head) {
+               ret = nouveau_client_fini(&cli->base, true);
+               if (ret)
+                       goto fail_client;
+       }
+       ret = nouveau_client_fini(&drm->client.base, true);
+       if (ret)
+               goto fail_client;
+       nouveau_agp_fini(drm);
+       pci_save_state(pdev);
+       if (pm_state.event == PM_EVENT_SUSPEND) {
+               pci_disable_device(pdev);
+               pci_set_power_state(pdev, PCI_D3hot);
+       }
+       return 0;
+ fail_client:
+       list_for_each_entry_continue_reverse(cli, &drm->clients, head) {
+               nouveau_client_init(&cli->base);
+       }
+       NV_INFO(drm, "resuming display...\n");
+       nouveau_display_resume(dev);
+       return ret;
+ }
+ int
+ nouveau_drm_resume(struct pci_dev *pdev)
+ {
+       struct drm_device *dev = pci_get_drvdata(pdev);
+       struct nouveau_drm *drm = nouveau_drm(dev);
+       struct nouveau_cli *cli;
+       int ret;
+       if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
+               return 0;
+       NV_INFO(drm, "re-enabling device...\n");
+       pci_set_power_state(pdev, PCI_D0);
+       pci_restore_state(pdev);
+       ret = pci_enable_device(pdev);
+       if (ret)
+               return ret;
+       pci_set_master(pdev);
+       nouveau_agp_reset(drm);
+       NV_INFO(drm, "resuming client object trees...\n");
+       nouveau_client_init(&drm->client.base);
+       nouveau_agp_init(drm);
+       list_for_each_entry(cli, &drm->clients, head) {
+               nouveau_client_init(&cli->base);
+       }
+       if (drm->fence && nouveau_fence(drm)->resume)
+               nouveau_fence(drm)->resume(drm);
+       nouveau_run_vbios_init(dev);
+       nouveau_irq_postinstall(dev);
+       nouveau_pm_resume(dev);
+       NV_INFO(drm, "resuming display...\n");
+       nouveau_display_resume(dev);
+       return 0;
+ }
+ static int
+ nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
+ {
+       struct pci_dev *pdev = dev->pdev;
+       struct nouveau_drm *drm = nouveau_drm(dev);
+       struct nouveau_cli *cli;
+       char name[16];
+       int ret;
 -      snprintf(name, sizeof(name), "%d", fpriv->pid);
++      snprintf(name, sizeof(name), "%d", pid_nr(fpriv->pid));
+       ret = nouveau_cli_create(pdev, name, sizeof(*cli), (void **)&cli);
+       if (ret)
+               return ret;
+       if (nv_device(drm->device)->card_type >= NV_50) {
+               ret = nouveau_vm_new(nv_device(drm->device), 0, (1ULL << 40),
+                                    0x1000, &cli->base.vm);
+               if (ret) {
+                       nouveau_cli_destroy(cli);
+                       return ret;
+               }
+       }
+       fpriv->driver_priv = cli;
+       mutex_lock(&drm->client.mutex);
+       list_add(&cli->head, &drm->clients);
+       mutex_unlock(&drm->client.mutex);
+       return 0;
+ }
+ static void
+ nouveau_drm_preclose(struct drm_device *dev, struct drm_file *fpriv)
+ {
+       struct nouveau_cli *cli = nouveau_cli(fpriv);
+       struct nouveau_drm *drm = nouveau_drm(dev);
+       if (cli->abi16)
+               nouveau_abi16_fini(cli->abi16);
+       mutex_lock(&drm->client.mutex);
+       list_del(&cli->head);
+       mutex_unlock(&drm->client.mutex);
+ }
+ static void
+ nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
+ {
+       struct nouveau_cli *cli = nouveau_cli(fpriv);
+       nouveau_cli_destroy(cli);
+ }
+ static struct drm_ioctl_desc
+ nouveau_ioctls[] = {
+       DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
+       DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+       DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH),
+       DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH),
+       DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
+       DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH),
+       DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
+       DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
+       DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
+       DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
+       DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
+       DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
+ };
+ static const struct file_operations
+ nouveau_driver_fops = {
+       .owner = THIS_MODULE,
+       .open = drm_open,
+       .release = drm_release,
+       .unlocked_ioctl = drm_ioctl,
+       .mmap = nouveau_ttm_mmap,
+       .poll = drm_poll,
+       .fasync = drm_fasync,
+       .read = drm_read,
+ #if defined(CONFIG_COMPAT)
+       .compat_ioctl = nouveau_compat_ioctl,
+ #endif
+       .llseek = noop_llseek,
+ };
+ static struct drm_driver
+ driver = {
+       .driver_features =
+               DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
+               DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
+               DRIVER_MODESET | DRIVER_PRIME,
+       .load = nouveau_drm_load,
+       .unload = nouveau_drm_unload,
+       .open = nouveau_drm_open,
+       .preclose = nouveau_drm_preclose,
+       .postclose = nouveau_drm_postclose,
+       .lastclose = nouveau_vga_lastclose,
+       .irq_preinstall = nouveau_irq_preinstall,
+       .irq_postinstall = nouveau_irq_postinstall,
+       .irq_uninstall = nouveau_irq_uninstall,
+       .irq_handler = nouveau_irq_handler,
+       .get_vblank_counter = drm_vblank_count,
+       .enable_vblank = nouveau_vblank_enable,
+       .disable_vblank = nouveau_vblank_disable,
+       .ioctls = nouveau_ioctls,
+       .fops = &nouveau_driver_fops,
+       .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
+       .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
+       .gem_prime_export = nouveau_gem_prime_export,
+       .gem_prime_import = nouveau_gem_prime_import,
+       .gem_init_object = nouveau_gem_object_new,
+       .gem_free_object = nouveau_gem_object_del,
+       .gem_open_object = nouveau_gem_object_open,
+       .gem_close_object = nouveau_gem_object_close,
+       .dumb_create = nouveau_display_dumb_create,
+       .dumb_map_offset = nouveau_display_dumb_map_offset,
+       .dumb_destroy = nouveau_display_dumb_destroy,
+       .name = DRIVER_NAME,
+       .desc = DRIVER_DESC,
+ #ifdef GIT_REVISION
+       .date = GIT_REVISION,
+ #else
+       .date = DRIVER_DATE,
+ #endif
+       .major = DRIVER_MAJOR,
+       .minor = DRIVER_MINOR,
+       .patchlevel = DRIVER_PATCHLEVEL,
+ };
+ static struct pci_device_id
+ nouveau_drm_pci_table[] = {
+       {
+               PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
+               .class = PCI_BASE_CLASS_DISPLAY << 16,
+               .class_mask  = 0xff << 16,
+       },
+       {
+               PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
+               .class = PCI_BASE_CLASS_DISPLAY << 16,
+               .class_mask  = 0xff << 16,
+       },
+       {}
+ };
+ static struct pci_driver
+ nouveau_drm_pci_driver = {
+       .name = "nouveau",
+       .id_table = nouveau_drm_pci_table,
+       .probe = nouveau_drm_probe,
+       .remove = nouveau_drm_remove,
+       .suspend = nouveau_drm_suspend,
+       .resume = nouveau_drm_resume,
+ };
+ static int __init
+ nouveau_drm_init(void)
+ {
+       driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls);
+       if (nouveau_modeset == -1) {
+ #ifdef CONFIG_VGA_CONSOLE
+               if (vgacon_text_force())
+                       nouveau_modeset = 0;
+               else
+ #endif
+                       nouveau_modeset = 1;
+       }
+       if (!nouveau_modeset)
+               return 0;
+       nouveau_register_dsm_handler();
+       return drm_pci_init(&driver, &nouveau_drm_pci_driver);
+ }
+ static void __exit
+ nouveau_drm_exit(void)
+ {
+       if (!nouveau_modeset)
+               return;
+       drm_pci_exit(&driver, &nouveau_drm_pci_driver);
+       nouveau_unregister_dsm_handler();
+ }
+ module_init(nouveau_drm_init);
+ module_exit(nouveau_drm_exit);
+ MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
+ MODULE_AUTHOR(DRIVER_AUTHOR);
+ MODULE_DESCRIPTION(DRIVER_DESC);
+ MODULE_LICENSE("GPL and additional rights");
index 0000000,3c12e98..8194712
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,144 +1,144 @@@
+ #ifndef __NOUVEAU_DRMCLI_H__
+ #define __NOUVEAU_DRMCLI_H__
+ #define DRIVER_AUTHOR         "Nouveau Project"
+ #define DRIVER_EMAIL          "nouveau@lists.freedesktop.org"
+ #define DRIVER_NAME           "nouveau"
+ #define DRIVER_DESC           "nVidia Riva/TNT/GeForce/Quadro/Tesla"
+ #define DRIVER_DATE           "20120801"
+ #define DRIVER_MAJOR          1
+ #define DRIVER_MINOR          1
+ #define DRIVER_PATCHLEVEL     0
+ #include <core/client.h>
+ #include <subdev/vm.h>
+ #include <drmP.h>
+ #include <drm/nouveau_drm.h>
 -#include "ttm/ttm_bo_api.h"
 -#include "ttm/ttm_bo_driver.h"
 -#include "ttm/ttm_placement.h"
 -#include "ttm/ttm_memory.h"
 -#include "ttm/ttm_module.h"
 -#include "ttm/ttm_page_alloc.h"
++#include <drm/ttm/ttm_bo_api.h>
++#include <drm/ttm/ttm_bo_driver.h>
++#include <drm/ttm/ttm_placement.h>
++#include <drm/ttm/ttm_memory.h>
++#include <drm/ttm/ttm_module.h>
++#include <drm/ttm/ttm_page_alloc.h>
+ struct nouveau_channel;
+ #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
+ #include "nouveau_fence.h"
+ #include "nouveau_bios.h"
+ struct nouveau_drm_tile {
+       struct nouveau_fence *fence;
+       bool used;
+ };
+ enum nouveau_drm_handle {
+       NVDRM_CLIENT = 0xffffffff,
+       NVDRM_DEVICE = 0xdddddddd,
+       NVDRM_PUSH   = 0xbbbb0000, /* |= client chid */
+       NVDRM_CHAN   = 0xcccc0000, /* |= client chid */
+ };
+ struct nouveau_cli {
+       struct nouveau_client base;
+       struct list_head head;
+       struct mutex mutex;
+       void *abi16;
+ };
+ static inline struct nouveau_cli *
+ nouveau_cli(struct drm_file *fpriv)
+ {
+       return fpriv ? fpriv->driver_priv : NULL;
+ }
+ struct nouveau_drm {
+       struct nouveau_cli client;
+       struct drm_device *dev;
+       struct nouveau_object *device;
+       struct list_head clients;
+       struct {
+               enum {
+                       UNKNOWN = 0,
+                       DISABLE = 1,
+                       ENABLED = 2
+               } stat;
+               u32 base;
+               u32 size;
+       } agp;
+       /* TTM interface support */
+       struct {
+               struct drm_global_reference mem_global_ref;
+               struct ttm_bo_global_ref bo_global_ref;
+               struct ttm_bo_device bdev;
+               atomic_t validate_sequence;
+               int (*move)(struct nouveau_channel *,
+                           struct ttm_buffer_object *,
+                           struct ttm_mem_reg *, struct ttm_mem_reg *);
+               int mtrr;
+       } ttm;
+       /* GEM interface support */
+       struct {
+               u64 vram_available;
+               u64 gart_available;
+       } gem;
+       /* synchronisation */
+       void *fence;
+       /* context for accelerated drm-internal operations */
+       struct nouveau_channel *cechan;
+       struct nouveau_channel *channel;
+       struct nouveau_gpuobj *notify;
+       struct nouveau_fbdev *fbcon;
+       /* nv10-nv40 tiling regions */
+       struct {
+               struct nouveau_drm_tile reg[15];
+               spinlock_t lock;
+       } tile;
+       /* modesetting */
+       struct nvbios vbios;
+       struct nouveau_display *display;
+       struct backlight_device *backlight;
+       /* power management */
+       struct nouveau_pm *pm;
+ };
+ static inline struct nouveau_drm *
+ nouveau_drm(struct drm_device *dev)
+ {
+       return dev->dev_private;
+ }
+ static inline struct nouveau_device *
+ nouveau_dev(struct drm_device *dev)
+ {
+       return nv_device(nouveau_drm(dev)->device);
+ }
+ int nouveau_drm_suspend(struct pci_dev *, pm_message_t);
+ int nouveau_drm_resume(struct pci_dev *);
+ #define NV_FATAL(cli, fmt, args...) nv_fatal((cli), fmt, ##args)
+ #define NV_ERROR(cli, fmt, args...) nv_error((cli), fmt, ##args)
+ #define NV_WARN(cli, fmt, args...) nv_warn((cli), fmt, ##args)
+ #define NV_INFO(cli, fmt, args...) nv_info((cli), fmt, ##args)
+ #define NV_DEBUG(cli, fmt, args...) do {                                       \
+       if (drm_debug & DRM_UT_DRIVER)                                         \
+               nv_info((cli), fmt, ##args);                                   \
+ } while (0)
+ #endif
  #ifndef __NOUVEAU_ENCODER_H__
  #define __NOUVEAU_ENCODER_H__
  
+ #include <subdev/bios/dcb.h>
 -#include "drm_encoder_slave.h"
 +#include <drm/drm_encoder_slave.h>
- #include "nouveau_drv.h"
+ #include "nv04_display.h"
  
  #define NV_DPMS_CLEARED 0x80
  
  #include <linux/vga_switcheroo.h>
  #include <linux/console.h>
  
 -#include "drmP.h"
 -#include "drm.h"
 -#include "drm_crtc.h"
 -#include "drm_crtc_helper.h"
 -#include "drm_fb_helper.h"
 +#include <drm/drmP.h>
 +#include <drm/drm_crtc.h>
 +#include <drm/drm_crtc_helper.h>
 +#include <drm/drm_fb_helper.h>
- #include "nouveau_drv.h"
- #include <drm/nouveau_drm.h>
- #include "nouveau_crtc.h"
- #include "nouveau_fb.h"
+ #include "nouveau_drm.h"
+ #include "nouveau_gem.h"
+ #include "nouveau_bo.h"
  #include "nouveau_fbcon.h"
- #include "nouveau_dma.h"
+ #include "nouveau_chan.h"
+ #include "nouveau_crtc.h"
+ #include <core/client.h>
+ #include <core/device.h>
+ #include <subdev/fb.h>
+ MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
+ static int nouveau_nofbaccel = 0;
+ module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
  
  static void
  nouveau_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  #ifndef __NOUVEAU_FBCON_H__
  #define __NOUVEAU_FBCON_H__
  
 -#include "drm_fb_helper.h"
 +#include <drm/drm_fb_helper.h>
  
- #include "nouveau_fb.h"
+ #include "nouveau_display.h"
  struct nouveau_fbdev {
        struct drm_fb_helper helper;
        struct nouveau_framebuffer nouveau_fb;
   * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
   *
   */
  #include <linux/dma-buf.h>
- #include <drm/drmP.h>
 -#include <nouveau_drm.h>
  
- #include "nouveau_drv.h"
- #include <drm/nouveau_drm.h>
+ #include <subdev/fb.h>
+ #include "nouveau_drm.h"
  #include "nouveau_dma.h"
  #include "nouveau_fence.h"
+ #include "nouveau_abi16.h"
  
- #define nouveau_gem_pushbuf_sync(chan) 0
+ #include "nouveau_ttm.h"
+ #include "nouveau_gem.h"
  
  int
  nouveau_gem_object_new(struct drm_gem_object *gem)
index 0000000,085ece9..5c10492
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,43 +1,43 @@@
+ #ifndef __NOUVEAU_GEM_H__
+ #define __NOUVEAU_GEM_H__
 -#include "drmP.h"
++#include <drm/drmP.h>
 -#include <nouveau_drm.h>
++#include "nouveau_drm.h"
+ #include "nouveau_bo.h"
+ #define nouveau_bo_tile_layout(nvbo)                          \
+       ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
+ static inline struct nouveau_bo *
+ nouveau_gem_object(struct drm_gem_object *gem)
+ {
+       return gem ? gem->driver_private : NULL;
+ }
+ /* nouveau_gem.c */
+ extern int nouveau_gem_new(struct drm_device *, int size, int align,
+                          uint32_t domain, uint32_t tile_mode,
+                          uint32_t tile_flags, struct nouveau_bo **);
+ extern int nouveau_gem_object_new(struct drm_gem_object *);
+ extern void nouveau_gem_object_del(struct drm_gem_object *);
+ extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *);
+ extern void nouveau_gem_object_close(struct drm_gem_object *,
+                                    struct drm_file *);
+ extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
+                                struct drm_file *);
+ extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
+                                    struct drm_file *);
+ extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
+                                     struct drm_file *);
+ extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
+                                     struct drm_file *);
+ extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
+                                 struct drm_file *);
+ extern struct dma_buf *nouveau_gem_prime_export(struct drm_device *dev,
+                               struct drm_gem_object *obj, int flags);
+ extern struct drm_gem_object *nouveau_gem_prime_import(struct drm_device *dev,
+                               struct dma_buf *dma_buf);
+ #endif
@@@ -22,8 -22,8 +22,8 @@@
   * Authors: Ben Skeggs
   */
  
 -#include "drmP.h"
 +#include <drm/drmP.h>
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
  #include "nouveau_connector.h"
  #include "nouveau_encoder.h"
  #include "nouveau_crtc.h"
   * SOFTWARE.
   */
  
 -#include "drmP.h"
 +#include <drm/drmP.h>
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
  #include "nouveau_hw.h"
  
+ #include <subdev/bios/pll.h>
+ #include <subdev/clock.h>
+ #include <subdev/timer.h>
  #define CHIPSET_NFORCE 0x01a0
  #define CHIPSET_NFORCE2 0x01f0
  
  #ifndef __NOUVEAU_HW_H__
  #define __NOUVEAU_HW_H__
  
 -#include "drmP.h"
 +#include <drm/drmP.h>
- #include "nouveau_drv.h"
+ #include "nv04_display.h"
+ #include <subdev/bios/pll.h>
  
  #define MASK(field) ( \
        (0xffffffff >> (31 - ((1 ? field) - (0 ? field)))) << (0 ? field))
  
  #include <linux/compat.h>
  
 -#include "drmP.h"
 -#include "drm.h"
 +#include <drm/drmP.h>
  
- #include "nouveau_drv.h"
+ #include "nouveau_ioctl.h"
  
  /**
   * Called whenever a 32-bit process running under a 64-bit kernel
   * Authors: Ben Skeggs
   */
  
 -#include "drmP.h"
 +#include <drm/drmP.h>
  
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
+ #include "nouveau_reg.h"
  #include "nouveau_pm.h"
  
  static u8 *
  #include <linux/hwmon.h>
  #include <linux/hwmon-sysfs.h>
  
- static int
- nouveau_pwmfan_get(struct drm_device *dev)
- {
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
-       struct gpio_func gpio;
-       u32 divs, duty;
-       int ret;
 -#include "drmP.h"
++#include <drm/drmP.h>
  
-       if (!pm->pwm_get)
-               return -ENODEV;
+ #include "nouveau_drm.h"
+ #include "nouveau_pm.h"
  
-       ret = nouveau_gpio_find(dev, 0, DCB_GPIO_PWM_FAN, 0xff, &gpio);
-       if (ret == 0) {
-               ret = pm->pwm_get(dev, gpio.line, &divs, &duty);
-               if (ret == 0 && divs) {
-                       divs = max(divs, duty);
-                       if (dev_priv->card_type <= NV_40 || (gpio.log[0] & 1))
-                               duty = divs - duty;
-                       return (duty * 100) / divs;
-               }
+ #include <subdev/gpio.h>
+ #include <subdev/timer.h>
+ #include <subdev/therm.h>
  
-               return nouveau_gpio_func_get(dev, gpio.func) * 100;
-       }
+ MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
+ static char *nouveau_perflvl;
+ module_param_named(perflvl, nouveau_perflvl, charp, 0400);
  
-       return -ENODEV;
- }
- static int
- nouveau_pwmfan_set(struct drm_device *dev, int percent)
- {
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
-       struct gpio_func gpio;
-       u32 divs, duty;
-       int ret;
-       if (!pm->pwm_set)
-               return -ENODEV;
-       ret = nouveau_gpio_find(dev, 0, DCB_GPIO_PWM_FAN, 0xff, &gpio);
-       if (ret == 0) {
-               divs = pm->fan.pwm_divisor;
-               if (pm->fan.pwm_freq) {
-                       /*XXX: PNVIO clock more than likely... */
-                       divs = 135000 / pm->fan.pwm_freq;
-                       if (dev_priv->chipset < 0xa3)
-                               divs /= 4;
-               }
-               duty = ((divs * percent) + 99) / 100;
-               if (dev_priv->card_type <= NV_40 || (gpio.log[0] & 1))
-                       duty = divs - duty;
-               ret = pm->pwm_set(dev, gpio.line, divs, duty);
-               if (!ret)
-                       pm->fan.percent = percent;
-               return ret;
-       }
-       return -ENODEV;
- }
+ MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
+ static int nouveau_perflvl_wr;
+ module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
  
  static int
  nouveau_pm_perflvl_aux(struct drm_device *dev, struct nouveau_pm_level *perflvl,
   * Authors: Dave Airlie
   */
  
- #include <drm/drmP.h>
+ #include <linux/dma-buf.h>
  
- #include "nouveau_drv.h"
- #include <drm/nouveau_drm.h>
- #include "nouveau_dma.h"
 -#include "drmP.h"
 -#include "drm.h"
++#include <drm/drmP.h>
  
- #include <linux/dma-buf.h>
+ #include "nouveau_drm.h"
+ #include "nouveau_gem.h"
  
  static struct sg_table *nouveau_gem_map_dma_buf(struct dma_buf_attachment *attachment,
                                          enum dma_data_direction dir)
index 0000000,7bf7d13..6f0ac64
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,99 +1,99 @@@
+ #include <linux/vgaarb.h>
+ #include <linux/vga_switcheroo.h>
 -#include "drmP.h"
 -#include "drm_crtc_helper.h"
++#include <drm/drmP.h>
++#include <drm/drm_crtc_helper.h>
+ #include "nouveau_drm.h"
+ #include "nouveau_acpi.h"
+ #include "nouveau_fbcon.h"
+ #include "nouveau_vga.h"
+ static unsigned int
+ nouveau_vga_set_decode(void *priv, bool state)
+ {
+       struct nouveau_device *device = nouveau_dev(priv);
+       if (device->chipset >= 0x40)
+               nv_wr32(device, 0x088054, state);
+       else
+               nv_wr32(device, 0x001854, state);
+       if (state)
+               return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
+                      VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
+       else
+               return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
+ }
+ static void
+ nouveau_switcheroo_set_state(struct pci_dev *pdev,
+                            enum vga_switcheroo_state state)
+ {
+       struct drm_device *dev = pci_get_drvdata(pdev);
+       pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
+       if (state == VGA_SWITCHEROO_ON) {
+               printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
+               dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+               nouveau_drm_resume(pdev);
+               drm_kms_helper_poll_enable(dev);
+               dev->switch_power_state = DRM_SWITCH_POWER_ON;
+       } else {
+               printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
+               dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+               drm_kms_helper_poll_disable(dev);
+               nouveau_switcheroo_optimus_dsm();
+               nouveau_drm_suspend(pdev, pmm);
+               dev->switch_power_state = DRM_SWITCH_POWER_OFF;
+       }
+ }
+ static void
+ nouveau_switcheroo_reprobe(struct pci_dev *pdev)
+ {
+       struct drm_device *dev = pci_get_drvdata(pdev);
+       nouveau_fbcon_output_poll_changed(dev);
+ }
+ static bool
+ nouveau_switcheroo_can_switch(struct pci_dev *pdev)
+ {
+       struct drm_device *dev = pci_get_drvdata(pdev);
+       bool can_switch;
+       spin_lock(&dev->count_lock);
+       can_switch = (dev->open_count == 0);
+       spin_unlock(&dev->count_lock);
+       return can_switch;
+ }
+ static const struct vga_switcheroo_client_ops
+ nouveau_switcheroo_ops = {
+       .set_gpu_state = nouveau_switcheroo_set_state,
+       .reprobe = nouveau_switcheroo_reprobe,
+       .can_switch = nouveau_switcheroo_can_switch,
+ };
+ void
+ nouveau_vga_init(struct nouveau_drm *drm)
+ {
+       struct drm_device *dev = drm->dev;
+       vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
+       vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops);
+ }
+ void
+ nouveau_vga_fini(struct nouveau_drm *drm)
+ {
+       struct drm_device *dev = drm->dev;
+       vga_switcheroo_unregister_client(dev->pdev);
+       vga_client_register(dev->pdev, NULL, NULL, NULL);
+ }
+ void
+ nouveau_vga_lastclose(struct drm_device *dev)
+ {
+       vga_switcheroo_process_delayed_switch();
+ }
   * Authors: Ben Skeggs
   */
  
 -#include "drmP.h"
 +#include <drm/drmP.h>
  
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
  #include "nouveau_pm.h"
- #include "nouveau_gpio.h"
  
- static const enum dcb_gpio_tag vidtag[] = { 0x04, 0x05, 0x06, 0x1a, 0x73 };
+ #include <subdev/bios/gpio.h>
+ #include <subdev/gpio.h>
+ static const enum dcb_gpio_func_name vidtag[] = { 0x04, 0x05, 0x06, 0x1a, 0x73 };
  static int nr_vidtag = sizeof(vidtag) / sizeof(vidtag[0]);
  
  int
   * DEALINGS IN THE SOFTWARE.
   */
  
 -#include "drmP.h"
 -#include "drm_crtc_helper.h"
 +#include <drm/drmP.h>
 +#include <drm/drm_crtc_helper.h>
  
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
+ #include "nouveau_reg.h"
+ #include "nouveau_bo.h"
+ #include "nouveau_gem.h"
  #include "nouveau_encoder.h"
  #include "nouveau_connector.h"
  #include "nouveau_crtc.h"
@@@ -1,6 -1,7 +1,7 @@@
 -#include "drmP.h"
 -#include "drm_mode.h"
 +#include <drm/drmP.h>
++#include <drm/drm_mode.h>
+ #include "nouveau_drm.h"
  #include "nouveau_reg.h"
- #include "nouveau_drv.h"
  #include "nouveau_crtc.h"
  #include "nouveau_hw.h"
  
   * DEALINGS IN THE SOFTWARE.
   */
  
 -#include "drmP.h"
 -#include "drm_crtc_helper.h"
 +#include <drm/drmP.h>
 +#include <drm/drm_crtc_helper.h>
  
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
  #include "nouveau_encoder.h"
  #include "nouveau_connector.h"
  #include "nouveau_crtc.h"
   * DEALINGS IN THE SOFTWARE.
   */
  
 -#include "drmP.h"
 -#include "drm_crtc_helper.h"
 +#include <drm/drmP.h>
 +#include <drm/drm_crtc_helper.h>
  
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
+ #include "nouveau_reg.h"
  #include "nouveau_encoder.h"
  #include "nouveau_connector.h"
  #include "nouveau_crtc.h"
  #include "nouveau_hw.h"
  #include "nvreg.h"
  
 -#include "i2c/sil164.h"
 +#include <drm/i2c/sil164.h>
  
+ #include <subdev/i2c.h>
  #define FP_TG_CONTROL_ON  (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |      \
                           NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |         \
                           NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS)
   * Author: Ben Skeggs
   */
  
 -#include "drmP.h"
 -#include "drm.h"
 -#include "drm_crtc_helper.h"
 +#include <drm/drmP.h>
 +#include <drm/drm_crtc_helper.h>
  
- #include "nouveau_drv.h"
- #include "nouveau_fb.h"
+ #include "nouveau_drm.h"
+ #include "nouveau_reg.h"
  #include "nouveau_hw.h"
  #include "nouveau_encoder.h"
  #include "nouveau_connector.h"
@@@ -22,8 -22,9 +22,9 @@@
   * Authors: Ben Skeggs
   */
  
 -#include "drmP.h"
 +#include <drm/drmP.h>
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
+ #include "nouveau_reg.h"
  #include "nouveau_hw.h"
  #include "nouveau_pm.h"
  
   *
   */
  
 -#include "drmP.h"
 +#include <drm/drmP.h>
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
+ #include "nouveau_reg.h"
  #include "nouveau_encoder.h"
  #include "nouveau_connector.h"
  #include "nouveau_crtc.h"
  #include "nouveau_hw.h"
 -#include "drm_crtc_helper.h"
 +#include <drm/drm_crtc_helper.h>
  
 -#include "i2c/ch7006.h"
 +#include <drm/i2c/ch7006.h>
  
+ #include <subdev/i2c.h>
  static struct i2c_board_info nv04_tv_encoder_info[] = {
        {
                I2C_BOARD_INFO("ch7006", 0x75),
   *
   */
  
 -#include "drmP.h"
 -#include "drm_crtc_helper.h"
 +#include <drm/drmP.h>
 +#include <drm/drm_crtc_helper.h>
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
+ #include "nouveau_reg.h"
  #include "nouveau_encoder.h"
  #include "nouveau_connector.h"
  #include "nouveau_crtc.h"
@@@ -24,9 -24,9 +24,9 @@@
   *
   */
  
 -#include "drmP.h"
 -#include "drm_crtc_helper.h"
 +#include <drm/drmP.h>
 +#include <drm/drm_crtc_helper.h>
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
  #include "nouveau_encoder.h"
  #include "nouveau_crtc.h"
  #include "nouveau_hw.h"
@@@ -22,8 -22,8 +22,8 @@@
   * Authors: Ben Skeggs
   */
  
 -#include "drmP.h"
 +#include <drm/drmP.h>
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
  #include "nouveau_bios.h"
  #include "nouveau_pm.h"
  #include "nouveau_hw.h"
   *
   */
  
 -#include "drmP.h"
 -#include "drm_mode.h"
 -#include "drm_crtc_helper.h"
 +#include <drm/drmP.h>
 +#include <drm/drm_crtc_helper.h>
  
- #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
  #include "nouveau_reg.h"
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
+ #include "nouveau_dma.h"
+ #include "nouveau_gem.h"
  #include "nouveau_hw.h"
  #include "nouveau_encoder.h"
  #include "nouveau_crtc.h"
   *
   */
  
 -#include "drmP.h"
 -#include "drm_mode.h"
 +#include <drm/drmP.h>
  
- #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
- #include "nouveau_reg.h"
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
+ #include "nouveau_dma.h"
  #include "nouveau_crtc.h"
  #include "nv50_display.h"
  
Simple merge
  #include "nouveau_crtc.h"
  #include "nouveau_encoder.h"
  #include "nouveau_connector.h"
- #include "nouveau_fb.h"
  #include "nouveau_fbcon.h"
- #include "nouveau_ramht.h"
- #include "nouveau_software.h"
 -#include "drm_crtc_helper.h"
 +#include <drm/drm_crtc_helper.h>
+ #include "nouveau_fence.h"
+ #include <core/gpuobj.h>
+ #include <subdev/timer.h>
  
- static void nv50_display_isr(struct drm_device *);
  static void nv50_display_bh(unsigned long);
  
  static inline int
   * Authors: Ben Skeggs
   */
  
 -#include "drmP.h"
 +#include <drm/drmP.h>
  
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
  #include "nouveau_dma.h"
- #include "nouveau_ramht.h"
  #include "nv50_display.h"
  
+ #include <core/gpuobj.h>
+ #include <subdev/timer.h>
+ #include <subdev/fb.h>
+ static u32
+ nv50_evo_rd32(struct nouveau_object *object, u32 addr)
+ {
+       void __iomem *iomem = object->oclass->ofuncs->rd08;
+       return ioread32_native(iomem + addr);
+ }
+ static void
+ nv50_evo_wr32(struct nouveau_object *object, u32 addr, u32 data)
+ {
+       void __iomem *iomem = object->oclass->ofuncs->rd08;
+       iowrite32_native(data, iomem + addr);
+ }
  static void
  nv50_evo_channel_del(struct nouveau_channel **pevo)
  {
@@@ -22,8 -22,8 +22,8 @@@
   * Authors: Ben Skeggs
   */
  
 -#include "drmP.h"
 +#include <drm/drmP.h>
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
  #include "nouveau_bios.h"
  #include "nouveau_hw.h"
  #include "nouveau_pm.h"
Simple merge
@@@ -22,8 -22,8 +22,8 @@@
   * Authors: Ben Skeggs
   */
  
 -#include "drmP.h"
 +#include <drm/drmP.h>
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
  #include "nouveau_bios.h"
  #include "nouveau_pm.h"
  
  
  #include <linux/dma-mapping.h>
  
 -#include "drmP.h"
 -#include "drm_crtc_helper.h"
 +#include <drm/drmP.h>
 +#include <drm/drm_crtc_helper.h>
  
- #include "nouveau_drv.h"
+ #include "nouveau_drm.h"
+ #include "nouveau_dma.h"
+ #include "nouveau_gem.h"
  #include "nouveau_connector.h"
  #include "nouveau_encoder.h"
  #include "nouveau_crtc.h"
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   * Authors: Dave Airlie
   *          Alex Deucher
   */
 -#include "drmP.h"
 -#include "drm_crtc_helper.h"
 -#include "radeon_drm.h"
 +#include <drm/drmP.h>
 +#include <drm/drm_crtc_helper.h>
 +#include <drm/radeon_drm.h>
  #include "radeon.h"
  #include "atom.h"
+ #include <linux/backlight.h>
  
  extern int atom_debug;
  
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  #include <linux/pci.h>
  #include <linux/acpi.h>
  #include <linux/slab.h>
+ #include <linux/power_supply.h>
  #include <acpi/acpi_drivers.h>
  #include <acpi/acpi_bus.h>
+ #include <acpi/video.h>
  
 -#include "drmP.h"
 -#include "drm.h"
 -#include "drm_sarea.h"
 -#include "drm_crtc_helper.h"
 +#include <drm/drmP.h>
 +#include <drm/drm_crtc_helper.h>
  #include "radeon.h"
+ #include "radeon_acpi.h"
+ #include "atom.h"
  
  #include <linux/vga_switcheroo.h>
  
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  #include <linux/module.h>
  #include <linux/slab.h>
  #include <linux/fb.h>
+ #include <linux/dma-buf.h>
  
 -#include "drmP.h"
 -#include "drm.h"
 -#include "drm_crtc.h"
 -#include "drm_crtc_helper.h"
 +#include <drm/drmP.h>
 +#include <drm/drm_crtc.h>
 +#include <drm/drm_crtc_helper.h>
  #include "udl_drv.h"
  
 -#include "drm_fb_helper.h"
 +#include <drm/drm_fb_helper.h>
  
  #define DL_DEFIO_WRITE_DELAY    5 /* fb_deferred_io.delay in jiffies */
  
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