ASoC: tegra-alt: add spdif driver
Songhee Baek [Sat, 7 Dec 2013 04:51:55 +0000 (20:51 -0800)]
This change is for adding spdif driver in tegra-alt ASoC.

Bug 1423733

Change-Id: Ic52b58ab9bd0e8cb82e7834a5d1d2f3f87550bf8
Signed-off-by: Songhee Baek <sbaek@nvidia.com>
Reviewed-on: http://git-master/r/339601
GVS: Gerrit_Virtual_Submit
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Gajanan Bhat <gbhat@nvidia.com>
Reviewed-by: Arun Shamanna Lakshmi <aruns@nvidia.com>

sound/soc/tegra-alt/Kconfig
sound/soc/tegra-alt/Makefile
sound/soc/tegra-alt/tegra30_apbif_alt.c
sound/soc/tegra-alt/tegra30_apbif_alt.h
sound/soc/tegra-alt/tegra30_spdif_alt.c [new file with mode: 0644]
sound/soc/tegra-alt/tegra30_spdif_alt.h [new file with mode: 0644]
sound/soc/tegra-alt/tegra30_xbar_alt.c

index 1fbc85f..190cb8a 100644 (file)
@@ -36,6 +36,12 @@ config SND_SOC_TEGRA30_I2S_ALT
        help
          Say Y or M if you want to add support for Tegra30 I2S module.
 
+config SND_SOC_TEGRA30_SPDIF_ALT
+       tristate "Tegra30 SPDIF driver"
+       depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_30_OR_LATER
+       help
+         Say Y or M if you want to add support for Tegra30 SPDIF module.
+
 config SND_SOC_TEGRA114_AMX_ALT
        tristate "Tegra114 AMX driver"
        depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_114_OR_LATER
@@ -59,6 +65,7 @@ config SND_SOC_TEGRA_VCM30T124_ALT
        select SND_SOC_TEGRA114_ADX_ALT
        select SND_SOC_AD193X
        select SND_SOC_WM8731
+       select SND_SOC_SPDIF
        help
          Say Y or M here if you want to add support for SoC audio on the
          TEGRA VCM30_T124 using wm8731 and ad1937 codecs.
index 52ef0ef..d8d4c83 100644 (file)
@@ -8,6 +8,7 @@ snd-soc-tegra-alt-utils-objs := tegra_asoc_utils_alt.o
 snd-soc-tegra30-alt-apbif-objs := tegra30_apbif_alt.o
 snd-soc-tegra30-alt-xbar-objs := tegra30_xbar_alt.o
 snd-soc-tegra30-alt-i2s-objs := tegra30_i2s_alt.o
+snd-soc-tegra30-alt-spdif-objs := tegra30_spdif_alt.o
 snd-soc-tegra114-alt-amx-objs := tegra114_amx_alt.o
 snd-soc-tegra114-alt-adx-objs := tegra114_adx_alt.o
 
@@ -16,6 +17,7 @@ obj-$(CONFIG_SND_SOC_TEGRA_ALT) += snd-soc-tegra-alt-utils.o
 obj-$(CONFIG_SND_SOC_TEGRA30_APBIF_ALT) += snd-soc-tegra30-alt-apbif.o
 obj-$(CONFIG_SND_SOC_TEGRA30_XBAR_ALT) += snd-soc-tegra30-alt-xbar.o
 obj-$(CONFIG_SND_SOC_TEGRA30_I2S_ALT) += snd-soc-tegra30-alt-i2s.o
+obj-$(CONFIG_SND_SOC_TEGRA30_SPDIF_ALT) += snd-soc-tegra30-alt-spdif.o
 obj-$(CONFIG_SND_SOC_TEGRA114_AMX_ALT) += snd-soc-tegra114-alt-amx.o
 obj-$(CONFIG_SND_SOC_TEGRA114_ADX_ALT) += snd-soc-tegra114-alt-adx.o
 
index 3dbd36a..be6f68c 100644 (file)
@@ -463,6 +463,7 @@ struct of_dev_auxdata tegra30_apbif_auxdata[] = {
        OF_DEV_AUXDATA("nvidia,tegra124-i2s", 0x70301200, "tegra30-i2s.2", NULL),
        OF_DEV_AUXDATA("nvidia,tegra124-i2s", 0x70301300, "tegra30-i2s.3", NULL),
        OF_DEV_AUXDATA("nvidia,tegra124-i2s", 0x70301400, "tegra30-i2s.4", NULL),
+       OF_DEV_AUXDATA("nvidia,tegra124-spdif", 0x70306000, "tegra30-spdif", NULL),
        OF_DEV_AUXDATA("nvidia,tegra124-amx", 0x70303000, "tegra124-amx.0", NULL),
        OF_DEV_AUXDATA("nvidia,tegra124-amx", 0x70303100, "tegra124-amx.1", NULL),
        OF_DEV_AUXDATA("nvidia,tegra124-adx", 0x70303800, "tegra124-adx.0", NULL),
@@ -679,7 +680,7 @@ static int tegra30_apbif_probe(struct platform_device *pdev)
        ret = snd_soc_register_component(&pdev->dev,
                                        &tegra30_apbif_dai_driver,
                                        tegra30_apbif_dais,
-                                       ARRAY_SIZE(tegra30_apbif_dais));
+                                       apbif->soc_data->num_ch);
        if (ret) {
                dev_err(&pdev->dev, "Could not register DAIs %d: %d\n",
                        i, ret);
index 13b1890..30924f5 100644 (file)
@@ -313,8 +313,6 @@ struct tegra30_apbif {
        struct clk *clk;
        /* regmap for APBIF */
        struct regmap *regmap[2];
-       /* regmap for APBIF2 */
-       struct regmap *regmap1;
        struct tegra_alt_pcm_dma_params *capture_dma_data;
        struct tegra_alt_pcm_dma_params *playback_dma_data;
        const struct tegra30_apbif_soc_data *soc_data;
diff --git a/sound/soc/tegra-alt/tegra30_spdif_alt.c b/sound/soc/tegra-alt/tegra30_spdif_alt.c
new file mode 100644 (file)
index 0000000..76cf8c9
--- /dev/null
@@ -0,0 +1,485 @@
+/*
+ * tegra30_spdif_alt.c - Tegra30 SPDIF driver
+ *
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/of_device.h>
+
+#include "tegra30_xbar_alt.h"
+#include "tegra30_spdif_alt.h"
+
+#define DRV_NAME "tegra30-spdif"
+
+static int tegra30_spdif_runtime_suspend(struct device *dev)
+{
+       struct tegra30_spdif *spdif = dev_get_drvdata(dev);
+
+       regcache_cache_only(spdif->regmap, true);
+
+       clk_disable_unprepare(spdif->clk_spdif_out);
+       clk_disable_unprepare(spdif->clk_spdif_in);
+
+       return 0;
+}
+
+static int tegra30_spdif_runtime_resume(struct device *dev)
+{
+       struct tegra30_spdif *spdif = dev_get_drvdata(dev);
+       int ret;
+
+       ret = clk_prepare_enable(spdif->clk_spdif_out);
+       if (ret) {
+               dev_err(dev, "spdif_out_clk_enable failed: %d\n", ret);
+               return ret;
+       }
+
+       ret = clk_prepare_enable(spdif->clk_spdif_in);
+       if (ret) {
+               dev_err(dev, "spdif_in_clk_enable failed: %d\n", ret);
+               return ret;
+       }
+
+       regcache_cache_only(spdif->regmap, false);
+
+       return 0;
+}
+
+static int tegra30_spdif_set_dai_sysclk(struct snd_soc_dai *dai,
+               int clk_id, unsigned int freq, int dir)
+{
+       struct device *dev = dai->dev;
+       struct tegra30_spdif *spdif = snd_soc_dai_get_drvdata(dai);
+       int spdif_out_clock_rate, spdif_in_clock_rate;
+       int ret;
+
+       switch (freq) {
+       case 32000:
+               spdif_out_clock_rate = 4096000;
+               spdif_in_clock_rate = 48000000;
+               break;
+       case 44100:
+               spdif_out_clock_rate = 5644800;
+               spdif_in_clock_rate = 48000000;
+               break;
+       case 48000:
+               spdif_out_clock_rate = 6144000;
+               spdif_in_clock_rate = 48000000;
+               break;
+       case 88200:
+               spdif_out_clock_rate = 11289600;
+               spdif_in_clock_rate = 72000000;
+               break;
+       case 96000:
+               spdif_out_clock_rate = 12288000;
+               spdif_in_clock_rate = 72000000;
+               break;
+       case 176400:
+               spdif_out_clock_rate = 22579200;
+               spdif_in_clock_rate = 108000000;
+               break;
+       case 192000:
+               spdif_out_clock_rate = 24576000;
+               spdif_in_clock_rate = 108000000;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       if (dir == SND_SOC_CLOCK_OUT) {
+               ret = clk_set_rate(spdif->clk_spdif_out, spdif_out_clock_rate);
+               if (ret) {
+                       dev_err(dev, "Can't set SPDIF Out clock rate: %d\n",
+                               ret);
+                       return ret;
+               }
+       } else {
+               ret = clk_set_rate(spdif->clk_spdif_in, spdif_in_clock_rate);
+               if (ret) {
+                       dev_err(dev, "Can't set SPDIF In clock rate: %d\n",
+                               ret);
+                       return ret;
+               }
+       }
+
+       return 0;
+}
+
+
+static int tegra30_spdif_hw_params(struct snd_pcm_substream *substream,
+                                struct snd_pcm_hw_params *params,
+                                struct snd_soc_dai *dai)
+{
+       struct device *dev = dai->dev;
+       struct tegra30_spdif *spdif = snd_soc_dai_get_drvdata(dai);
+       int channels, audio_bits, bit_mode;
+       struct tegra30_xbar_cif_conf cif_conf;
+
+       channels = params_channels(params);
+
+       if (channels < 2) {
+               dev_err(dev, "Doesn't support %d channels\n", channels);
+               return -EINVAL;
+       }
+
+       switch (params_format(params)) {
+       case SNDRV_PCM_FORMAT_S16_LE:
+               audio_bits = TEGRA30_AUDIOCIF_BITS_16;
+               bit_mode = TEGRA30_SPDIF_BIT_MODE16;
+               break;
+       case SNDRV_PCM_FORMAT_S32_LE:
+               audio_bits = TEGRA30_AUDIOCIF_BITS_32;
+               bit_mode = TEGRA30_SPDIF_BIT_MODERAW;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       cif_conf.threshold = 0;
+       cif_conf.audio_channels = channels;
+       cif_conf.client_channels = channels;
+       cif_conf.audio_bits = audio_bits;
+       cif_conf.client_bits = audio_bits;
+       cif_conf.expand = 0;
+       cif_conf.stereo_conv = 0;
+       cif_conf.replicate = 0;
+       cif_conf.direction = 0;
+       cif_conf.truncate = 0;
+       cif_conf.mono_conv = 0;
+
+       regmap_update_bits(spdif->regmap, TEGRA30_SPDIF_CTRL,
+                               TEGRA30_SPDIF_CTRL_BIT_MODE_MASK,
+                               bit_mode);
+
+       /* As a CODEC DAI, CAPTURE is transmit */
+       if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+               cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX;
+               spdif->soc_data->set_audio_cif(spdif->regmap,
+                                       TEGRA30_SPDIF_CIF_TXD_CTRL,
+                                       &cif_conf);
+       } else {
+               cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX;
+               spdif->soc_data->set_audio_cif(spdif->regmap,
+                                       TEGRA30_SPDIF_CIF_RXD_CTRL,
+                                       &cif_conf);
+       }
+
+       return 0;
+}
+
+static int tegra30_spdif_codec_probe(struct snd_soc_codec *codec)
+{
+       struct tegra30_spdif *spdif = snd_soc_codec_get_drvdata(codec);
+       int ret;
+
+       codec->control_data = spdif->regmap;
+       ret = snd_soc_codec_set_cache_io(codec, 32, 32, SND_SOC_REGMAP);
+       if (ret != 0) {
+               dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+               return ret;
+       }
+
+       return 0;
+}
+
+static struct snd_soc_dai_ops tegra30_spdif_dai_ops = {
+       .hw_params      = tegra30_spdif_hw_params,
+       .set_sysclk     = tegra30_spdif_set_dai_sysclk,
+};
+
+static struct snd_soc_dai_driver tegra30_spdif_dais[] = {
+       {
+               .name = "CIF",
+               .playback = {
+                       .stream_name = "CIF Receive",
+                       .channels_min = 1,
+                       .channels_max = 16,
+                       .rates = SNDRV_PCM_RATE_8000_96000,
+                       .formats = SNDRV_PCM_FMTBIT_S16_LE,
+               },
+               .capture = {
+                       .stream_name = "CIF Transmit",
+                       .channels_min = 1,
+                       .channels_max = 16,
+                       .rates = SNDRV_PCM_RATE_8000_96000,
+                       .formats = SNDRV_PCM_FMTBIT_S16_LE,
+               },
+       },
+       {
+               .name = "DAP",
+               .playback = {
+                       .stream_name = "DAP Receive",
+                       .channels_min = 1,
+                       .channels_max = 16,
+                       .rates = SNDRV_PCM_RATE_8000_96000,
+                       .formats = SNDRV_PCM_FMTBIT_S16_LE,
+               },
+               .capture = {
+                       .stream_name = "DAP Transmit",
+                       .channels_min = 1,
+                       .channels_max = 16,
+                       .rates = SNDRV_PCM_RATE_8000_96000,
+                       .formats = SNDRV_PCM_FMTBIT_S16_LE,
+               },
+               .ops = &tegra30_spdif_dai_ops,
+       }
+};
+
+static const struct snd_soc_dapm_widget tegra30_spdif_widgets[] = {
+       SND_SOC_DAPM_AIF_IN("CIF RX", NULL, 0, SND_SOC_NOPM, 0, 0),
+       SND_SOC_DAPM_AIF_OUT("CIF TX", NULL, 0, SND_SOC_NOPM, 0, 0),
+       SND_SOC_DAPM_AIF_IN("DAP RX", NULL, 0, TEGRA30_SPDIF_CTRL, 29, 0),
+       SND_SOC_DAPM_AIF_OUT("DAP TX", NULL, 0, TEGRA30_SPDIF_CTRL, 28, 0),
+};
+
+static const struct snd_soc_dapm_route tegra30_spdif_routes[] = {
+       { "CIF RX",       NULL, "CIF Receive"},
+       { "DAP TX",       NULL, "CIF RX"},
+       { "DAP Transmit", NULL, "DAP TX"},
+
+       { "DAP RX",       NULL, "DAP Receive"},
+       { "CIF TX",       NULL, "DAP RX"},
+       { "CIF Transmit", NULL, "CIF TX"},
+};
+
+static struct snd_soc_codec_driver tegra30_spdif_codec = {
+       .probe = tegra30_spdif_codec_probe,
+       .dapm_widgets = tegra30_spdif_widgets,
+       .num_dapm_widgets = ARRAY_SIZE(tegra30_spdif_widgets),
+       .dapm_routes = tegra30_spdif_routes,
+       .num_dapm_routes = ARRAY_SIZE(tegra30_spdif_routes),
+};
+
+static bool tegra30_spdif_wr_rd_reg(struct device *dev, unsigned int reg)
+{
+       switch (reg) {
+       case TEGRA30_SPDIF_CTRL:
+       case TEGRA30_SPDIF_STROBE_CTRL:
+       case TEGRA30_SPDIF_CIF_TXD_CTRL:
+       case TEGRA30_SPDIF_CIF_RXD_CTRL:
+       case TEGRA30_SPDIF_CIF_TXU_CTRL:
+       case TEGRA30_SPDIF_CIF_RXU_CTRL:
+       case TEGRA30_SPDIF_CH_STA_RX_A:
+       case TEGRA30_SPDIF_CH_STA_RX_B:
+       case TEGRA30_SPDIF_CH_STA_RX_C:
+       case TEGRA30_SPDIF_CH_STA_RX_D:
+       case TEGRA30_SPDIF_CH_STA_RX_E:
+       case TEGRA30_SPDIF_CH_STA_RX_F:
+       case TEGRA30_SPDIF_CH_STA_TX_A:
+       case TEGRA30_SPDIF_CH_STA_TX_B:
+       case TEGRA30_SPDIF_CH_STA_TX_C:
+       case TEGRA30_SPDIF_CH_STA_TX_D:
+       case TEGRA30_SPDIF_CH_STA_TX_E:
+       case TEGRA30_SPDIF_CH_STA_TX_F:
+       case TEGRA30_SPDIF_FLOWCTL_CTRL:
+       case TEGRA30_SPDIF_TX_STEP:
+       case TEGRA30_SPDIF_FLOW_STATUS:
+       case TEGRA30_SPDIF_FLOW_TOTAL:
+       case TEGRA30_SPDIF_FLOW_OVER:
+       case TEGRA30_SPDIF_FLOW_UNDER:
+       case TEGRA30_SPDIF_LCOEF_1_4_0:
+       case TEGRA30_SPDIF_LCOEF_1_4_1:
+       case TEGRA30_SPDIF_LCOEF_1_4_2:
+       case TEGRA30_SPDIF_LCOEF_1_4_3:
+       case TEGRA30_SPDIF_LCOEF_1_4_4:
+       case TEGRA30_SPDIF_LCOEF_1_4_5:
+       case TEGRA30_SPDIF_LCOEF_2_4_0:
+       case TEGRA30_SPDIF_LCOEF_2_4_1:
+       case TEGRA30_SPDIF_LCOEF_2_4_2:
+               return true;
+       default:
+               return false;
+       };
+}
+
+static const struct regmap_config tegra30_spdif_regmap_config = {
+       .reg_bits = 32,
+       .reg_stride = 4,
+       .val_bits = 32,
+       .max_register = TEGRA30_SPDIF_LCOEF_2_4_2,
+       .writeable_reg = tegra30_spdif_wr_rd_reg,
+       .readable_reg = tegra30_spdif_wr_rd_reg,
+       .cache_type = REGCACHE_RBTREE,
+};
+
+static const struct tegra30_spdif_soc_data soc_data_tegra30 = {
+       .set_audio_cif = tegra30_xbar_set_cif,
+};
+
+static const struct tegra30_spdif_soc_data soc_data_tegra124 = {
+       .set_audio_cif = tegra124_xbar_set_cif,
+};
+
+static const struct of_device_id tegra30_spdif_of_match[] = {
+       { .compatible = "nvidia,tegra30-spdif", .data = &soc_data_tegra30 },
+       { .compatible = "nvidia,tegra124-spdif", .data = &soc_data_tegra124 },
+       {},
+};
+
+static int tegra30_spdif_platform_probe(struct platform_device *pdev)
+{
+       struct tegra30_spdif *spdif;
+       struct resource *mem, *memregion;
+       void __iomem *regs;
+       const struct of_device_id *match;
+       struct tegra30_spdif_soc_data *soc_data;
+       int ret;
+
+       match = of_match_device(tegra30_spdif_of_match, &pdev->dev);
+       if (!match) {
+               dev_err(&pdev->dev, "Error: No device match found\n");
+               ret = -ENODEV;
+               goto err;
+       }
+       soc_data = (struct tegra30_spdif_soc_data *)match->data;
+
+       spdif = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_spdif),
+                               GFP_KERNEL);
+       if (!spdif) {
+               dev_err(&pdev->dev, "Can't allocate tegra30_spdif\n");
+               ret = -ENOMEM;
+               goto err;
+       }
+       dev_set_drvdata(&pdev->dev, spdif);
+
+       spdif->soc_data = soc_data;
+
+       spdif->clk_spdif_out = devm_clk_get(&pdev->dev, "spdif_out");
+       if (IS_ERR(spdif->clk_spdif_out)) {
+               dev_err(&pdev->dev, "Can't retrieve spdif clock\n");
+               ret = PTR_ERR(spdif->clk_spdif_out);
+               goto err;
+       }
+
+       spdif->clk_spdif_in = devm_clk_get(&pdev->dev, "spdif_in");
+       if (IS_ERR(spdif->clk_spdif_in)) {
+               dev_err(&pdev->dev, "Can't retrieve spdif clock\n");
+               ret = PTR_ERR(spdif->clk_spdif_in);
+               goto err_spdif_out_clk_put;
+       }
+
+       mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       if (!mem) {
+               dev_err(&pdev->dev, "No memory resource\n");
+               ret = -ENODEV;
+               goto err_spdif_in_clk_put;
+       }
+
+       memregion = devm_request_mem_region(&pdev->dev, mem->start,
+                                           resource_size(mem), DRV_NAME);
+       if (!memregion) {
+               dev_err(&pdev->dev, "Memory region already claimed\n");
+               ret = -EBUSY;
+               goto err_spdif_in_clk_put;
+       }
+
+       regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
+       if (!regs) {
+               dev_err(&pdev->dev, "ioremap failed\n");
+               ret = -ENOMEM;
+               goto err_spdif_in_clk_put;
+       }
+
+       spdif->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
+                                           &tegra30_spdif_regmap_config);
+       if (IS_ERR(spdif->regmap)) {
+               dev_err(&pdev->dev, "regmap init failed\n");
+               ret = PTR_ERR(spdif->regmap);
+               goto err_spdif_in_clk_put;
+       }
+       regcache_cache_only(spdif->regmap, true);
+
+       pm_runtime_enable(&pdev->dev);
+       if (!pm_runtime_enabled(&pdev->dev)) {
+               ret = tegra30_spdif_runtime_resume(&pdev->dev);
+               if (ret)
+                       goto err_pm_disable;
+       }
+
+       ret = snd_soc_register_codec(&pdev->dev, &tegra30_spdif_codec,
+                                    tegra30_spdif_dais,
+                                    ARRAY_SIZE(tegra30_spdif_dais));
+       if (ret != 0) {
+               dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
+               goto err_suspend;
+       }
+
+       return 0;
+
+err_suspend:
+       if (!pm_runtime_status_suspended(&pdev->dev))
+               tegra30_spdif_runtime_suspend(&pdev->dev);
+err_pm_disable:
+       pm_runtime_disable(&pdev->dev);
+err_spdif_in_clk_put:
+       devm_clk_put(&pdev->dev, spdif->clk_spdif_in);
+err_spdif_out_clk_put:
+       devm_clk_put(&pdev->dev, spdif->clk_spdif_out);
+err:
+       return ret;
+}
+
+static int tegra30_spdif_platform_remove(struct platform_device *pdev)
+{
+       struct tegra30_spdif *spdif = dev_get_drvdata(&pdev->dev);
+
+       snd_soc_unregister_codec(&pdev->dev);
+
+       pm_runtime_disable(&pdev->dev);
+       if (!pm_runtime_status_suspended(&pdev->dev))
+               tegra30_spdif_runtime_suspend(&pdev->dev);
+
+       devm_clk_put(&pdev->dev, spdif->clk_spdif_out);
+       devm_clk_put(&pdev->dev, spdif->clk_spdif_in);
+
+       return 0;
+}
+
+static const struct dev_pm_ops tegra30_spdif_pm_ops = {
+       SET_RUNTIME_PM_OPS(tegra30_spdif_runtime_suspend,
+                          tegra30_spdif_runtime_resume, NULL)
+};
+
+static struct platform_driver tegra30_spdif_driver = {
+       .driver = {
+               .name = DRV_NAME,
+               .owner = THIS_MODULE,
+               .of_match_table = tegra30_spdif_of_match,
+               .pm = &tegra30_spdif_pm_ops,
+       },
+       .probe = tegra30_spdif_platform_probe,
+       .remove = tegra30_spdif_platform_remove,
+};
+module_platform_driver(tegra30_spdif_driver);
+
+MODULE_AUTHOR("Songhee Baek <sbaek@nvidia.com>");
+MODULE_AUTHOR("Arun Shamanna Lakshmi <aruns@nvidia.com>");
+MODULE_DESCRIPTION("Tegra30 SPDIF ASoC driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRV_NAME);
+MODULE_DEVICE_TABLE(of, tegra30_spdif_of_match);
diff --git a/sound/soc/tegra-alt/tegra30_spdif_alt.h b/sound/soc/tegra-alt/tegra30_spdif_alt.h
new file mode 100644 (file)
index 0000000..000239a
--- /dev/null
@@ -0,0 +1,260 @@
+/*
+ * tegra30_spdif.h - Definitions for Tegra30 SPDIF driver
+ *
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __TEGRA30_SPDIF_ALT_H__
+#define __TEGRA30_SPDIF_ALT_H__
+
+/* Register offsets from TEGRA_SPDIF_BASE */
+
+#define TEGRA30_SPDIF_CTRL                     0x0
+#define TEGRA30_SPDIF_STROBE_CTRL              0x4
+#define TEGRA30_SPDIF_CIF_TXD_CTRL             0x08
+#define TEGRA30_SPDIF_CIF_RXD_CTRL             0x0C
+#define TEGRA30_SPDIF_CIF_TXU_CTRL             0x10
+#define TEGRA30_SPDIF_CIF_RXU_CTRL             0x14
+#define TEGRA30_SPDIF_CH_STA_RX_A              0x18
+#define TEGRA30_SPDIF_CH_STA_RX_B              0x1C
+#define TEGRA30_SPDIF_CH_STA_RX_C              0x20
+#define TEGRA30_SPDIF_CH_STA_RX_D              0x24
+#define TEGRA30_SPDIF_CH_STA_RX_E              0x28
+#define TEGRA30_SPDIF_CH_STA_RX_F              0x2C
+#define TEGRA30_SPDIF_CH_STA_TX_A              0x30
+#define TEGRA30_SPDIF_CH_STA_TX_B              0x34
+#define TEGRA30_SPDIF_CH_STA_TX_C              0x38
+#define TEGRA30_SPDIF_CH_STA_TX_D              0x3C
+#define TEGRA30_SPDIF_CH_STA_TX_E              0x40
+#define TEGRA30_SPDIF_CH_STA_TX_F              0x44
+#define TEGRA30_SPDIF_FLOWCTL_CTRL             0x70
+#define TEGRA30_SPDIF_TX_STEP                  0x74
+#define TEGRA30_SPDIF_FLOW_STATUS              0x78
+#define TEGRA30_SPDIF_FLOW_TOTAL               0x7c
+#define TEGRA30_SPDIF_FLOW_OVER                        0x80
+#define TEGRA30_SPDIF_FLOW_UNDER               0x84
+#define TEGRA30_SPDIF_LCOEF_1_4_0              0x88
+#define TEGRA30_SPDIF_LCOEF_1_4_1              0x8c
+#define TEGRA30_SPDIF_LCOEF_1_4_2              0x90
+#define TEGRA30_SPDIF_LCOEF_1_4_3              0x94
+#define TEGRA30_SPDIF_LCOEF_1_4_4              0x98
+#define TEGRA30_SPDIF_LCOEF_1_4_5              0x9c
+#define TEGRA30_SPDIF_LCOEF_2_4_0              0xa0
+#define TEGRA30_SPDIF_LCOEF_2_4_1              0xa4
+#define TEGRA30_SPDIF_LCOEF_2_4_2              0xa8
+
+/* Fields in TEGRA30_SPDIF_CTRL */
+#define TEGRA30_SPDIF_CTRL_FLOWCTL_EN_ENABLE   (1<<31)
+#define TEGRA30_SPDIF_CTRL_CAP_LC_LEFT_CH      (1<<30)
+#define TEGRA30_SPDIF_CTRL_RX_EN_ENABLE                (1<<29)
+#define TEGRA30_SPDIF_CTRL_TX_EN_ENABLE                (1<<28)
+#define TEGRA30_SPDIF_CTRL_TC_EN_ENABLE                (1<<27)
+#define TEGRA30_SPDIF_CTRL_TU_EN_ENABLE                (1<<26)
+#define TEGRA30_SPDIF_CTRL_IE_P_RSVD_ENABLE    (1<<23)
+#define TEGRA30_SPDIF_CTRL_IE_B_RSVD_ENABLE    (1<<22)
+#define TEGRA30_SPDIF_CTRL_IE_C_RSVD_ENABLE    (1<<21)
+#define TEGRA30_SPDIF_CTRL_IE_U_RSVD_ENABLE    (1<<20)
+#define TEGRA30_SPDIF_CTRL_LBK_EN_ENABLE       (1<<15)
+#define TEGRA30_SPDIF_CTRL_PACK_ENABLE         (1<<14)
+
+#define TEGRA30_SPDIF_BIT_MODE16               0
+#define TEGRA30_SPDIF_BIT_MODE20               1
+#define TEGRA30_SPDIF_BIT_MODE24               2
+#define TEGRA30_SPDIF_BIT_MODERAW              3
+
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT      12
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_MASK       (3                         << TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT)
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_16BIT      (TEGRA30_SPDIF_BIT_MODE16  << TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT)
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_20BIT      (TEGRA30_SPDIF_BIT_MODE20  << TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT)
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_24BIT      (TEGRA30_SPDIF_BIT_MODE24  << TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT)
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_RAW                (TEGRA30_SPDIF_BIT_MODERAW << TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT)
+
+#define TEGRA30_SPDIF_CTRL_CG_EN_ENABLE                (1<<11)
+
+#define TEGRA30_SPDIF_CTRL_OBS_SEL_SHIFT       8
+#define TEGRA30_SPDIF_CTRL_OBS_SEL_NASK                (0x7 << TEGRA30_SPDIF_CTRL_OBS_SEL_SHIFT)
+
+#define TEGRA30_SPDIF_CTRL_SOFT_RESET_ENABLE   (1<<7)
+
+/* Fields in TEGRA30_SPDIF_STROBE_CTRL */
+#define TEGRA30_SPDIF_STROBE_CTRL_PERIOD_SHIFT         16
+#define TEGRA30_SPDIF_STROBE_CTRL_PERIOD_MASK          (0xff << TEGRA30_SPDIF_STROBE_CTRL_PERIOD_SHIFT)
+
+#define TEGRA30_SPDIF_STROBE_CTRL_STROBE               (1<<15)
+
+#define TEGRA30_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT   8
+#define TEGRA30_SPDIF_STROBE_CTRL_DATA_STROBES_MASK    (0x1f << TEGRA30_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT)
+
+#define TEGRA30_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT   0
+#define TEGRA30_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK    (0x3f << TEGRA30_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT)
+
+/*
+ * The 6-word receive channel data page buffer holds a block (192 frames) of
+ * channel status information. The order of receive is from LSB to MSB
+ * bit, and from CH_STA_RX_A to CH_STA_RX_F then back to CH_STA_RX_A.
+ */
+
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_A */
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_22050                     0x4
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_24000                     0x6
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_32000                     0x3
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_44100                     0x0
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_48000                     0x2
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_88200                     0x8
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_96000                     0xA
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_176400                    0xC
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_192000                    0xE
+
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT              24
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_MASK               \
+               (0xF                                 << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_22050      \
+               (TEGRA30_SPDIF_CH_STA_TX_A_SF_22050  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_24000              \
+               (TEGRA30_SPDIF_CH_STA_TX_A_SF_24000  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_32000              \
+               (TEGRA30_SPDIF_CH_STA_TX_A_SF_32000  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_44100              \
+               (TEGRA30_SPDIF_CH_STA_TX_A_SF_44100  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_48000              \
+               (TEGRA30_SPDIF_CH_STA_TX_A_SF_48000  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_88200              \
+               (TEGRA30_SPDIF_CH_STA_TX_A_SF_88200  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_96000              \
+               (TEGRA30_SPDIF_CH_STA_TX_A_SF_96000  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_176400             \
+               (TEGRA30_SPDIF_CH_STA_TX_A_SF_176400 << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_192000             \
+               (TEGRA30_SPDIF_CH_STA_TX_A_SF_192000 << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_B */
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_8000                      0x6
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_11025                     0xA
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_12000                     0x2
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_16000                     0x8
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_22050                     0xB
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_24000                     0x9
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_32000                     0xC
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_44100                     0xF
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_48000                     0xD
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_88200                     0x7
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_96000                     0x5
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_176400                    0x3
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_192000                    0x1
+
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT         4
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_MASK          \
+               (0xF                                 << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_8000          \
+               (TEGRA30_SPDIF_CH_STA_TX_B_SF_8000   << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_11025         \
+               (TEGRA30_SPDIF_CH_STA_TX_B_SF_11025  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_12000         \
+               (TEGRA30_SPDIF_CH_STA_TX_B_SF_12000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_16000         \
+               (TEGRA30_SPDIF_CH_STA_TX_B_SF_16000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_22050         \
+               (TEGRA30_SPDIF_CH_STA_TX_B_SF_22025  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_24000         \
+               (TEGRA30_SPDIF_CH_STA_TX_B_SF_24000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_32000         \
+               (TEGRA30_SPDIF_CH_STA_TX_B_SF_32000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_44100         \
+               (TEGRA30_SPDIF_CH_STA_TX_B_SF_44100  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_48000         \
+               (TEGRA30_SPDIF_CH_STA_TX_B_SF_48000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_88200         \
+               (TEGRA30_SPDIF_CH_STA_TX_B_SF_88200  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_96000         \
+               (TEGRA30_SPDIF_CH_STA_TX_B_SF_96000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_176400                \
+               (TEGRA30_SPDIF_CH_STA_TX_B_SF_176400 << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_192000                \
+               (TEGRA30_SPDIF_CH_STA_TX_B_SF_192000 << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_C */
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_D */
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_E */
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_F */
+
+/* Fields in TEGRA30_SPDIF_FLOWCTL_CTRL */
+#define TEGRA30_SPDIF_FLOWCTL_CTRL_FILTER_QUAD         (1<<31)
+
+/* Fields in TEGRA30_SPDIF_TX_STEP */
+#define TEGRA30_SPDIF_TX_STEP_STEP_SIZE_SHIFT          0
+#define TEGRA30_SPDIF_TX_STEP_STEP_SIZE_MASK           (0xffff << TEGRA30_SPDIF_TX_STEP_STEP_SIZE_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_FLOW_STATUS */
+#define TEGRA30_SPDIF_FLOW_STATUS_COUNTER_EN_ENABLE    (1<<1)
+#define TEGRA30_SPDIF_FLOW_STATUS_MONITOR_CLR_CLEAR    (1<<2)
+#define TEGRA30_SPDIF_FLOW_STATUS_COUNTER_CLR_CLEAR    (1<<3)
+#define TEGRA30_SPDIF_FLOW_STATUS_MONITOR_INT_EN_ENABLE        (1<<4)
+#define TEGRA30_SPDIF_FLOW_STATUS_FLOW_OVERFLOW_OVER   (1<<30)
+#define TEGRA30_SPDIF_FLOW_STATUS_FLOW_UNDERFLOW_UNDER (1<<31)
+
+/* Fields in TEGRA30_SPDIF_FLOW_TOTAL */
+/* Fields in TEGRA30_SPDIF_FLOW_OVER */
+/* Fields in TEGRA30_SPDIF_FLOW_UNDER */
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_0 */
+#define TEGRA30_SPDIF_LCOEF_1_4_0_COEF_SHIFT           0
+#define TEGRA30_SPDIF_LCOEF_1_4_0_COEF_MASK            (0xffff << TEGRA30_TEGRA30_SPDIF_LCOEF_1_4_0_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_1 */
+#define TEGRA30_SPDIF_LCOEF_1_4_1_COEF_SHIFT           0
+#define TEGRA30_SPDIF_LCOEF_1_4_1_COEF_MASK            (0xffff << TEGRA30_SPDIF_LCOEF_1_4_1_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_2 */
+#define TEGRA30_SPDIF_LCOEF_1_4_2_COEF_SHIFT           0
+#define TEGRA30_SPDIF_LCOEF_1_4_2_COEF_MASK            (0xffff << TEGRA30_SPDIF_LCOEF_1_4_2_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_3 */
+#define TEGRA30_SPDIF_LCOEF_1_4_3_COEF_SHIFT           0
+#define TEGRA30_SPDIF_LCOEF_1_4_3_COEF_MASK            (0xffff << TEGRA30_SPDIF_LCOEF_1_4_3_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_4 */
+#define TEGRA30_SPDIF_LCOEF_1_4_4_COEF_SHIFT           0
+#define TEGRA30_SPDIF_LCOEF_1_4_4_COEF_MASK            (0xffff << TEGRA30_SPDIF_LCOEF_1_4_4_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_5 */
+#define TEGRA30_SPDIF_LCOEF_1_4_5_COEF_SHIFT           0
+#define TEGRA30_SPDIF_LCOEF_1_4_5_COEF_MASK            (0xffff << TEGRA30_SPDIF_LCOEF_1_4_5_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_2_4_0 */
+#define TEGRA30_SPDIF_LCOEF_2_4_0_COEF_SHIFT           0
+#define TEGRA30_SPDIF_LCOEF_2_4_0_COEF_MASK            (0xffff << TEGRA30_SPDIF_LCOEF_2_4_0_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_2_4_1 */
+#define TEGRA30_SPDIF_LCOEF_2_4_1_COEF_SHIFT           0
+#define TEGRA30_SPDIF_LCOEF_2_4_1_COEF_MASK            (0xffff << TEGRA30_SPDIF_LCOEF_2_4_1_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_2_4_2 */
+#define TEGRA30_SPDIF_LCOEF_2_4_2_COEF_SHIFT           0
+#define TEGRA30_SPDIF_LCOEF_2_4_2_COEF_MASK            (0xffff << SPDIF_LCOEF_2_4_2_COEF_SHIFT)
+
+struct tegra30_spdif_soc_data {
+       void (*set_audio_cif)(struct regmap *map,
+                       unsigned int reg,
+                       struct tegra30_xbar_cif_conf *conf);
+};
+
+struct tegra30_spdif {
+       struct clk *clk_spdif_out;
+       struct clk *clk_spdif_in;
+       struct regmap *regmap;
+       const struct tegra30_spdif_soc_data *soc_data;
+};
+
+#endif
index 96054fc..f51ba4d 100644 (file)
@@ -120,7 +120,8 @@ static struct snd_soc_dai_driver tegra30_xbar_dais[] = {
        DAI(I2S2),
        DAI(I2S3),
        DAI(I2S4),
-       /* index 0..8 above are used on Tegra30 */
+       DAI(SPDIF),
+       /* index 0..9 above are used on Tegra30 */
        DAI(APBIF4),
        DAI(APBIF5),
        DAI(APBIF6),
@@ -137,7 +138,7 @@ static struct snd_soc_dai_driver tegra30_xbar_dais[] = {
        DAI(ADX0-2),
        DAI(ADX0-3),
        DAI(ADX0),
-       /* index 0..24 above are used on Tegra114 */
+       /* index 0..25 above are used on Tegra114 */
        DAI(AMX1),
        DAI(AMX1-0),
        DAI(AMX1-1),
@@ -148,7 +149,7 @@ static struct snd_soc_dai_driver tegra30_xbar_dais[] = {
        DAI(ADX1-2),
        DAI(ADX1-3),
        DAI(ADX1),
-       /* index 0..34 above are used on Tegra124 */
+       /* index 0..35 above are used on Tegra124 */
 };
 
 static const char * const tegra30_xbar_mux_texts[] = {
@@ -162,7 +163,8 @@ static const char * const tegra30_xbar_mux_texts[] = {
        "I2S2",
        "I2S3",
        "I2S4",
-       /* index 0..9 above are used on Tegra30 */
+       "SPDIF",
+       /* index 0..10 above are used on Tegra30 */
        "APBIF4",
        "APBIF5",
        "APBIF6",
@@ -174,13 +176,13 @@ static const char * const tegra30_xbar_mux_texts[] = {
        "ADX0-1",
        "ADX0-2",
        "ADX0-3",
-       /* index 0..20 above are used on Tegra114 */
+       /* index 0..21 above are used on Tegra114 */
        "AMX1",
        "ADX1-0",
        "ADX1-1",
        "ADX1-2",
        "ADX1-3",
-       /* index 0..25 above are used on Tegra124 */
+       /* index 0..26 above are used on Tegra124 */
 };
 
 static const int tegra30_xbar_mux_values[] = {
@@ -195,7 +197,8 @@ static const int tegra30_xbar_mux_values[] = {
        BIT(6),         0,
        BIT(7),         0,
        BIT(8),         0,
-       /* index 0..9 above are used on Tegra30 */
+       BIT(12),        0,
+       /* index 0..10 above are used on Tegra30 */
        BIT(14),        0,
        BIT(15),        0,
        BIT(16),        0,
@@ -207,13 +210,13 @@ static const int tegra30_xbar_mux_values[] = {
        BIT(22),        0,
        BIT(23),        0,
        BIT(24),        0,
-       /* index 0..20 above are used on Tegra114 */
+       /* index 0..21 above are used on Tegra114 */
        0,              BIT(0),
        0,              BIT(1),
        0,              BIT(2),
        0,              BIT(3),
        0,              BIT(4),
-       /* index 0..25 above are used on Tegra124 */
+       /* index 0..26 above are used on Tegra124 */
 };
 
 int tegra30_xbar_get_value_enum(struct snd_kcontrol *kcontrol,
@@ -331,6 +334,7 @@ MUX_ENUM_CTRL_DECL(i2s1_tx, 0x05);
 MUX_ENUM_CTRL_DECL(i2s2_tx, 0x06);
 MUX_ENUM_CTRL_DECL(i2s3_tx, 0x07);
 MUX_ENUM_CTRL_DECL(i2s4_tx, 0x08);
+MUX_ENUM_CTRL_DECL(spdif_tx, 0x0f);
 /* above controls are used on Tegra30 */
 MUX_ENUM_CTRL_DECL(apbif4_tx, 0x11);
 MUX_ENUM_CTRL_DECL(apbif5_tx, 0x12);
@@ -375,7 +379,8 @@ static const struct snd_soc_dapm_widget tegra30_xbar_widgets[] = {
        WIDGETS("I2S2", i2s2_tx),
        WIDGETS("I2S3", i2s3_tx),
        WIDGETS("I2S4", i2s4_tx),
-       /* index 0..8 above are used on Tegra30 */
+       WIDGETS("SPDIF", spdif_tx),
+       /* index 0..9 above are used on Tegra30 */
        WIDGETS("APBIF4", apbif4_tx),
        WIDGETS("APBIF5", apbif5_tx),
        WIDGETS("APBIF6", apbif6_tx),
@@ -392,7 +397,7 @@ static const struct snd_soc_dapm_widget tegra30_xbar_widgets[] = {
        TX_WIDGETS("ADX0-1"),
        TX_WIDGETS("ADX0-2"),
        TX_WIDGETS("ADX0-3"),
-       /* index 0..24 above are used on Tegra114 */
+       /* index 0..25 above are used on Tegra114 */
        WIDGETS("AMX1-0", amx10_tx),
        WIDGETS("AMX1-1", amx11_tx),
        WIDGETS("AMX1-2", amx12_tx),
@@ -403,7 +408,7 @@ static const struct snd_soc_dapm_widget tegra30_xbar_widgets[] = {
        TX_WIDGETS("ADX1-1"),
        TX_WIDGETS("ADX1-2"),
        TX_WIDGETS("ADX1-3"),
-       /* index 0..34 above are used on Tegra124 */
+       /* index 0..35 above are used on Tegra124 */
 };
 
 /* These routes used on Tegra30, Tegra114, Tegra124 */
@@ -419,7 +424,8 @@ static const struct snd_soc_dapm_widget tegra30_xbar_widgets[] = {
        { name " Mux",      "I2S1",     "I2S1 RX" },            \
        { name " Mux",      "I2S2",     "I2S2 RX" },            \
        { name " Mux",      "I2S3",     "I2S3 RX" },            \
-       { name " Mux",      "I2S4",     "I2S4 RX" },
+       { name " Mux",      "I2S4",     "I2S4 RX" },            \
+       { name " Mux",      "SPDIF",    "SPDIF RX" },
 
 /* These routes used on Tegra114 and Tegra124 */
 #define TEGRA114_ROUTES(name)                                  \
@@ -462,6 +468,7 @@ static const struct snd_soc_dapm_route tegra30_xbar_routes[] = {
        TEGRA30_ROUTES("I2S2")
        TEGRA30_ROUTES("I2S3")
        TEGRA30_ROUTES("I2S4")
+       TEGRA30_ROUTES("SPDIF")
        /* above routes are used on Tegra30 */
        TEGRA30_ROUTES("APBIF4")
        TEGRA30_ROUTES("APBIF5")
@@ -483,6 +490,7 @@ static const struct snd_soc_dapm_route tegra30_xbar_routes[] = {
        TEGRA114_ROUTES("I2S2")
        TEGRA114_ROUTES("I2S3")
        TEGRA114_ROUTES("I2S4")
+       TEGRA114_ROUTES("SPDIF")
        TEGRA114_ROUTES("APBIF4")
        TEGRA114_ROUTES("APBIF5")
        TEGRA114_ROUTES("APBIF6")
@@ -519,6 +527,7 @@ static const struct snd_soc_dapm_route tegra30_xbar_routes[] = {
        TEGRA124_ROUTES("I2S2")
        TEGRA124_ROUTES("I2S3")
        TEGRA124_ROUTES("I2S4")
+       TEGRA124_ROUTES("SPDIF")
        TEGRA124_ROUTES("APBIF4")
        TEGRA124_ROUTES("APBIF5")
        TEGRA124_ROUTES("APBIF6")
@@ -551,9 +560,9 @@ static struct snd_soc_codec_driver tegra30_xbar_codec = {
 
 static const struct tegra30_xbar_soc_data soc_data_tegra30 = {
        .regmap_config = &tegra30_xbar_regmap_config,
-       .num_dais = 9,
-       .num_mux_widgets = 9,
-       .num_mux0_input = 9,
+       .num_dais = 10,
+       .num_mux_widgets = 10,
+       .num_mux0_input = 10,
        .num_mux1_input = 0,
        .mask[0] = 0x1ff,
        .mask[1] = 0,
@@ -561,9 +570,9 @@ static const struct tegra30_xbar_soc_data soc_data_tegra30 = {
 
 static const struct tegra30_xbar_soc_data soc_data_tegra114 = {
        .regmap_config = &tegra30_xbar_regmap_config,
-       .num_dais = 25,
-       .num_mux_widgets = 20,
-       .num_mux0_input = 20,
+       .num_dais = 26,
+       .num_mux_widgets = 21,
+       .num_mux0_input = 21,
        .num_mux1_input = 0,
        .mask[0] = 0x1ffffff,
        .mask[1] = 0,
@@ -571,9 +580,9 @@ static const struct tegra30_xbar_soc_data soc_data_tegra114 = {
 
 static const struct tegra30_xbar_soc_data soc_data_tegra124 = {
        .regmap_config = &tegra124_xbar_regmap_config,
-       .num_dais = 35,
-       .num_mux_widgets = 25,
-       .num_mux0_input = 20,
+       .num_dais = 36,
+       .num_mux_widgets = 26,
+       .num_mux0_input = 21,
        .num_mux1_input = 5,
        .mask[0] = 0x1ffffff,
        .mask[1] = 0x7ff,