ARM: tegra11x: Support min residency per platform
Bo Yan [Fri, 8 Feb 2013 18:54:27 +0000 (10:54 -0800)]
Though there is no compelling reason to have different residency
requirement of Fmin@Vmin and non-CPU power gating for each platform,
still makes it possible to define these thresholds per platform.
If they are not defined, the default value are taken.

Change-Id: I663afb869338bd2e4078b15253c8f8e29c3d6b3c
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/198846
(cherry picked from commit 841fb812bfc793c3028b72cbfa05ce26a21226c4)
Reviewed-on: http://git-master/r/200860
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

arch/arm/mach-tegra/cpuidle-t11x.c
arch/arm/mach-tegra/pm.c
arch/arm/mach-tegra/pm.h

index 5592aa0..2f06029 100644 (file)
 #define ARCH_TIMER_CTRL_ENABLE          (1 << 0)
 #define ARCH_TIMER_CTRL_IT_MASK         (1 << 1)
 
-#define TEGRA_MIN_RESIDENCY_CLKGT_VMIN 2000
-#define TEGRA_MIN_RESIDENCY_NCPU_SLOW  2000
-#define TEGRA_MIN_RESIDENCY_NCPU_FAST  13000
-
 #ifdef CONFIG_SMP
 static s64 tegra_cpu_wake_by_time[4] = {
        LLONG_MAX, LLONG_MAX, LLONG_MAX, LLONG_MAX };
@@ -478,7 +474,7 @@ bool tegra11x_idle_power_down(struct cpuidle_device *dev,
 
        if (is_lp_cluster()) {
                if (slow_cluster_power_gating_noncpu &&
-                       (request > TEGRA_MIN_RESIDENCY_NCPU_SLOW))
+                       (request > tegra_min_residency_ncpu()))
                                power_gating_cpu_only = false;
                else
                        power_gating_cpu_only = true;
@@ -492,8 +488,8 @@ bool tegra11x_idle_power_down(struct cpuidle_device *dev,
                        else if (tegra_force_clkgt_at_vmin ==
                                        TEGRA_CPUIDLE_FORCE_NO_CLKGT_VMIN)
                                clkgt_at_vmin = false;
-                       else if ((request >= TEGRA_MIN_RESIDENCY_CLKGT_VMIN) &&
-                                (request < TEGRA_MIN_RESIDENCY_NCPU_FAST))
+                       else if ((request >= tegra_min_residency_vmin_fmin()) &&
+                                (request < tegra_min_residency_ncpu()))
                                clkgt_at_vmin = true;
 
                        if (!cpu_gating_only && tegra_rail_off_is_allowed()) {
@@ -501,7 +497,7 @@ bool tegra11x_idle_power_down(struct cpuidle_device *dev,
                                                TEGRA_POWER_CLUSTER_FORCE_MASK)
                                        power_gating_cpu_only = false;
                                else if (request >
-                                               TEGRA_MIN_RESIDENCY_NCPU_FAST)
+                                               tegra_min_residency_ncpu())
                                        power_gating_cpu_only = false;
                                else
                                        power_gating_cpu_only = true;
index a63471d..85d922d 100644 (file)
@@ -257,9 +257,35 @@ unsigned long tegra_cpu_lp2_min_residency(void)
 }
 
 #ifdef CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
+#define TEGRA_MIN_RESIDENCY_VMIN_FMIN  2000
+#define TEGRA_MIN_RESIDENCY_NCPU_SLOW  2000
+#define TEGRA_MIN_RESIDENCY_NCPU_FAST  13000
+#define TEGRA_MIN_RESIDENCY_CRAIL      20000
+
+unsigned long tegra_min_residency_vmin_fmin(void)
+{
+       return pdata && pdata->min_residency_vmin_fmin
+                       ? pdata->min_residency_vmin_fmin
+                       : TEGRA_MIN_RESIDENCY_VMIN_FMIN;
+}
+
+unsigned long tegra_min_residency_ncpu()
+{
+       if (is_lp_cluster()) {
+               return pdata && pdata->min_residency_ncpu_slow
+                       ? pdata->min_residency_ncpu_slow
+                       : TEGRA_MIN_RESIDENCY_NCPU_SLOW;
+       } else
+               return pdata && pdata->min_residency_ncpu_fast
+                       ? pdata->min_residency_ncpu_fast
+                       : TEGRA_MIN_RESIDENCY_NCPU_FAST;
+}
+
 unsigned long tegra_min_residency_crail(void)
 {
-       return pdata->min_residency_crail;
+       return pdata && pdata->min_residency_crail
+                       ? pdata->min_residency_crail
+                       : TEGRA_MIN_RESIDENCY_CRAIL;
 }
 #endif
 
index 94ff396..afabd71 100644 (file)
@@ -74,6 +74,9 @@ struct tegra_suspend_platform_data {
        unsigned int lp1_core_volt_high;
 #endif
 #ifdef CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
+       unsigned long min_residency_vmin_fmin;
+       unsigned long min_residency_ncpu_slow;
+       unsigned long min_residency_ncpu_fast;
        unsigned long min_residency_crail;
 #endif
 };
@@ -85,6 +88,8 @@ unsigned long tegra_cpu_power_good_time(void);
 unsigned long tegra_cpu_power_off_time(void);
 unsigned long tegra_cpu_lp2_min_residency(void);
 #ifdef CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
+unsigned long tegra_min_residency_vmin_fmin(void);
+unsigned long tegra_min_residency_ncpu(void);
 unsigned long tegra_min_residency_crail(void);
 #endif
 void tegra_clear_cpu_in_pd(int cpu);