arm: tegra: soctherm: PMC scratch register config for thermtrip
Diwakar Tundlam [Thu, 20 Dec 2012 20:56:10 +0000 (12:56 -0800)]
Initalize PMC scratch registers with regulator PMIC I2C bus and address.
Setup parameters to do shutdown on THERMTRIP from soc_therm.

Added support for Dalmore and Pluto and placeholders for ceres and pismo.

Bug 1200075

Change-Id: Ie9165febd88bd552c533e38c9cd073d8fe4f562d
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/173218
(cherry picked from commit e7b1053fac4275c1d4dd8ee7202366f7de1bb69c)
Reviewed-on: http://git-master/r/198959
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/board-dalmore-power.c
arch/arm/mach-tegra/board-pismo-power.c
arch/arm/mach-tegra/board-pluto-power.c
arch/arm/mach-tegra/board-roth-power.c
arch/arm/mach-tegra/tegra11_soctherm.c
arch/arm/mach-tegra/tegra11_soctherm.h

index c322f36..98ad38a 100644 (file)
@@ -53,6 +53,7 @@
 #include "devices.h"
 #include "tegra11_soctherm.h"
 #include "iomap.h"
+#include "tegra3_tsensor.h"
 
 #define PMC_CTRL               0x0
 #define PMC_CTRL_INTR_LOW      (1 << 17)
@@ -1176,6 +1177,26 @@ int __init dalmore_edp_init(void)
        return 0;
 }
 
+static struct tegra_tsensor_pmu_data tpdata_palmas = {
+       .reset_tegra = 1,
+       .pmu_16bit_ops = 0,
+       .controller_type = 0,
+       .pmu_i2c_addr = 0x58,
+       .i2c_controller_id = 4,
+       .poweroff_reg_addr = 0xa0,
+       .poweroff_reg_data = 0x0,
+};
+
+static struct tegra_tsensor_pmu_data tpdata_max77663 = {
+       .reset_tegra = 1,
+       .pmu_16bit_ops = 0,
+       .controller_type = 0,
+       .pmu_i2c_addr = 0x3c,
+       .i2c_controller_id = 4,
+       .poweroff_reg_addr = 0x41,
+       .poweroff_reg_data = 0x80,
+};
+
 static struct soctherm_platform_data dalmore_soctherm_data = {
        .therm = {
                [THERM_CPU] = {
@@ -1222,10 +1243,18 @@ static struct soctherm_platform_data dalmore_soctherm_data = {
                        },
                },
        },
+       .tshut_pmu_trip_data = &tpdata_palmas,
 };
 
 int __init dalmore_soctherm_init(void)
 {
+       struct board_info board_info;
+
+       tegra_get_board_info(&board_info);
+       if (!(board_info.board_id == BOARD_E1611 ||
+               board_info.board_id == BOARD_P2454))
+               dalmore_soctherm_data.tshut_pmu_trip_data = &tpdata_max77663;
+
        tegra_platform_edp_init(dalmore_soctherm_data.therm[THERM_CPU].trips,
                        &dalmore_soctherm_data.therm[THERM_CPU].num_trips);
        tegra_add_tj_trips(dalmore_soctherm_data.therm[THERM_CPU].trips,
index d842171..6b6a1d9 100644 (file)
@@ -814,6 +814,18 @@ int __init pismo_edp_init(void)
        return 0;
 }
 
+/* place holder for tpdata for as3720 regulator
+ * TODO: fill the correct i2c type, bus, reg_addr and data here:
+static struct tegra_tsensor_pmu_data tpdata_as3720 = {
+       .reset_tegra = ,
+       .pmu_16bit_ops = ,
+       .controller_type = ,
+       .pmu_i2c_addr = ,
+       .i2c_controller_id = ,
+       .poweroff_reg_addr = ,
+       .poweroff_reg_data = ,
+};
+*/
 
 static struct soctherm_platform_data pismo_soctherm_data = {
        .therm = {
@@ -861,6 +873,8 @@ static struct soctherm_platform_data pismo_soctherm_data = {
                        },
                },
        },
+       /* ENABLE THIS AFTER correctly setting up tpdata_as3720
+        * .tshut_pmu_trip_data = &tpdata_as3720, */
 };
 
 int __init pismo_soctherm_init(void)
index 9bb2387..f42ed09 100644 (file)
@@ -41,6 +41,7 @@
 #include "tegra_cl_dvfs.h"
 #include "devices.h"
 #include "tegra11_soctherm.h"
+#include "tegra3_tsensor.h"
 
 #define PMC_CTRL               0x0
 #define PMC_CTRL_INTR_LOW      (1 << 17)
@@ -718,6 +719,16 @@ int __init pluto_edp_init(void)
        return 0;
 }
 
+static struct tegra_tsensor_pmu_data tpdata_palmas = {
+       .reset_tegra = 1,
+       .pmu_16bit_ops = 0,
+       .controller_type = 0,
+       .pmu_i2c_addr = 0x58,
+       .i2c_controller_id = 4,
+       .poweroff_reg_addr = 0xa0,
+       .poweroff_reg_data = 0x0,
+};
+
 static struct soctherm_platform_data pluto_soctherm_data = {
        .therm = {
                [THERM_CPU] = {
@@ -764,6 +775,7 @@ static struct soctherm_platform_data pluto_soctherm_data = {
                        },
                },
        },
+       .tshut_pmu_trip_data = &tpdata_palmas,
 };
 
 int __init pluto_soctherm_init(void)
index cddafc1..1cb3bc4 100644 (file)
@@ -47,6 +47,7 @@
 #include "devices.h"
 #include "tegra11_soctherm.h"
 #include "iomap.h"
+#include "tegra3_tsensor.h"
 
 #define PMC_CTRL               0x0
 #define PMC_CTRL_INTR_LOW      (1 << 17)
@@ -699,12 +700,26 @@ int __init roth_edp_init(void)
        return 0;
 }
 
+static struct tegra_tsensor_pmu_data tpdata_palmas = {
+       .reset_tegra = 1,
+       .pmu_16bit_ops = 0,
+       .controller_type = 0,
+       .pmu_i2c_addr = 0x58,
+       .i2c_controller_id = 4,
+       .poweroff_reg_addr = 0xa0,
+       .poweroff_reg_data = 0x0,
+};
+
 static struct soctherm_platform_data roth_soctherm_data = {
        .therm = {
                [THERM_CPU] = {
                        .zone_enable = true,
                        .passive_delay = 1000,
-                       .num_trips = 3,
+                       .num_trips = 0, /* Disables the trips config below */
+                       /*
+                        * Following .trips config retained for compatibility
+                        * with dalmore/pluto and later enablement when needed
+                        */
                        .trips = {
                                {
                                        .cdev_type = "tegra-balanced",
@@ -745,6 +760,7 @@ static struct soctherm_platform_data roth_soctherm_data = {
                        },
                },
        },
+       .tshut_pmu_trip_data = &tpdata_palmas,
 };
 
 int __init roth_soctherm_init(void)
index 5e77cb7..3e1f28c 100644 (file)
@@ -40,6 +40,7 @@
 #include <mach/tegra_fuse.h>
 
 #include "iomap.h"
+#include "tegra3_tsensor.h"
 #include "tegra11_soctherm.h"
 
 /* Min temp granularity specified as X in 2^X.
@@ -247,6 +248,43 @@ static const int soc_therm_precision; /* default 0 -> low precision */
 #define FUSE_TSENSOR_CALIB_CP_MASK     0x1fff
 #define FUSE_TSENSOR_CALIB_BITS                13
 
+/* car register offsets needed for enabling HW throttling */
+#define CAR_SUPER_CCLK_DIVIDER         0x24
+#define CDIV_USE_THERM_CONTROLS_SHIFT  30
+#define CDIV_USE_THERM_CONTROLS_MASK   0x1
+
+/* pmc register offsets needed for powering off PMU */
+#define PMC_SCRATCH_WRITE_SHIFT                        2
+#define PMC_SCRATCH_WRITE_MASK                 0x1
+#define PMC_ENABLE_RST_SHIFT                   1
+#define PMC_ENABLE_RST_MASK                    0x1
+#define PMC_SENSOR_CTRL                                0x1B0
+#define PMC_SCRATCH54                          0x258
+#define PMC_SCRATCH55                          0x25C
+
+/* scratch54 register bit fields */
+#define PMU_OFF_DATA_SHIFT                     8
+#define PMU_OFF_DATA_MASK                      0xff
+#define PMU_OFF_ADDR_SHIFT                     0
+#define PMU_OFF_ADDR_MASK                      0xff
+
+/* scratch55 register bit fields */
+#define RESET_TEGRA_SHIFT                      31
+#define RESET_TEGRA_MASK                       0x1
+#define CONTROLLER_TYPE_SHIFT                  30
+#define CONTROLLER_TYPE_MASK                   0x1
+#define I2C_CONTROLLER_ID_SHIFT                        27
+#define I2C_CONTROLLER_ID_MASK                 0x7
+#define PINMUX_SHIFT                           24
+#define PINMUX_MASK                            0x7
+#define CHECKSUM_SHIFT                         16
+#define CHECKSUM_MASK                          0xff
+#define PMU_16BIT_SUPPORT_SHIFT                        15
+#define PMU_16BIT_SUPPORT_MASK                 0x1
+#define PMU_I2C_ADDRESS_SHIFT                  0
+#define PMU_I2C_ADDRESS_MASK                   0x7f
+
+
 #define PSKIP_CTRL_OC1_CPU                     0x490
 
 #define THROT_PSKIP_CTRL(throt, dev)           (THROT_PSKIP_CTRL_LITE_CPU + \
@@ -1089,6 +1127,42 @@ static void soctherm_fuse_read_tsensor(enum soctherm_sense sensor)
        soctherm_writel(r, TS_TSENSE_REG_OFFSET(TS_CPU0_CONFIG2, sensor));
 }
 
+static void soctherm_therm_trip_init(struct tegra_tsensor_pmu_data *data)
+{
+       u32 val, checksum;
+
+       if (!data)
+               return;
+
+       val = pmc_readl(PMC_SENSOR_CTRL);
+       val = REG_SET(val, PMC_SCRATCH_WRITE, 1);
+       val = REG_SET(val, PMC_ENABLE_RST, 1);
+       pmc_writel(val, PMC_SENSOR_CTRL);
+
+       /* Fill scratch registers to shutdown device on therm TRIP */
+       val = REG_SET(0, PMU_OFF_DATA, data->poweroff_reg_data);
+       val = REG_SET(val, PMU_OFF_ADDR, data->poweroff_reg_addr);
+       pmc_writel(val, PMC_SCRATCH54);
+
+       val = REG_SET(0, RESET_TEGRA, 1);
+       val = REG_SET(val, CONTROLLER_TYPE, data->controller_type);
+       val = REG_SET(val, I2C_CONTROLLER_ID, data->i2c_controller_id);
+       val = REG_SET(val, PINMUX, data->pinmux);
+       val = REG_SET(val, PMU_16BIT_SUPPORT, data->pmu_16bit_ops);
+       val = REG_SET(val, PMU_I2C_ADDRESS, data->pmu_i2c_addr);
+
+       checksum = data->poweroff_reg_addr +
+               data->poweroff_reg_data +
+               (val & 0xFF) +
+               ((val >> 8) & 0xFF) +
+               ((val >> 24) & 0xFF);
+       checksum &= 0xFF;
+       checksum = 0x100 - checksum;
+
+       val = REG_SET(val, CHECKSUM, checksum);
+       pmc_writel(val, PMC_SCRATCH55);
+}
+
 static int soctherm_init_platform_data(void)
 {
        struct soctherm_therm *therm;
@@ -1183,6 +1257,13 @@ static int soctherm_init_platform_data(void)
        r = REG_SET(r, CTL_LVL0_CPU0_EN, 1);
        soctherm_writel(r, CTL_LVL0_CPU0);
 
+       /* Enable PMC to shutdown */
+       soctherm_therm_trip_init(plat_data.tshut_pmu_trip_data);
+
+       r = clk_reset_readl(CAR_SUPER_CCLK_DIVIDER);
+       r = REG_SET(r, CDIV_USE_THERM_CONTROLS, 1);
+       clk_reset_writel(r, 0x24);
+
        /* Thermtrip */
        for (i = 0; i < THERM_SIZE; i++) {
                therm = &plat_data.therm[i];
@@ -1194,15 +1275,6 @@ static int soctherm_init_platform_data(void)
                                prog_hw_shutdown(&therm->trips[j], i);
        }
 
-       /* Enable PMC to shutdown */
-       r = pmc_readl(0x1b0);
-       r |= 0x2;
-       pmc_writel(r, 0x1b0);
-
-       r = clk_reset_readl(0x24);
-       r |= (1 << 30);
-       clk_reset_writel(r, 0x24);
-
        return 0;
 }
 
@@ -1404,6 +1476,16 @@ static int regs_show(struct seq_file *s, void *data)
                   !soc_therm_precision ? state * 2 : state);
        state = REG_GET(r, THERMTRIP_CPU_EN);
        seq_printf(s, "%d\n", state);
+       state = REG_GET(r, THERMTRIP_TSENSE_THRESH);
+       seq_printf(s, "THERMTRIP_TSENSE_THRESH: %d ", state);
+       state = REG_GET(r, THERMTRIP_TSENSE_EN);
+       seq_printf(s, "%d\n", state);
+       state = REG_GET(r, THERMTRIP_GPUMEM_THRESH);
+       seq_printf(s, "THERMTRIP_GPUMEM_THRESH: %d ", state);
+       state = REG_GET(r, THERMTRIP_GPU_EN);
+       seq_printf(s, "gpu=%d ", state);
+       state = REG_GET(r, THERMTRIP_MEM_EN);
+       seq_printf(s, "mem=%d\n", state);
 
 
        seq_printf(s, "\n-----THROTTLE-----\n");
index f67a08a..182e6ca 100644 (file)
@@ -85,6 +85,17 @@ struct soctherm_throttle {
        struct soctherm_throttle_dev devs[THROTTLE_DEV_SIZE];
 };
 
+struct soctherm_tsensor_pmu_data {
+       u8 poweroff_reg_data;
+       u8 poweroff_reg_addr;
+       u8 reset_tegra;
+       u8 controller_type;
+       u8 i2c_controller_id;
+       u8 pinmux;
+       u8 pmu_16bit_ops;
+       u8 pmu_i2c_addr;
+};
+
 struct soctherm_platform_data {
        unsigned long soctherm_clk_rate;
        unsigned long tsensor_clk_rate;
@@ -92,9 +103,7 @@ struct soctherm_platform_data {
        struct soctherm_sensor sensor_data[TSENSE_SIZE];
        struct soctherm_therm therm[THERM_SIZE];
        struct soctherm_throttle throttle[THROTTLE_SIZE];
-
-       int edp_weights[12];
-       int edp_threshold;
+       struct tegra_tsensor_pmu_data *tshut_pmu_trip_data;
 };
 
 #ifdef CONFIG_TEGRA_SOCTHERM