ARM: tegra11: clock: Don't report PLLC2/C3 lock timeout
Alex Frid [Tue, 5 Mar 2013 00:32:02 +0000 (16:32 -0800)]
- Since PLLC2/C3 lock bits may fluctuate after pll is locked, don't
report timeout in this case.
- Expanded lock timeout message with the state of lock register

Bug 1057353
Bug 1213649
Bug 1232950

Change-Id: I33666bccba098733f29b01ffb3518e79603e3abf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/206173
(cherry picked from commit b88abe28f9d3f8aec4b3602d6f6100486866e078)
Reviewed-on: http://git-master/r/206133
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c

index f91022e..d8b5358 100644 (file)
@@ -1816,15 +1816,28 @@ static int tegra11_pll_clk_wait_for_lock(
 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
 #if USE_PLL_LOCK_BITS
        int i;
+       u32 val = 0;
+
        for (i = 0; i < (c->u.pll.lock_delay / PLL_PRE_LOCK_DELAY + 1); i++) {
                udelay(PLL_PRE_LOCK_DELAY);
-               if ((clk_readl(lock_reg) & lock_bits) == lock_bits) {
+               val = clk_readl(lock_reg);
+               if ((val & lock_bits) == lock_bits) {
                        udelay(PLL_POST_LOCK_DELAY);
                        return 0;
                }
        }
-       pr_err("Timed out waiting for lock bit on pll %s\n", c->name);
-       return -1;
+
+       /* PLLCX lock bits may fluctuate after the lock - don't report timeout
+          in this case (phase lock bit happens to uniquely identify PLLCX) */
+       if (lock_bits & PLLCX_BASE_PHASE_LOCK) {
+               pr_debug("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
+                        c->name, lock_reg, val);
+               return 0;
+       } else {
+               pr_err("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
+                      c->name, lock_reg, val);
+               return -ETIMEDOUT;
+       }
 #endif
        udelay(c->u.pll.lock_delay);
 #endif