ARM: tegra: ceres: Enable vim2_clk for camera
Sudhir Vyas [Tue, 5 Feb 2013 13:25:19 +0000 (05:25 -0800)]
Sensor input clock (cam_mclk) is sourced from vi_sensor2
on ceres, which needs vim2_clk enable.

Bug 1180011
Bug 1180015

Change-Id: I061d43926eaa378e44cbdd00f93fff6b8210a2ec
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/197467
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

arch/arm/mach-tegra/tegra14_clocks.c

index 4c98c4f..e568f34 100644 (file)
@@ -5985,7 +5985,7 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("isp_sapor", "isp_sapor",            NULL,   163,    0x654,  26000000, mux_pllm_pllc_pllp_plla,      MUX | DIV_U71 | PERIPH_NO_RESET),
        PERIPH_CLK("hdmi_audio","hdmi_audio",           NULL,   176,    0x668,  26000000, mux_pllp_pllc_clkm,           MUX | DIV_U71 | PERIPH_NO_RESET),
        PERIPH_CLK("clk72mhz",  "clk72mhz",             NULL,   177,    0x66c,  26000000, mux_pllp3_pllc_clkm,          MUX | DIV_U71 | PERIPH_NO_RESET),
-       PERIPH_CLK("vim2_clk",  "vim2_clk",             NULL,   171,    0,      26000000, mux_clk_m,                    PERIPH_NO_RESET),
+       PERIPH_CLK("vim2_clk",  "tegra_camera",         "vim2_clk",     171,    0,      26000000, mux_clk_m,                    PERIPH_NO_RESET),
        PERIPH_CLK("vgpio",     "vgpio",                NULL,   172,    0,      26000000, mux_clk_m,                    PERIPH_NO_RESET),
 
        SHARED_CLK("avp.sclk",  "tegra-avp",            "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),