Merge branch 'late/fixes' into fixes
Olof Johansson [Thu, 9 May 2013 20:05:00 +0000 (13:05 -0700)]
* late/fixes:
  ARM: OMAP2+: Fix unmet direct dependencies for SERIAL_OMAP
  ARM: ux500: always select ABX500_CORE
  ARM: SIRF: select SMP_ON_UP only on SMP builds
  ARM: SPEAr: conditionalize l2x0 support
  ARM: imx: build CPU suspend code only when needed
  ARM: OMAP: build SMP code only for OMAP4/5
  ARM: tegra: Tegra114 needs CPU_FREQ_TABLE
  ARM: default machine descriptor for multiplatform

Signed-off-by: Olof Johansson <olof@lixom.net>

1  2 
arch/arm/Kconfig
arch/arm/configs/omap2plus_defconfig
arch/arm/kernel/setup.c
arch/arm/mach-imx/headsmp.S
arch/arm/mach-omap2/Kconfig
arch/arm/mach-omap2/Makefile
arch/arm/mach-prima2/Kconfig
arch/arm/mach-spear/spear13xx.c
arch/arm/mach-tegra/Kconfig
arch/arm/mach-ux500/Kconfig

@@@ -894,10 -1011,9 +894,9 @@@ config ARCH_MULTI_V
        select CPU_V6
  
  config ARCH_MULTI_V7
 -      bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
 +      bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
        default y
        select ARCH_MULTI_V6_V7
-       select ARCH_VEXPRESS
        select CPU_V7
  
  config ARCH_MULTI_V6_V7
Simple merge
Simple merge
@@@ -24,12 -24,14 +24,12 @@@ ENTRY(v7_secondary_startup
  ENDPROC(v7_secondary_startup)
  #endif
  
- #ifdef CONFIG_PM
+ #ifdef CONFIG_ARM_CPU_SUSPEND
  /*
 - * The following code is located into the .data section.  This is to
 - * allow phys_l2x0_saved_regs to be accessed with a relative load
 - * as we are running on physical address here.
 + * The following code must assume it is running from physical address
 + * where absolute virtual addresses to the data section have to be
 + * turned into relative ones.
   */
 -      .data
 -      .align
  
  #ifdef CONFIG_CACHE_L2X0
        .macro  pl310_resume
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@@@ -36,9 -16,8 +36,9 @@@ config ARCH_MARC
        default y
        select ARM_GIC
        select CPU_V7
 +      select HAVE_ARM_SCU if SMP
        select HAVE_SMP
-       select SMP_ON_UP
+       select SMP_ON_UP if SMP
        help
            Support for CSR SiRFSoC ARM Cortex A9 Platform
  
index 3621599,0000000..7aa6e8c
mode 100644,000000..100644
--- /dev/null
@@@ -1,126 -1,0 +1,128 @@@
 +/*
 + * arch/arm/mach-spear13xx/spear13xx.c
 + *
 + * SPEAr13XX machines common source file
 + *
 + * Copyright (C) 2012 ST Microelectronics
 + * Viresh Kumar <viresh.linux@gmail.com>
 + *
 + * This file is licensed under the terms of the GNU General Public
 + * License version 2. This program is licensed "as is" without any
 + * warranty of any kind, whether express or implied.
 + */
 +
 +#define pr_fmt(fmt) "SPEAr13xx: " fmt
 +
 +#include <linux/amba/pl022.h>
 +#include <linux/clk.h>
 +#include <linux/clocksource.h>
 +#include <linux/err.h>
 +#include <linux/of.h>
 +#include <asm/hardware/cache-l2x0.h>
 +#include <asm/mach/map.h>
 +#include <mach/spear.h>
 +#include "generic.h"
 +
 +void __init spear13xx_l2x0_init(void)
 +{
 +      /*
 +       * 512KB (64KB/way), 8-way associativity, parity supported
 +       *
 +       * FIXME: 9th bit, of Auxillary Controller register must be set
 +       * for some spear13xx devices for stable L2 operation.
 +       *
 +       * Enable Early BRESP, L2 prefetch for Instruction and Data,
 +       * write alloc and 'Full line of zero' options
 +       *
 +       */
++      if (!IS_ENABLED(CONFIG_CACHE_L2X0))
++              return;
 +
 +      writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL);
 +
 +      /*
 +       * Program following latencies in order to make
 +       * SPEAr1340 work at 600 MHz
 +       */
 +      writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL);
 +      writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL);
 +      l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff);
 +}
 +
 +/*
 + * Following will create 16MB static virtual/physical mappings
 + * PHYSICAL           VIRTUAL
 + * 0xB3000000         0xFE000000
 + * 0xE0000000         0xFD000000
 + * 0xEC000000         0xFC000000
 + * 0xED000000         0xFB000000
 + */
 +struct map_desc spear13xx_io_desc[] __initdata = {
 +      {
 +              .virtual        = (unsigned long)VA_PERIP_GRP2_BASE,
 +              .pfn            = __phys_to_pfn(PERIP_GRP2_BASE),
 +              .length         = SZ_16M,
 +              .type           = MT_DEVICE
 +      }, {
 +              .virtual        = (unsigned long)VA_PERIP_GRP1_BASE,
 +              .pfn            = __phys_to_pfn(PERIP_GRP1_BASE),
 +              .length         = SZ_16M,
 +              .type           = MT_DEVICE
 +      }, {
 +              .virtual        = (unsigned long)VA_A9SM_AND_MPMC_BASE,
 +              .pfn            = __phys_to_pfn(A9SM_AND_MPMC_BASE),
 +              .length         = SZ_16M,
 +              .type           = MT_DEVICE
 +      }, {
 +              .virtual        = (unsigned long)VA_L2CC_BASE,
 +              .pfn            = __phys_to_pfn(L2CC_BASE),
 +              .length         = SZ_4K,
 +              .type           = MT_DEVICE
 +      },
 +};
 +
 +/* This will create static memory mapping for selected devices */
 +void __init spear13xx_map_io(void)
 +{
 +      iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
 +}
 +
 +static void __init spear13xx_clk_init(void)
 +{
 +      if (of_machine_is_compatible("st,spear1310"))
 +              spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE);
 +      else if (of_machine_is_compatible("st,spear1340"))
 +              spear1340_clk_init(VA_MISC_BASE);
 +      else
 +              pr_err("%s: Unknown machine\n", __func__);
 +}
 +
 +void __init spear13xx_timer_init(void)
 +{
 +      char pclk_name[] = "osc_24m_clk";
 +      struct clk *gpt_clk, *pclk;
 +
 +      spear13xx_clk_init();
 +
 +      /* get the system timer clock */
 +      gpt_clk = clk_get_sys("gpt0", NULL);
 +      if (IS_ERR(gpt_clk)) {
 +              pr_err("%s:couldn't get clk for gpt\n", __func__);
 +              BUG();
 +      }
 +
 +      /* get the suitable parent clock for timer*/
 +      pclk = clk_get(NULL, pclk_name);
 +      if (IS_ERR(pclk)) {
 +              pr_err("%s:couldn't get %s as parent for gpt\n", __func__,
 +                              pclk_name);
 +              BUG();
 +      }
 +
 +      clk_set_parent(gpt_clk, pclk);
 +      clk_put(gpt_clk);
 +      clk_put(pclk);
 +
 +      spear_setup_of_timer();
 +      clocksource_of_init();
 +}
Simple merge
Simple merge