ARM: tegra12: clock: Convert mselect clock to shared bus
Alex Frid [Wed, 27 Nov 2013 01:28:47 +0000 (17:28 -0800)]
Converted mselect clock to bus shared between CPU and PCIE users.

Bug 1413311

Change-Id: Ibb34a474021e18cd842627bf66c5f466c5e355f5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/336457
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/tegra12_clocks.c
arch/arm/mach-tegra/tegra12_dvfs.c

index d8e4bc2..9f14f23 100644 (file)
@@ -454,6 +454,7 @@ static __initdata struct tegra_clk_init_table tegra12x_clk_init_table[] = {
        { "sbc4.sclk",  NULL,           40000000,       false},
        { "sbc5.sclk",  NULL,           40000000,       false},
        { "sbc6.sclk",  NULL,           40000000,       false},
+       { "cpu.mselect", NULL,          102000000,      true},
        { "gpu_ref",    NULL,           0,              true},
 #ifdef CONFIG_TEGRA_PLLM_SCALED
        { "vi",         "pll_p",        0,              false},
index fb953e4..2db5fa3 100644 (file)
@@ -7446,6 +7446,28 @@ static struct clk tegra_clk_host1x = {
        .rate_change_nh = &host1x_rate_change_nh,
 };
 
+static struct raw_notifier_head mselect_rate_change_nh;
+
+static struct clk tegra_clk_mselect = {
+       .name      = "mselect",
+       .lookup    = {
+               .dev_id = "mselect",
+       },
+       .ops       = &tegra_1xbus_clk_ops,
+       .reg       = 0x3b4,
+       .inputs    = mux_pllp_clkm,
+       .flags     = MUX | DIV_U71 | DIV_U71_INT,
+       .max_rate  = 408000000,
+       .min_rate  = 12000000,
+       .u.periph = {
+               .clk_num   = 99,
+               .pll_low = &tegra_pll_p,
+               .pll_high = &tegra_pll_p,
+               .threshold = 408000000,
+       },
+       .rate_change_nh = &mselect_rate_change_nh,
+};
+
 #ifdef CONFIG_TEGRA_DUAL_CBUS
 
 static struct raw_notifier_head c2bus_rate_change_nh;
@@ -7954,7 +7976,6 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("pcie",      "tegra-pcie",           "pcie", 70,     0,      250000000, mux_clk_m,                   0),
        PERIPH_CLK("afi",       "tegra-pcie",           "afi",  72,     0,      250000000, mux_clk_m,                   0),
        PERIPH_CLK("se",        "se",                   NULL,   127,    0x42c,  600000000, mux_pllp_pllc2_c_c3_pllm_clkm,       MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
-       PERIPH_CLK("mselect",   "mselect",              NULL,   99,     0x3b4,  408000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_INT),
        PERIPH_CLK("cl_dvfs_ref", "tegra_cl_dvfs",      "ref",  155,    0x62c,  54000000,  mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
        PERIPH_CLK("cl_dvfs_soc", "tegra_cl_dvfs",      "soc",  155,    0x630,  54000000,  mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
        PERIPH_CLK("soc_therm", "soc_therm",            NULL,   78,     0x644,  136000000, mux_pllm_pllc_pllp_plla_v2,  MUX | DIV_U71 | PERIPH_ON_APB),
@@ -8059,6 +8080,11 @@ struct clk tegra_list_clks[] = {
        SHARED_LIMIT("cap.vcore.host1x", "cap.vcore.host1x", NULL, &tegra_clk_host1x, NULL,  0, SHARED_CEILING),
        SHARED_LIMIT("floor.host1x", "floor.host1x",    NULL,     &tegra_clk_host1x, NULL,  0, 0),
        SHARED_CLK("override.host1x", "override.host1x", NULL,    &tegra_clk_host1x, NULL,  0, SHARED_OVERRIDE),
+
+       SHARED_CLK("cpu.mselect",         "cpu",        "mselect",   &tegra_clk_mselect, NULL,  0, 0),
+       SHARED_CLK("pcie.mselect",        "tegra_pcie", "mselect",   &tegra_clk_mselect, NULL,  0, 0),
+       SHARED_LIMIT("cap.vcore.mselect", "cap.vcore.mselect", NULL, &tegra_clk_mselect, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("override.mselect",    "override.mselect",  NULL, &tegra_clk_mselect, NULL,  0, SHARED_OVERRIDE),
 };
 
 /* VI, ISP buses */
@@ -8333,6 +8359,7 @@ struct clk *tegra_ptr_clks[] = {
        &tegra_clk_apb,
        &tegra_clk_emc,
        &tegra_clk_host1x,
+       &tegra_clk_mselect,
 #ifdef CONFIG_TEGRA_DUAL_CBUS
        &tegra_clk_c2bus,
        &tegra_clk_c3bus,
@@ -8747,7 +8774,7 @@ int tegra_update_mselect_rate(unsigned long cpu_rate)
        unsigned long mselect_rate;
 
        if (!mselect) {
-               mselect = tegra_get_clock_by_name("mselect");
+               mselect = tegra_get_clock_by_name("cpu.mselect");
                if (!mselect)
                        return -ENODEV;
        }
@@ -8757,11 +8784,7 @@ int tegra_update_mselect_rate(unsigned long cpu_rate)
           cpu rate is in kHz, mselect rate is in Hz */
        mselect_rate = DIV_ROUND_UP(cpu_rate, 2) * 1000;
        mselect_rate = min(mselect_rate, 102000000UL);
-
-       if (mselect_rate != clk_get_rate(mselect))
-               return clk_set_rate(mselect, mselect_rate);
-
-       return 0;
+       return clk_set_rate(mselect, mselect_rate);
 }
 #endif
 
index c1ec37e..09b8877 100644 (file)
@@ -1145,6 +1145,7 @@ static struct core_dvfs_cap_table tegra12_core_cap_table[] = {
        { .cap_name = "cap.vcore.sclk" },
        { .cap_name = "cap.vcore.emc" },
        { .cap_name = "cap.vcore.host1x" },
+       { .cap_name = "cap.vcore.mselect" },
 };
 
 static struct core_bus_limit_table tegra12_gpu_cap_syfs = {