[ARM] 4092/1: i.MX/MX1 CPU Frequency scaling latency definition
Pavel Pisa [Fri, 12 Jan 2007 08:57:22 +0000 (09:57 +0100)]
The transition latency has to be defined and reasonably
small to allow on-demand and conservative governors.
The value has been defined according to manual.
The imx_set_target() protected against seen out of range
requests now.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

arch/arm/mach-imx/cpufreq.c

index ac5f998..4f66e90 100644 (file)
@@ -184,6 +184,17 @@ static int imx_set_target(struct cpufreq_policy *policy,
        long sysclk;
        unsigned int bclk_div = 1;
 
+       /*
+        * Some governors do not respects CPU and policy lower limits
+        * which leads to bad things (division by zero etc), ensure
+        * that such things do not happen.
+        */
+       if(target_freq < policy->cpuinfo.min_freq)
+               target_freq = policy->cpuinfo.min_freq;
+
+       if(target_freq < policy->min)
+               target_freq = policy->min;
+
        freq = target_freq * 1000;
 
        pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n",
@@ -258,7 +269,8 @@ static int __init imx_cpufreq_driver_init(struct cpufreq_policy *policy)
        policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
        policy->cpuinfo.min_freq = 8000;
        policy->cpuinfo.max_freq = 200000;
-       policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+        /* Manual states, that PLL stabilizes in two CLK32 periods */
+       policy->cpuinfo.transition_latency = 4 * 1000000000LL / CLK32;
        return 0;
 }