Merge branch 'linux-3.10.33' into dev-kernel-3.10
Deepak Nibade [Tue, 11 Mar 2014 10:36:31 +0000 (15:36 +0530)]
Bug 1456092

Change-Id: I3021247ec68a3c2dddd9e98cde13d70a45191d53
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>

65 files changed:
1  2 
Documentation/filesystems/proc.txt
Makefile
arch/arm/include/asm/cacheflush.h
arch/arm/kernel/process.c
arch/arm/mm/dma-mapping.c
arch/arm/mm/proc-v7.S
arch/arm64/include/asm/arch_timer.h
arch/arm64/include/asm/cacheflush.h
arch/arm64/include/asm/pgtable.h
arch/arm64/kernel/ptrace.c
arch/arm64/kernel/setup.c
arch/arm64/kernel/smp.c
arch/arm64/mm/flush.c
arch/arm64/mm/mmu.c
arch/arm64/mm/proc.S
arch/x86/mm/fault.c
arch/x86/xen/p2m.c
drivers/clocksource/arm_arch_timer.c
drivers/clocksource/dw_apb_timer_of.c
drivers/cpufreq/powernow-k8.c
drivers/i2c/busses/Kconfig
drivers/input/input.c
drivers/input/joystick/xpad.c
drivers/mmc/card/block.c
drivers/net/tun.c
drivers/net/usb/smsc95xx.c
drivers/net/usb/usbnet.c
drivers/net/wireless/rtlwifi/pci.c
drivers/pinctrl/core.c
drivers/usb/core/hub.c
drivers/usb/gadget/composite.c
drivers/usb/host/ehci-hcd.c
drivers/usb/host/ehci.h
fs/ext4/super.c
fs/fs-writeback.c
fs/fuse/dev.c
fs/nfs/nfs4proc.c
include/linux/mm.h
include/linux/mm_types.h
kernel/fork.c
kernel/freezer.c
kernel/futex.c
kernel/sched/core.c
kernel/sched/debug.c
kernel/sched/rt.c
kernel/sched/sched.h
kernel/time/timekeeping.c
kernel/trace/trace.c
mm/memcontrol.c
mm/mempolicy.c
mm/mprotect.c
mm/oom_kill.c
mm/vmscan.c
net/core/sock.c
net/ipv4/devinet.c
net/ipv4/tcp_output.c
net/ipv4/udp.c
net/unix/af_unix.c
security/selinux/hooks.c
sound/pci/hda/hda_intel.c
sound/pci/hda/patch_hdmi.c
sound/soc/codecs/max98090.c
sound/soc/tegra/tegra20_i2s.c
sound/soc/tegra/tegra20_spdif.c
sound/soc/tegra/tegra30_i2s.c

Simple merge
diff --cc Makefile
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@@@ -1687,18 -1308,11 +1687,17 @@@ static void *arm_iommu_alloc_attrs(stru
        struct page **pages;
        void *addr = NULL;
  
 -      *handle = DMA_ERROR_CODE;
 +      /* Following is a work-around (a.k.a. hack) to prevent pages
 +       * with __GFP_COMP being passed to split_page() which cannot
 +       * handle them.  The real problem is that this flag probably
 +       * should be 0 on ARM as it is not supported on this
 +       * platform--see CONFIG_HUGETLB_PAGE. */
 +      gfp &= ~(__GFP_COMP);
 +
        size = PAGE_ALIGN(size);
  
-       if (gfp & GFP_ATOMIC)
+       if (!(gfp & __GFP_WAIT))
 -              return __iommu_alloc_atomic(dev, size, handle);
 +              return __iommu_alloc_atomic(dev, size, handle, attrs);
  
        pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
        if (!pages)
@@@ -676,8 -329,6 +676,7 @@@ __v7_setup
  
  3:    mov     r10, #0
        mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
-       dsb
 +4:
  #ifdef CONFIG_MMU
        mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
        v7_ttb_setup r10, r4, r8, r5            @ TTBCR, TTBRx setup
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  #include <asm/tlbflush.h>
  #include <asm/traps.h>
  #include <asm/memblock.h>
 +#include <asm/mmu_context.h>
  #include <asm/psci.h>
- #include <asm/virt.h>
- #include <asm/arch_timer.h>
  
 +#include <asm/mach/arch.h>
 +#include <asm/system_misc.h>
 +
  unsigned int processor_id;
  EXPORT_SYMBOL(processor_id);
  
@@@ -414,18 -280,6 +412,9 @@@ void __init setup_arch(char **cmdline_p
        conswitchp = &dummy_con;
  #endif
  #endif
 +
-       /* Supply the real ARCH timer counter to skip the
-        * arch_timer_read_zero (arm_arch_timer.c) which
-        * causes hang in udelay. Proper counter setup will
-        * be performed in a later state in time_init. */
-       if (is_hyp_mode_available())
-               arch_timer_read_counter = arch_counter_get_cntpct;
-       else
-               arch_timer_read_counter = arch_counter_get_cntvct;
 +      if (machine_desc->init_early)
 +              machine_desc->init_early();
  }
  
  static int __init arm64_device_init(void)
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@@@ -2085,12 -1931,8 +2085,13 @@@ static int mmc_blk_issue_rq(struct mmc_
        struct mmc_card *card = md->queue.card;
        struct mmc_host *host = card->host;
        unsigned long flags;
+       unsigned int cmd_flags = req ? req->cmd_flags : 0;
  
 +#ifdef CONFIG_MMC_BLOCK_DEFERRED_RESUME
 +      if (mmc_bus_needs_resume(card->host))
 +              mmc_resume_bus(card->host);
 +#endif
 +
        if (req && !mq->mqrq_prev->req)
                /* claim host only for the first request */
                mmc_claim_host(card->host);
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@@@ -198,11 -200,7 +198,12 @@@ struct ehci_hcd {                        /* one per controll
        unsigned                has_synopsys_hc_bug:1; /* Synopsys HC */
        unsigned                frame_index_bug:1; /* MosChip (AKA NetMos) */
        unsigned                need_oc_pp_cycle:1; /* MPC834X port power */
 +#ifdef CONFIG_USB_EHCI_TEGRA
 +      unsigned                controller_resets_phy:1;
 +      unsigned                controller_remote_wakeup:1;
 +      unsigned                broken_hostpc_phcd:1;
 +#endif
+       unsigned                imx28_write_fix:1; /* For Freescale i.MX28 */
  
        /* required for usb32 quirk */
        #define OHCI_CTRL_HCFS          (3 << 6)
diff --cc fs/ext4/super.c
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diff --cc fs/fuse/dev.c
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@@@ -462,14 -465,45 +470,55 @@@ static inline cpumask_t *mm_cpumask(str
        return mm->cpu_vm_mask_var;
  }
  
 +
 +/* Return the name for an anonymous mapping or NULL for a file-backed mapping */
 +static inline const char __user *vma_get_anon_name(struct vm_area_struct *vma)
 +{
 +      if (vma->vm_file)
 +              return NULL;
 +
 +      return vma->shared.anon_name;
 +}
 +
+ #if defined(CONFIG_NUMA_BALANCING) || defined(CONFIG_COMPACTION)
+ /*
+  * Memory barriers to keep this state in sync are graciously provided by
+  * the page table locks, outside of which no page table modifications happen.
+  * The barriers below prevent the compiler from re-ordering the instructions
+  * around the memory barriers that are already present in the code.
+  */
+ static inline bool mm_tlb_flush_pending(struct mm_struct *mm)
+ {
+       barrier();
+       return mm->tlb_flush_pending;
+ }
+ static inline void set_tlb_flush_pending(struct mm_struct *mm)
+ {
+       mm->tlb_flush_pending = true;
+       /*
+        * Guarantee that the tlb_flush_pending store does not leak into the
+        * critical section updating the page tables
+        */
+       smp_mb__before_spinlock();
+ }
+ /* Clearing is done after a TLB flush, which also provides a barrier. */
+ static inline void clear_tlb_flush_pending(struct mm_struct *mm)
+ {
+       barrier();
+       mm->tlb_flush_pending = false;
+ }
+ #else
+ static inline bool mm_tlb_flush_pending(struct mm_struct *mm)
+ {
+       return false;
+ }
+ static inline void set_tlb_flush_pending(struct mm_struct *mm)
+ {
+ }
+ static inline void clear_tlb_flush_pending(struct mm_struct *mm)
+ {
+ }
+ #endif
  #endif /* _LINUX_MM_TYPES_H */
diff --cc kernel/fork.c
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diff --cc kernel/futex.c
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diff --cc mm/memcontrol.c
Simple merge
diff --cc mm/mempolicy.c
Simple merge
diff --cc mm/mprotect.c
Simple merge
diff --cc mm/oom_kill.c
Simple merge
diff --cc mm/vmscan.c
Simple merge
diff --cc net/core/sock.c
Simple merge
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diff --cc net/ipv4/udp.c
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@@@ -2681,34 -2594,30 +2728,34 @@@ static const struct hda_codec_preset sn
  { .id = 0x10de0005, .name = "MCP77/78 HDMI",  .patch = patch_nvhdmi_8ch_7x },
  { .id = 0x10de0006, .name = "MCP77/78 HDMI",  .patch = patch_nvhdmi_8ch_7x },
  { .id = 0x10de0007, .name = "MCP79/7A HDMI",  .patch = patch_nvhdmi_8ch_7x },
- { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de000c, .name = "MCP89 HDMI",     .patch = patch_generic_hdmi },
- { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
+ { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi },
+ { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi },
+ { .id = 0x10de000c, .name = "MCP89 HDMI",     .patch = patch_nvhdmi },
+ { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi },
+ { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi },
+ { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi },
+ { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi },
+ { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi },
+ { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi },
+ { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi },
+ { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi },
  /* 17 is known to be absent */
- { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
 -{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi },
 -{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi },
 -{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi },
 -{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi },
 -{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi },
 -{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi },
 -{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi },
 -{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi },
 -{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi },
 -{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi },
 -{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi },
 -{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi },
++{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi},
++{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi},
++{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi},
++{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi},
++{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi},
 +{ .id = 0x10de0020, .name = "Tegra30 HDMI",   .patch = patch_generic_hdmi },
 +{ .id = 0x10de0022, .name = "Tegra35 HDMI",   .patch = patch_generic_hdmi },
 +{ .id = 0x10de002a, .name = "Tegra14x HDMI",  .patch = patch_generic_hdmi },
 +{ .id = 0x10de0028, .name = "Tegra12x HDMI",  .patch = patch_generic_hdmi },
- { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
- { .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_generic_hdmi },
++{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi},
++{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi},
++{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi},
++{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi},
++{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi},
++{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi},
++{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi},
  { .id = 0x10de0067, .name = "MCP67 HDMI",     .patch = patch_nvhdmi_2ch },
  { .id = 0x10de8001, .name = "MCP73 HDMI",     .patch = patch_nvhdmi_2ch },
  { .id = 0x11069f80, .name = "VX900 HDMI/DP",  .patch = patch_via_hdmi },
@@@ -2520,13 -1768,21 +2520,23 @@@ static int max98090_set_bias_level(stru
                break;
  
        case SND_SOC_BIAS_STANDBY:
+               if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
 -                      ret = regcache_sync(max98090->regmap);
++                      ret = snd_soc_cache_sync(codec);
+                       if (ret != 0) {
+                               dev_err(codec->dev,
+                                       "Failed to sync cache: %d\n", ret);
+                               return ret;
+                       }
+               }
+               break;
        case SND_SOC_BIAS_OFF:
 +              snd_soc_update_bits(codec, M98090_REG_3E_PWR_EN_IN,
 +                      M98090_PWR_MBEN_MASK, 0);
                /* Set internal pull-up to lowest power mode */
 -              snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
 +              snd_soc_update_bits(codec, M98090_REG_3D_CFG_JACK,
                        M98090_JDWK_MASK, M98090_JDWK_MASK);
 -              regcache_mark_dirty(max98090->regmap);
 +              codec->cache_sync = 1;
                break;
        }
        codec->dapm.bias_level = level;
Simple merge
@@@ -67,16 -67,15 +67,16 @@@ static int tegra20_spdif_hw_params(stru
  {
        struct device *dev = dai->dev;
        struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
-       unsigned int mask, val;
+       unsigned int mask = 0, val = 0;
 -      int ret, spdifclock;
 +      int ret, srate, spdifclock;
 +      u32 ch_sta[2] = {0, 0};
  
-       mask = TEGRA20_SPDIF_CTRL_PACK |
-              TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
+       mask |= TEGRA20_SPDIF_CTRL_PACK |
+               TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
        switch (params_format(params)) {
        case SNDRV_PCM_FORMAT_S16_LE:
-               val = TEGRA20_SPDIF_CTRL_PACK |
-                     TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
+               val |= TEGRA20_SPDIF_CTRL_PACK |
+                      TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
                break;
        default:
                return -EINVAL;
@@@ -163,38 -117,21 +163,38 @@@ static int tegra30_i2s_set_fmt(struct s
                                unsigned int fmt)
  {
        struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-       unsigned int mask, val;
+       unsigned int mask = 0, val = 0;
  
 +      mask = TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK |
 +              TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_MASK;
        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
        case SND_SOC_DAIFMT_NB_NF:
 +              val = TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
 +              if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK)
 +                      == SND_SOC_DAIFMT_DSP_A) {
 +                      val = TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE |
 +                              TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK;
 +              }
 +              break;
 +      case SND_SOC_DAIFMT_IB_NF:
 +              val = TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE;
 +              if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK)
 +                      == SND_SOC_DAIFMT_DSP_A) {
 +                      val = TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
 +              }
                break;
        default:
                return -EINVAL;
        }
 +      regmap_update_bits(i2s->regmap, TEGRA30_I2S_CH_CTRL, mask, val);
  
-       mask = TEGRA30_I2S_CTRL_MASTER_ENABLE;
+       mask |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
        case SND_SOC_DAIFMT_CBS_CFS:
-               val = TEGRA30_I2S_CTRL_MASTER_ENABLE;
+               val |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
                break;
        case SND_SOC_DAIFMT_CBM_CFM:
 +              val = 0;
                break;
        default:
                return -EINVAL;