Merge tag 'pinctrl-for-v3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
Linus Torvalds [Tue, 11 Dec 2012 19:21:33 +0000 (11:21 -0800)]
Pull pinctrl changes from Linus Walleij:
 "These are the first and major pinctrl changes for the v3.8 merge
  cycle.  Some of this is used as merge base for other trees so I better
  be early on the trigger.

  As can be seen from the diffstat the major changes are:

  - A big conversion of the AT91 pinctrl driver and the associated ACKed
    platform changes under arch/arm/max-at91 and its device trees.  This
    has been coordinated with the AT91 maintainers to go in through the
    pinctrl tree.

  - A larger chunk of changes to the SPEAr drivers and the addition of
    the "plgpio" driver for the SPEAr as well.

  - The removal of the remnants of the Nomadik driver from the arch/arm
    tree and fusion of that into the Nomadik driver and platform data
    header files.

  - Some local movement in the Marvell MVEBU drivers, these now have
    their own subdirectory.

  - The addition of a chunk of code to gpiolib under drivers/gpio to
    register gpio-to-pin range mappings from the GPIO side of things.
    This has been requested by Grant Likely and is now implemented, it
    is particularly useful for device tree work.

  Then we have incremental updates all over the place, many of these are
  cleanups and fixes from Axel Lin who has done a great job of removing
  minor mistakes and compilation annoyances."

* tag 'pinctrl-for-v3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (114 commits)
  ARM: mmp: select PINCTRL for ARCH_MMP
  pinctrl: Drop selecting PINCONF for MMP2, PXA168 and PXA910
  pinctrl: pinctrl-single: Fix error check condition
  pinctrl: SPEAr: Update error check for unsigned variables
  gpiolib: Fix use after free in gpiochip_add_pin_range
  gpiolib: rename pin range arguments
  pinctrl: single: support gpio request and free
  pinctrl: generic: add input schmitt disable parameter
  pinctrl/u300/coh901: stop spawning pinctrl from GPIO
  pinctrl/u300/coh901: let the gpio_chip register the range
  pinctrl: add function to retrieve range from pin
  gpiolib: return any error code from range creation
  pinctrl: make range registration defer properly
  gpiolib: rename find_pinctrl_*
  gpiolib: let gpiochip_add_pin_range() specify offset
  ARM: at91: pm9g45: add mmc support
  ARM: at91: Animeo IP: add mmc support
  ARM: at91: dt: add mmc pinctrl for Atmel reference boards
  ARM: at91: dt: at91sam9: add mmc pinctrl support
  ARM: at91/dts: add nodes for atmel hsmci controllers for atmel boards
  ...

126 files changed:
Documentation/devicetree/bindings/arm/atmel-at91.txt
Documentation/devicetree/bindings/gpio/gpio.txt
Documentation/devicetree/bindings/gpio/gpio_atmel.txt
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt [new file with mode: 0644]
Documentation/gpio.txt
Documentation/pinctrl.txt
MAINTAINERS
arch/arm/Kconfig
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/animeo_ip.dts [new file with mode: 0644]
arch/arm/boot/dts/at91rm9200.dtsi [new file with mode: 0644]
arch/arm/boot/dts/at91rm9200ek.dts [new file with mode: 0644]
arch/arm/boot/dts/at91sam9260.dtsi
arch/arm/boot/dts/at91sam9263.dtsi
arch/arm/boot/dts/at91sam9263ek.dts
arch/arm/boot/dts/at91sam9g15.dtsi [new file with mode: 0644]
arch/arm/boot/dts/at91sam9g15ek.dts [new file with mode: 0644]
arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
arch/arm/boot/dts/at91sam9g20ek_common.dtsi
arch/arm/boot/dts/at91sam9g25.dtsi [new file with mode: 0644]
arch/arm/boot/dts/at91sam9g25ek.dts
arch/arm/boot/dts/at91sam9g35.dtsi [new file with mode: 0644]
arch/arm/boot/dts/at91sam9g35ek.dts [new file with mode: 0644]
arch/arm/boot/dts/at91sam9g45.dtsi
arch/arm/boot/dts/at91sam9m10g45ek.dts
arch/arm/boot/dts/at91sam9n12.dtsi
arch/arm/boot/dts/at91sam9n12ek.dts
arch/arm/boot/dts/at91sam9x25.dtsi [new file with mode: 0644]
arch/arm/boot/dts/at91sam9x25ek.dts [new file with mode: 0644]
arch/arm/boot/dts/at91sam9x35.dtsi [new file with mode: 0644]
arch/arm/boot/dts/at91sam9x35ek.dts [new file with mode: 0644]
arch/arm/boot/dts/at91sam9x5.dtsi
arch/arm/boot/dts/at91sam9x5ek.dtsi [new file with mode: 0644]
arch/arm/boot/dts/pm9g45.dts [new file with mode: 0644]
arch/arm/boot/dts/spear1310-evb.dts
arch/arm/boot/dts/spear1310.dtsi
arch/arm/boot/dts/spear1340-evb.dts
arch/arm/boot/dts/spear1340.dtsi
arch/arm/boot/dts/spear310.dtsi
arch/arm/boot/dts/spear320-evb.dts
arch/arm/boot/dts/spear320.dtsi
arch/arm/configs/at91_dt_defconfig
arch/arm/mach-at91/Kconfig
arch/arm/mach-at91/Makefile
arch/arm/mach-at91/at91rm9200.c
arch/arm/mach-at91/at91rm9200_time.c
arch/arm/mach-at91/at91sam9260.c
arch/arm/mach-at91/at91sam9261.c
arch/arm/mach-at91/at91sam9263.c
arch/arm/mach-at91/at91sam9g45.c
arch/arm/mach-at91/at91sam9n12.c
arch/arm/mach-at91/at91sam9rl.c
arch/arm/mach-at91/at91sam9x5.c
arch/arm/mach-at91/board-dt.c
arch/arm/mach-at91/board-rm9200-dt.c [new file with mode: 0644]
arch/arm/mach-at91/generic.h
arch/arm/mach-at91/gpio.c
arch/arm/mach-at91/setup.c
arch/arm/mach-at91/soc.h
arch/arm/mach-nomadik/board-nhk8815.c
arch/arm/mach-nomadik/cpu-8815.c
arch/arm/mach-nomadik/i2c-8815nhk.c
arch/arm/mach-u300/core.c
arch/arm/mach-u300/include/mach/irqs.h
arch/arm/mach-ux500/board-mop500-audio.c
arch/arm/mach-ux500/board-mop500-pins.c
arch/arm/mach-ux500/board-mop500.c
arch/arm/mach-ux500/cpu-db8500.c
arch/arm/mach-ux500/devices-common.c
arch/arm/mach-ux500/devices-common.h
arch/arm/plat-nomadik/include/plat/gpio-nomadik.h [deleted file]
drivers/gpio/gpiolib-of.c
drivers/gpio/gpiolib.c
drivers/mtd/nand/atmel_nand.c
drivers/pinctrl/Kconfig
drivers/pinctrl/Makefile
drivers/pinctrl/core.c
drivers/pinctrl/core.h
drivers/pinctrl/devicetree.c
drivers/pinctrl/mvebu/Kconfig [new file with mode: 0644]
drivers/pinctrl/mvebu/Makefile [new file with mode: 0644]
drivers/pinctrl/mvebu/pinctrl-armada-370.c [moved from drivers/pinctrl/pinctrl-armada-370.c with 100% similarity]
drivers/pinctrl/mvebu/pinctrl-armada-xp.c [moved from drivers/pinctrl/pinctrl-armada-xp.c with 100% similarity]
drivers/pinctrl/mvebu/pinctrl-dove.c [moved from drivers/pinctrl/pinctrl-dove.c with 100% similarity]
drivers/pinctrl/mvebu/pinctrl-kirkwood.c [moved from drivers/pinctrl/pinctrl-kirkwood.c with 100% similarity]
drivers/pinctrl/mvebu/pinctrl-mvebu.c [moved from drivers/pinctrl/pinctrl-mvebu.c with 99% similarity]
drivers/pinctrl/mvebu/pinctrl-mvebu.h [moved from drivers/pinctrl/pinctrl-mvebu.h with 100% similarity]
drivers/pinctrl/pinconf-generic.c
drivers/pinctrl/pinctrl-at91.c [new file with mode: 0644]
drivers/pinctrl/pinctrl-bcm2835.c
drivers/pinctrl/pinctrl-coh901.c
drivers/pinctrl/pinctrl-exynos.c
drivers/pinctrl/pinctrl-falcon.c
drivers/pinctrl/pinctrl-imx.c
drivers/pinctrl/pinctrl-lantiq.c
drivers/pinctrl/pinctrl-mxs.c
drivers/pinctrl/pinctrl-nomadik-db8500.c
drivers/pinctrl/pinctrl-nomadik-db8540.c
drivers/pinctrl/pinctrl-nomadik.c
drivers/pinctrl/pinctrl-nomadik.h
drivers/pinctrl/pinctrl-pxa3xx.c
drivers/pinctrl/pinctrl-pxa3xx.h
drivers/pinctrl/pinctrl-single.c
drivers/pinctrl/pinctrl-sirf.c
drivers/pinctrl/pinctrl-tegra.c
drivers/pinctrl/pinctrl-u300.c
drivers/pinctrl/pinctrl-xway.c
drivers/pinctrl/pinmux.c
drivers/pinctrl/spear/Kconfig
drivers/pinctrl/spear/Makefile
drivers/pinctrl/spear/pinctrl-plgpio.c [new file with mode: 0644]
drivers/pinctrl/spear/pinctrl-spear.c
drivers/pinctrl/spear/pinctrl-spear.h
drivers/pinctrl/spear/pinctrl-spear1310.c
drivers/pinctrl/spear/pinctrl-spear1340.c
drivers/pinctrl/spear/pinctrl-spear300.c
drivers/pinctrl/spear/pinctrl-spear310.c
drivers/pinctrl/spear/pinctrl-spear320.c
drivers/pinctrl/spear/pinctrl-spear3xx.c
drivers/tty/serial/atmel_serial.c
include/asm-generic/gpio.h
include/linux/gpio.h
include/linux/pinctrl/pinconf-generic.h
include/linux/pinctrl/pinctrl.h
include/linux/platform_data/pinctrl-coh901.h
include/linux/platform_data/pinctrl-nomadik.h [moved from arch/arm/plat-nomadik/include/plat/pincfg.h with 66% similarity]

index d187e9f..1196290 100644 (file)
@@ -7,6 +7,12 @@ PIT Timer required properties:
 - interrupts: Should contain interrupt for the PIT which is the IRQ line
   shared across all System Controller members.
 
+System Timer (ST) required properties:
+- compatible: Should be "atmel,at91rm9200-st"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt for the ST which is the IRQ line
+  shared across all System Controller members.
+
 TC/TCLIB Timer required properties:
 - compatible: Should be "atmel,<chip>-tcb".
   <chip> can be "at91rm9200" or "at91sam9x5"
index 4e16ba4..a336287 100644 (file)
@@ -75,4 +75,40 @@ Example of two SOC GPIO banks defined as gpio-controller nodes:
                gpio-controller;
        };
 
+2.1) gpio-controller and pinctrl subsystem
+------------------------------------------
 
+gpio-controller on a SOC might be tightly coupled with the pinctrl
+subsystem, in the sense that the pins can be used by other functions
+together with optional gpio feature.
+
+While the pin allocation is totally managed by the pin ctrl subsystem,
+gpio (under gpiolib) is still maintained by gpio drivers. It may happen
+that different pin ranges in a SoC is managed by different gpio drivers.
+
+This makes it logical to let gpio drivers announce their pin ranges to
+the pin ctrl subsystem and call 'pinctrl_request_gpio' in order to
+request the corresponding pin before any gpio usage.
+
+For this, the gpio controller can use a pinctrl phandle and pins to
+announce the pinrange to the pin ctrl subsystem. For example,
+
+       qe_pio_e: gpio-controller@1460 {
+               #gpio-cells = <2>;
+               compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
+               reg = <0x1460 0x18>;
+               gpio-controller;
+               gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>;
+
+    }
+
+where,
+   &pinctrl1 and &pinctrl2 is the phandle to the pinctrl DT node.
+
+   Next values specify the base pin and number of pins for the range
+   handled by 'qe_pio_e' gpio. In the given example from base pin 20 to
+   pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled
+   by this gpio controller.
+
+The pinctrl node must have "#gpio-range-cells" property to show number of
+arguments to pass with phandle from gpio controllers node.
index 66efc80..85f8c0d 100644 (file)
@@ -9,6 +9,10 @@ Required properties:
   unused).
 - gpio-controller: Marks the device node as a GPIO controller.
 
+optional properties:
+- #gpio-lines: Number of gpio if absent 32.
+
+
 Example:
        pioA: gpio@fffff200 {
                compatible = "atmel,at91rm9200-gpio";
@@ -16,5 +20,6 @@ Example:
                interrupts = <2 4>;
                #gpio-cells = <2>;
                gpio-controller;
+               #gpio-lines = <19>;
        };
 
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
new file mode 100644 (file)
index 0000000..3a26812
--- /dev/null
@@ -0,0 +1,141 @@
+* Atmel AT91 Pinmux Controller
+
+The AT91 Pinmux Controler, enables the IC
+to share one PAD to several functional blocks. The sharing is done by
+multiplexing the PAD input/output signals. For each PAD there are up to
+8 muxing options (called periph modes). Since different modules require
+different PAD settings (like pull up, keeper, etc) the contoller controls
+also the PAD settings parameters.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Atmel AT91 pin configuration node is a node of a group of pins which can be
+used for a specific device or function. This node represents both mux and config
+of the pins in that group. The 'pins' selects the function mode(also named pin
+mode) this pin can work on and the 'config' configures various pad settings
+such as pull-up, multi drive, etc.
+
+Required properties for iomux controller:
+- compatible: "atmel,at91rm9200-pinctrl"
+- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
+  configured in this periph mode. All the periph and bank need to be describe.
+
+How to create such array:
+
+Each column will represent the possible peripheral of the pinctrl
+Each line will represent a pio bank
+
+Take an example on the 9260
+Peripheral: 2 ( A and B)
+Bank: 3 (A, B and C)
+=>
+
+  /*    A         B     */
+  0xffffffff 0xffc00c3b  /* pioA */
+  0xffffffff 0x7fff3ccf  /* pioB */
+  0xffffffff 0x007fffff  /* pioC */
+
+For each peripheral/bank we will descibe in a u32 if a pin can can be
+configured in it by putting 1 to the pin bit (1 << pin)
+
+Let's take the pioA on peripheral B
+From the datasheet Table 10-2.
+Peripheral B
+PA0    MCDB0
+PA1    MCCDB
+PA2
+PA3    MCDB3
+PA4    MCDB2
+PA5    MCDB1
+PA6
+PA7
+PA8
+PA9
+PA10   ETX2
+PA11   ETX3
+PA12
+PA13
+PA14
+PA15
+PA16
+PA17
+PA18
+PA19
+PA20
+PA21
+PA22   ETXER
+PA23   ETX2
+PA24   ETX3
+PA25   ERX2
+PA26   ERX3
+PA27   ERXCK
+PA28   ECRS
+PA29   ECOL
+PA30   RXD4
+PA31   TXD4
+
+=> 0xffc00c3b
+
+Required properties for pin configuration node:
+- atmel,pins: 4 integers array, represents a group of pins mux and config
+  setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
+  The PERIPH 0 means gpio.
+
+Bits used for CONFIG:
+PULL_UP                (1 << 0): indicate this pin need a pull up.
+MULTIDRIVE     (1 << 1): indicate this pin need to be configured as multidrive.
+DEGLITCH       (1 << 2): indicate this pin need deglitch.
+PULL_DOWN      (1 << 3): indicate this pin need a pull down.
+DIS_SCHMIT     (1 << 4): indicate this pin need to disable schmit trigger.
+DEBOUNCE       (1 << 16): indicate this pin need debounce.
+DEBOUNCE_VAL   (0x3fff << 17): debounce val.
+
+NOTE:
+Some requirements for using atmel,at91rm9200-pinctrl binding:
+1. We have pin function node defined under at91 controller node to represent
+   what pinmux functions this SoC supports.
+2. The driver can use the function node's name and pin configuration node's
+   name describe the pin function and group hierarchy.
+   For example, Linux at91 pinctrl driver takes the function node's name
+   as the function name and pin configuration node's name as group name to
+   create the map table.
+3. Each pin configuration node should have a phandle, devices can set pins
+   configurations by referring to the phandle of that pin configuration node.
+4. The gpio controller must be describe in the pinctrl simple-bus.
+
+Examples:
+
+pinctrl@fffff400 {
+       #address-cells = <1>;
+       #size-cells = <1>;
+       ranges;
+       compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+       reg = <0xfffff400 0x600>;
+
+       atmel,mux-mask = <
+             /*    A         B     */
+              0xffffffff 0xffc00c3b  /* pioA */
+              0xffffffff 0x7fff3ccf  /* pioB */
+              0xffffffff 0x007fffff  /* pioC */
+             >;
+
+       /* shared pinctrl settings */
+       dbgu {
+               pinctrl_dbgu: dbgu-0 {
+                       atmel,pins =
+                               <1 14 0x1 0x0   /* PB14 periph A */
+                                1 15 0x1 0x1>; /* PB15 periph with pullup */
+               };
+       };
+};
+
+dbgu: serial@fffff200 {
+       compatible = "atmel,at91sam9260-usart";
+       reg = <0xfffff200 0x200>;
+       interrupts = <1 4 7>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_dbgu>;
+       status = "disabled";
+};
index e08a883..77a1d11 100644 (file)
@@ -439,6 +439,48 @@ slower clock delays the rising edge of SCK, and the I2C master adjusts its
 signaling rate accordingly.
 
 
+GPIO controllers and the pinctrl subsystem
+------------------------------------------
+
+A GPIO controller on a SOC might be tightly coupled with the pinctrl
+subsystem, in the sense that the pins can be used by other functions
+together with an optional gpio feature. We have already covered the
+case where e.g. a GPIO controller need to reserve a pin or set the
+direction of a pin by calling any of:
+
+pinctrl_request_gpio()
+pinctrl_free_gpio()
+pinctrl_gpio_direction_input()
+pinctrl_gpio_direction_output()
+
+But how does the pin control subsystem cross-correlate the GPIO
+numbers (which are a global business) to a certain pin on a certain
+pin controller?
+
+This is done by registering "ranges" of pins, which are essentially
+cross-reference tables. These are described in
+Documentation/pinctrl.txt
+
+While the pin allocation is totally managed by the pinctrl subsystem,
+gpio (under gpiolib) is still maintained by gpio drivers. It may happen
+that different pin ranges in a SoC is managed by different gpio drivers.
+
+This makes it logical to let gpio drivers announce their pin ranges to
+the pin ctrl subsystem before it will call 'pinctrl_request_gpio' in order
+to request the corresponding pin to be prepared by the pinctrl subsystem
+before any gpio usage.
+
+For this, the gpio controller can register its pin range with pinctrl
+subsystem. There are two ways of doing it currently: with or without DT.
+
+For with DT support refer to Documentation/devicetree/bindings/gpio/gpio.txt.
+
+For non-DT support, user can call gpiochip_add_pin_range() with appropriate
+parameters to register a range of gpio pins with a pinctrl driver. For this
+exact name string of pinctrl device has to be passed as one of the
+argument to this routine.
+
+
 What do these conventions omit?
 ===============================
 One of the biggest things these conventions omit is pin multiplexing, since
index 3b4ee53..da40efb 100644 (file)
@@ -364,6 +364,9 @@ will get an pin number into its handled number range. Further it is also passed
 the range ID value, so that the pin controller knows which range it should
 deal with.
 
+Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
+section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
+pinctrl and gpio drivers.
 
 PINMUX interfaces
 =================
@@ -1193,4 +1196,6 @@ foo_switch()
        ...
 }
 
-The above has to be done from process context.
+The above has to be done from process context. The reservation of the pins
+will be done when the state is activated, so in effect one specific pin
+can be used by different functions at different times on a running system.
index 3d3abba..d02cdb5 100644 (file)
@@ -5689,6 +5689,12 @@ S:       Maintained
 F:     drivers/pinctrl/
 F:     include/linux/pinctrl/
 
+PIN CONTROLLER - ATMEL AT91
+M:     Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
+L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:     Maintained
+F:     drivers/pinctrl/pinctrl-at91.c
+
 PIN CONTROLLER - ST SPEAR
 M:     Viresh Kumar <viresh.linux@gmail.com>
 L:     spear-devel@list.st.com
index 9759fec..67f1fdb 100644 (file)
@@ -330,6 +330,8 @@ config ARCH_AT91
        select IRQ_DOMAIN
        select NEED_MACH_GPIO_H
        select NEED_MACH_IO_H if PCCARD
+       select PINCTRL
+       select PINCTRL_AT91 if USE_OF
        help
          This enables support for systems based on Atmel
          AT91RM9200 and AT91SAM9* processors.
@@ -587,6 +589,7 @@ config ARCH_MMP
        select GPIO_PXA
        select IRQ_DOMAIN
        select NEED_MACH_GPIO_H
+       select PINCTRL
        select PLAT_PXA
        select SPARSE_IRQ
        help
index f37cf9f..fb5b077 100644 (file)
@@ -1,21 +1,37 @@
 ifeq ($(CONFIG_OF),y)
 
-dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \
-       at91sam9263ek.dtb \
-       at91sam9g20ek_2mmc.dtb \
-       at91sam9g20ek.dtb \
-       at91sam9g25ek.dtb \
-       at91sam9m10g45ek.dtb \
-       at91sam9n12ek.dtb \
-       ethernut5.dtb \
-       evk-pro3.dtb \
-       kizbox.dtb \
-       tny_a9260.dtb \
-       tny_a9263.dtb \
-       tny_a9g20.dtb \
-       usb_a9260.dtb \
-       usb_a9263.dtb \
-       usb_a9g20.dtb
+# Keep at91 dtb files sorted alphabetically for each SoC
+# rm9200
+dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb
+# sam9260
+dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb
+dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb
+dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb
+dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb
+dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb
+dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb
+# sam9263
+dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
+dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb
+# sam9g20
+dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
+dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
+dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
+dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
+# sam9g45
+dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
+# sam9n12
+dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
+# sam9x5
+dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
+
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
        dove-cubox.dtb \
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
new file mode 100644 (file)
index 0000000..74d92cd
--- /dev/null
@@ -0,0 +1,178 @@
+/*
+ * animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards
+ *
+ *  Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 only.
+ */
+
+/dts-v1/;
+/include/ "at91sam9260.dtsi"
+
+/ {
+       model = "Somfy Animeo IP";
+       compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9";
+
+       aliases {
+               serial0 = &usart1;
+               serial1 = &usart2;
+               serial2 = &usart0;
+               serial3 = &dbgu;
+               serial4 = &usart3;
+               serial5 = &uart0;
+               serial6 = &uart1;
+       };
+
+       chosen {
+               linux,stdout-path = &usart2;
+       };
+
+       memory {
+               reg = <0x20000000 0x4000000>;
+       };
+
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               main_clock: clock@0 {
+                       compatible = "atmel,osc", "fixed-clock";
+                       clock-frequency = <18432000>;
+               };
+       };
+
+       ahb {
+               apb {
+                       usart0: serial@fffb0000 {
+                               pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts>;
+                               linux,rs485-enabled-at-boot-time;
+                               status = "okay";
+                       };
+
+                       usart1: serial@fffb4000 {
+                               pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts>;
+                               linux,rs485-enabled-at-boot-time;
+                               status = "okay";
+                       };
+
+                       usart2: serial@fffb8000 {
+                               pinctrl-0 = <&pinctrl_usart2>;
+                               status = "okay";
+                       };
+
+                       macb0: ethernet@fffc4000 {
+                               pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii>;
+                               phy-mode = "mii";
+                               status = "okay";
+                       };
+
+                       mmc0: mmc@fffa8000 {
+                               pinctrl-0 = <&pinctrl_mmc0_clk
+                                            &pinctrl_mmc0_slot1_cmd_dat0
+                                            &pinctrl_mmc0_slot1_dat1_3>;
+                               status = "okay";
+
+                               slot@1 {
+                                       reg = <1>;
+                                       bus-width = <4>;
+                               };
+                       };
+               };
+
+               nand0: nand@40000000 {
+                       nand-bus-width = <8>;
+                       nand-ecc-mode = "soft";
+                       nand-on-flash-bbt;
+                       status = "okay";
+
+                       at91bootstrap@0 {
+                               label = "at91bootstrap";
+                               reg = <0x0 0x8000>;
+                       };
+
+                       barebox@8000 {
+                               label = "barebox";
+                               reg = <0x8000 0x40000>;
+                       };
+
+                       bareboxenv@48000 {
+                               label = "bareboxenv";
+                               reg = <0x48000 0x8000>;
+                       };
+
+                       user_block@0x50000 {
+                               label = "user_block";
+                               reg = <0x50000 0xb0000>;
+                       };
+
+                       kernel@100000 {
+                               label = "kernel";
+                               reg = <0x100000 0x1b0000>;
+                       };
+
+                       root@2b0000 {
+                               label = "root";
+                               reg = <0x2b0000 0x1D50000>;
+                       };
+               };
+
+               usb0: ohci@00500000 {
+                       num-ports = <2>;
+                       atmel,vbus-gpio = <&pioB 15 1>;
+                       status = "okay";
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               power_green {
+                       label = "power_green";
+                       gpios = <&pioC 17 0>;
+                       linux,default-trigger = "heartbeat";
+               };
+
+               power_red {
+                       label = "power_red";
+                       gpios = <&pioA 2 0>;
+               };
+
+               tx_green {
+                       label = "tx_green";
+                       gpios = <&pioC 19 0>;
+               };
+
+               tx_red {
+                       label = "tx_red";
+                       gpios = <&pioC 18 0>;
+               };
+       };
+
+       gpio_keys {
+               compatible = "gpio-keys";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               keyswitch_in {
+                       label = "keyswitch_in";
+                       gpios = <&pioB 1 0>;
+                       linux,code = <28>;
+                       gpio-key,wakeup;
+               };
+
+               error_in {
+                       label = "error_in";
+                       gpios = <&pioB 2 0>;
+                       linux,code = <29>;
+                       gpio-key,wakeup;
+               };
+
+               btn {
+                       label = "btn";
+                       gpios = <&pioC 23 0>;
+                       linux,code = <31>;
+                       gpio-key,wakeup;
+               };
+       };
+};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
new file mode 100644 (file)
index 0000000..e154f24
--- /dev/null
@@ -0,0 +1,349 @@
+/*
+ * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
+ *
+ *  Copyright (C) 2011 Atmel,
+ *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
+ *                2012 Joachim Eastwood <manabian@gmail.com>
+ *
+ * Based on at91sam9260.dtsi
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+       model = "Atmel AT91RM9200 family SoC";
+       compatible = "atmel,at91rm9200";
+       interrupt-parent = <&aic>;
+
+       aliases {
+               serial0 = &dbgu;
+               serial1 = &usart0;
+               serial2 = &usart1;
+               serial3 = &usart2;
+               serial4 = &usart3;
+               gpio0 = &pioA;
+               gpio1 = &pioB;
+               gpio2 = &pioC;
+               gpio3 = &pioD;
+               tcb0 = &tcb0;
+               tcb1 = &tcb1;
+       };
+       cpus {
+               cpu@0 {
+                       compatible = "arm,arm920t";
+               };
+       };
+
+       memory {
+               reg = <0x20000000 0x04000000>;
+       };
+
+       ahb {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               apb {
+                       compatible = "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       aic: interrupt-controller@fffff000 {
+                               #interrupt-cells = <3>;
+                               compatible = "atmel,at91rm9200-aic";
+                               interrupt-controller;
+                               reg = <0xfffff000 0x200>;
+                               atmel,external-irqs = <25 26 27 28 29 30 31>;
+                       };
+
+                       ramc0: ramc@ffffff00 {
+                               compatible = "atmel,at91rm9200-sdramc";
+                               reg = <0xffffff00 0x100>;
+                       };
+
+                       pmc: pmc@fffffc00 {
+                               compatible = "atmel,at91rm9200-pmc";
+                               reg = <0xfffffc00 0x100>;
+                       };
+
+                       st: timer@fffffd00 {
+                               compatible = "atmel,at91rm9200-st";
+                               reg = <0xfffffd00 0x100>;
+                               interrupts = <1 4 7>;
+                       };
+
+                       tcb0: timer@fffa0000 {
+                               compatible = "atmel,at91rm9200-tcb";
+                               reg = <0xfffa0000 0x100>;
+                               interrupts = <17 4 0 18 4 0 19 4 0>;
+                       };
+
+                       tcb1: timer@fffa4000 {
+                               compatible = "atmel,at91rm9200-tcb";
+                               reg = <0xfffa4000 0x100>;
+                               interrupts = <20 4 0 21 4 0 22 4 0>;
+                       };
+
+                       pinctrl@fffff400 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+                               ranges = <0xfffff400 0xfffff400 0x800>;
+
+                               atmel,mux-mask = <
+                                       /*    A         B     */
+                                        0xffffffff 0xffffffff  /* pioA */
+                                        0xffffffff 0x083fffff  /* pioB */
+                                        0xffff3fff 0x00000000  /* pioC */
+                                        0x03ff87ff 0x0fffff80  /* pioD */
+                                       >;
+
+                               /* shared pinctrl settings */
+                               dbgu {
+                                       pinctrl_dbgu: dbgu-0 {
+                                               atmel,pins =
+                                                       <0 30 0x1 0x0   /* PA30 periph A */
+                                                        0 31 0x1 0x1>; /* PA31 periph with pullup */
+                                       };
+                               };
+
+                               uart0 {
+                                       pinctrl_uart0: uart0-0 {
+                                               atmel,pins =
+                                                       <0 17 0x1 0x0   /* PA17 periph A */
+                                                        0 18 0x1 0x0>; /* PA18 periph A */
+                                       };
+
+                                       pinctrl_uart0_rts: uart0_rts-0 {
+                                               atmel,pins =
+                                                       <0 20 0x1 0x0>; /* PA20 periph A */
+                                       };
+
+                                       pinctrl_uart0_cts: uart0_cts-0 {
+                                               atmel,pins =
+                                                       <0 21 0x1 0x0>; /* PA21 periph A */
+                                       };
+                               };
+
+                               uart1 {
+                                       pinctrl_uart1: uart1-0 {
+                                               atmel,pins =
+                                                       <1 20 0x1 0x1   /* PB20 periph A with pullup */
+                                                        1 21 0x1 0x0>; /* PB21 periph A */
+                                       };
+
+                                       pinctrl_uart1_rts: uart1_rts-0 {
+                                               atmel,pins =
+                                                       <1 24 0x1 0x0>; /* PB24 periph A */
+                                       };
+
+                                       pinctrl_uart1_cts: uart1_cts-0 {
+                                               atmel,pins =
+                                                       <1 26 0x1 0x0>; /* PB26 periph A */
+                                       };
+
+                                       pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
+                                               atmel,pins =
+                                                       <1 19 0x1 0x0   /* PB19 periph A */
+                                                        1 25 0x1 0x0>; /* PB25 periph A */
+                                       };
+
+                                       pinctrl_uart1_dcd: uart1_dcd-0 {
+                                               atmel,pins =
+                                                       <1 23 0x1 0x0>; /* PB23 periph A */
+                                       };
+
+                                       pinctrl_uart1_ri: uart1_ri-0 {
+                                               atmel,pins =
+                                                       <1 18 0x1 0x0>; /* PB18 periph A */
+                                       };
+                               };
+
+                               uart2 {
+                                       pinctrl_uart2: uart2-0 {
+                                               atmel,pins =
+                                                       <0 22 0x1 0x0   /* PA22 periph A */
+                                                        0 23 0x1 0x1>; /* PA23 periph A with pullup */
+                                       };
+
+                                       pinctrl_uart2_rts: uart2_rts-0 {
+                                               atmel,pins =
+                                                       <0 30 0x2 0x0>; /* PA30 periph B */
+                                       };
+
+                                       pinctrl_uart2_cts: uart2_cts-0 {
+                                               atmel,pins =
+                                                       <0 31 0x2 0x0>; /* PA31 periph B */
+                                       };
+                               };
+
+                               uart3 {
+                                       pinctrl_uart3: uart3-0 {
+                                               atmel,pins =
+                                                       <0 5 0x2 0x1    /* PA5 periph B with pullup */
+                                                        0 6 0x2 0x0>;  /* PA6 periph B */
+                                       };
+
+                                       pinctrl_uart3_rts: uart3_rts-0 {
+                                               atmel,pins =
+                                                       <1 0 0x2 0x0>;  /* PB0 periph B */
+                                       };
+
+                                       pinctrl_uart3_cts: uart3_cts-0 {
+                                               atmel,pins =
+                                                       <1 1 0x2 0x0>;  /* PB1 periph B */
+                                       };
+                               };
+
+                               nand {
+                                       pinctrl_nand: nand-0 {
+                                               atmel,pins =
+                                                       <2 2 0x0 0x1    /* PC2 gpio RDY pin pull_up */
+                                                        1 1 0x0 0x1>;  /* PB1 gpio CD pin pull_up */
+                                       };
+                               };
+
+                               pioA: gpio@fffff400 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff400 0x200>;
+                                       interrupts = <2 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioB: gpio@fffff600 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff600 0x200>;
+                                       interrupts = <3 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioC: gpio@fffff800 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff800 0x200>;
+                                       interrupts = <4 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioD: gpio@fffffa00 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffffa00 0x200>;
+                                       interrupts = <5 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+                       };
+
+                       dbgu: serial@fffff200 {
+                               compatible = "atmel,at91rm9200-usart";
+                               reg = <0xfffff200 0x200>;
+                               interrupts = <1 4 7>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_dbgu>;
+                               status = "disabled";
+                       };
+
+                       usart0: serial@fffc0000 {
+                               compatible = "atmel,at91rm9200-usart";
+                               reg = <0xfffc0000 0x200>;
+                               interrupts = <6 4 5>;
+                               atmel,use-dma-rx;
+                               atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_uart0>;
+                               status = "disabled";
+                       };
+
+                       usart1: serial@fffc4000 {
+                               compatible = "atmel,at91rm9200-usart";
+                               reg = <0xfffc4000 0x200>;
+                               interrupts = <7 4 5>;
+                               atmel,use-dma-rx;
+                               atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_uart1>;
+                               status = "disabled";
+                       };
+
+                       usart2: serial@fffc8000 {
+                               compatible = "atmel,at91rm9200-usart";
+                               reg = <0xfffc8000 0x200>;
+                               interrupts = <8 4 5>;
+                               atmel,use-dma-rx;
+                               atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_uart2>;
+                               status = "disabled";
+                       };
+
+                       usart3: serial@fffcc000 {
+                               compatible = "atmel,at91rm9200-usart";
+                               reg = <0xfffcc000 0x200>;
+                               interrupts = <23 4 5>;
+                               atmel,use-dma-rx;
+                               atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_uart3>;
+                               status = "disabled";
+                       };
+
+                       usb1: gadget@fffb0000 {
+                               compatible = "atmel,at91rm9200-udc";
+                               reg = <0xfffb0000 0x4000>;
+                               interrupts = <11 4 2>;
+                               status = "disabled";
+                       };
+               };
+
+               nand0: nand@40000000 {
+                       compatible = "atmel,at91rm9200-nand";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x40000000 0x10000000>;
+                       atmel,nand-addr-offset = <21>;
+                       atmel,nand-cmd-offset = <22>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_nand>;
+                       nand-ecc-mode = "soft";
+                       gpios = <&pioC 2 0
+                                0
+                                &pioB 1 0
+                               >;
+                       status = "disabled";
+               };
+
+               usb0: ohci@00300000 {
+                       compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                       reg = <0x00300000 0x100000>;
+                       interrupts = <23 4 2>;
+                       status = "disabled";
+               };
+       };
+
+       i2c@0 {
+               compatible = "i2c-gpio";
+               gpios = <&pioA 23 0 /* sda */
+                        &pioA 24 0 /* scl */
+                       >;
+               i2c-gpio,sda-open-drain;
+               i2c-gpio,scl-open-drain;
+               i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+};
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
new file mode 100644 (file)
index 0000000..8aa4893
--- /dev/null
@@ -0,0 +1,79 @@
+/*
+ * at91rm9200ek.dts - Device Tree file for Atmel AT91RM9200 evaluation kit
+ *
+ *  Copyright (C) 2012 Joachim Eastwood <manabian@gmail.com>
+ *
+ * Licensed under GPLv2 only
+ */
+/dts-v1/;
+/include/ "at91rm9200.dtsi"
+
+/ {
+       model = "Atmel AT91RM9200 evaluation kit";
+       compatible = "atmel,at91rm9200ek", "atmel,at91rm9200";
+
+       memory {
+               reg = <0x20000000 0x4000000>;
+       };
+
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               main_clock: clock@0 {
+                       compatible = "atmel,osc", "fixed-clock";
+                       clock-frequency = <18432000>;
+               };
+       };
+
+       ahb {
+               apb {
+                       dbgu: serial@fffff200 {
+                               status = "okay";
+                       };
+
+                       usart1: serial@fffc4000 {
+                               pinctrl-0 =
+                                               <&pinctrl_uart1
+                                                &pinctrl_uart1_rts
+                                                &pinctrl_uart1_cts
+                                                &pinctrl_uart1_dtr_dsr
+                                                &pinctrl_uart1_dcd
+                                                &pinctrl_uart1_ri>;
+                               status = "okay";
+                       };
+
+                       usb1: gadget@fffb0000 {
+                               atmel,vbus-gpio = <&pioD 4 0>;
+                               status = "okay";
+                       };
+               };
+
+               usb0: ohci@00300000 {
+                       num-ports = <2>;
+                       status = "okay";
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               ds2 {
+                       label = "green";
+                       gpios = <&pioB 0 0x1>;
+                       linux,default-trigger = "mmc0";
+               };
+
+               ds4 {
+                       label = "yellow";
+                       gpios = <&pioB 1 0x1>;
+                       linux,default-trigger = "heartbeat";
+               };
+
+               ds6 {
+                       label = "red";
+                       gpios = <&pioB 2 0x1>;
+               };
+       };
+};
index d410581..b1d3fab 100644 (file)
@@ -21,8 +21,8 @@
                serial2 = &usart1;
                serial3 = &usart2;
                serial4 = &usart3;
-               serial5 = &usart4;
-               serial6 = &usart5;
+               serial5 = &uart0;
+               serial6 = &uart1;
                gpio0 = &pioA;
                gpio1 = &pioB;
                gpio2 = &pioC;
                                interrupts = <26 4 0 27 4 0 28 4 0>;
                        };
 
-                       pioA: gpio@fffff400 {
-                               compatible = "atmel,at91rm9200-gpio";
-                               reg = <0xfffff400 0x100>;
-                               interrupts = <2 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                       };
+                       pinctrl@fffff400 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+                               ranges = <0xfffff400 0xfffff400 0x600>;
+
+                               atmel,mux-mask = <
+                                     /*    A         B     */
+                                      0xffffffff 0xffc00c3b  /* pioA */
+                                      0xffffffff 0x7fff3ccf  /* pioB */
+                                      0xffffffff 0x007fffff  /* pioC */
+                                     >;
+
+                               /* shared pinctrl settings */
+                               dbgu {
+                                       pinctrl_dbgu: dbgu-0 {
+                                               atmel,pins =
+                                                       <1 14 0x1 0x0   /* PB14 periph A */
+                                                        1 15 0x1 0x1>; /* PB15 periph with pullup */
+                                       };
+                               };
 
-                       pioB: gpio@fffff600 {
-                               compatible = "atmel,at91rm9200-gpio";
-                               reg = <0xfffff600 0x100>;
-                               interrupts = <3 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                       };
+                               usart0 {
+                                       pinctrl_usart0: usart0-0 {
+                                               atmel,pins =
+                                                       <1 4 0x1 0x0    /* PB4 periph A */
+                                                        1 5 0x1 0x0>;  /* PB5 periph A */
+                                       };
+
+                                       pinctrl_usart0_rts: usart0_rts-0 {
+                                               atmel,pins =
+                                                       <1 26 0x1 0x0>; /* PB26 periph A */
+                                       };
+
+                                       pinctrl_usart0_cts: usart0_cts-0 {
+                                               atmel,pins =
+                                                       <1 27 0x1 0x0>; /* PB27 periph A */
+                                       };
+
+                                       pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
+                                               atmel,pins =
+                                                       <1 24 0x1 0x0   /* PB24 periph A */
+                                                        1 22 0x1 0x0>; /* PB22 periph A */
+                                       };
+
+                                       pinctrl_usart0_dcd: usart0_dcd-0 {
+                                               atmel,pins =
+                                                       <1 23 0x1 0x0>; /* PB23 periph A */
+                                       };
+
+                                       pinctrl_usart0_ri: usart0_ri-0 {
+                                               atmel,pins =
+                                                       <1 25 0x1 0x0>; /* PB25 periph A */
+                                       };
+                               };
 
-                       pioC: gpio@fffff800 {
-                               compatible = "atmel,at91rm9200-gpio";
-                               reg = <0xfffff800 0x100>;
-                               interrupts = <4 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
+                               usart1 {
+                                       pinctrl_usart1: usart1-0 {
+                                               atmel,pins =
+                                                       <2 6 0x1 0x1    /* PB6 periph A with pullup */
+                                                        2 7 0x1 0x0>;  /* PB7 periph A */
+                                       };
+
+                                       pinctrl_usart1_rts: usart1_rts-0 {
+                                               atmel,pins =
+                                                       <1 28 0x1 0x0>; /* PB28 periph A */
+                                       };
+
+                                       pinctrl_usart1_cts: usart1_cts-0 {
+                                               atmel,pins =
+                                                       <1 29 0x1 0x0>; /* PB29 periph A */
+                                       };
+                               };
+
+                               usart2 {
+                                       pinctrl_usart2: usart2-0 {
+                                               atmel,pins =
+                                                       <1 8 0x1 0x1    /* PB8 periph A with pullup */
+                                                        1 9 0x1 0x0>;  /* PB9 periph A */
+                                       };
+
+                                       pinctrl_usart2_rts: usart2_rts-0 {
+                                               atmel,pins =
+                                                       <0 4 0x1 0x0>;  /* PA4 periph A */
+                                       };
+
+                                       pinctrl_usart2_cts: usart2_cts-0 {
+                                               atmel,pins =
+                                                       <0 5 0x1 0x0>;  /* PA5 periph A */
+                                       };
+                               };
+
+                               usart3 {
+                                       pinctrl_usart3: usart3-0 {
+                                               atmel,pins =
+                                                       <2 10 0x1 0x1   /* PB10 periph A with pullup */
+                                                        2 11 0x1 0x0>; /* PB11 periph A */
+                                       };
+
+                                       pinctrl_usart3_rts: usart3_rts-0 {
+                                               atmel,pins =
+                                                       <3 8 0x2 0x0>;  /* PB8 periph B */
+                                       };
+
+                                       pinctrl_usart3_cts: usart3_cts-0 {
+                                               atmel,pins =
+                                                       <3 10 0x2 0x0>; /* PB10 periph B */
+                                       };
+                               };
+
+                               uart0 {
+                                       pinctrl_uart0: uart0-0 {
+                                               atmel,pins =
+                                                       <0 31 0x2 0x1   /* PA31 periph B with pullup */
+                                                        0 30 0x2 0x0>; /* PA30 periph B */
+                                       };
+                               };
+
+                               uart1 {
+                                       pinctrl_uart1: uart1-0 {
+                                               atmel,pins =
+                                                       <2 12 0x1 0x1   /* PB12 periph A with pullup */
+                                                        2 13 0x1 0x0>; /* PB13 periph A */
+                                       };
+                               };
+
+                               nand {
+                                       pinctrl_nand: nand-0 {
+                                               atmel,pins =
+                                                       <2 13 0x0 0x1   /* PC13 gpio RDY pin pull_up */
+                                                        2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
+                                       };
+                               };
+
+                               macb {
+                                       pinctrl_macb_rmii: macb_rmii-0 {
+                                               atmel,pins =
+                                                       <0 12 0x1 0x0   /* PA12 periph A */
+                                                        0 13 0x1 0x0   /* PA13 periph A */
+                                                        0 14 0x1 0x0   /* PA14 periph A */
+                                                        0 15 0x1 0x0   /* PA15 periph A */
+                                                        0 16 0x1 0x0   /* PA16 periph A */
+                                                        0 17 0x1 0x0   /* PA17 periph A */
+                                                        0 18 0x1 0x0   /* PA18 periph A */
+                                                        0 19 0x1 0x0   /* PA19 periph A */
+                                                        0 20 0x1 0x0   /* PA20 periph A */
+                                                        0 21 0x1 0x0>; /* PA21 periph A */
+                                       };
+
+                                       pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+                                               atmel,pins =
+                                                       <0 22 0x2 0x0   /* PA22 periph B */
+                                                        0 23 0x2 0x0   /* PA23 periph B */
+                                                        0 24 0x2 0x0   /* PA24 periph B */
+                                                        0 25 0x2 0x0   /* PA25 periph B */
+                                                        0 26 0x2 0x0   /* PA26 periph B */
+                                                        0 27 0x2 0x0   /* PA27 periph B */
+                                                        0 28 0x2 0x0   /* PA28 periph B */
+                                                        0 29 0x2 0x0>; /* PA29 periph B */
+                                       };
+
+                                       pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
+                                               atmel,pins =
+                                                       <0 10 0x2 0x0   /* PA10 periph B */
+                                                        0 11 0x2 0x0   /* PA11 periph B */
+                                                        0 24 0x2 0x0   /* PA24 periph B */
+                                                        0 25 0x2 0x0   /* PA25 periph B */
+                                                        0 26 0x2 0x0   /* PA26 periph B */
+                                                        0 27 0x2 0x0   /* PA27 periph B */
+                                                        0 28 0x2 0x0   /* PA28 periph B */
+                                                        0 29 0x2 0x0>; /* PA29 periph B */
+                                       };
+                               };
+
+                               mmc0 {
+                                       pinctrl_mmc0_clk: mmc0_clk-0 {
+                                               atmel,pins =
+                                                       <0 8 0x1 0x0>;  /* PA8 periph A */
+                                       };
+
+                                       pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
+                                               atmel,pins =
+                                                       <0 7 0x1 0x1    /* PA7 periph A with pullup */
+                                                        0 6 0x1 0x1>;  /* PA6 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+                                               atmel,pins =
+                                                       <0 9 0x1 0x1    /* PA9 periph A with pullup */
+                                                        0 10 0x1 0x1   /* PA10 periph A with pullup */
+                                                        0 11 0x1 0x1>; /* PA11 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
+                                               atmel,pins =
+                                                       <0 1 0x2 0x1    /* PA1 periph B with pullup */
+                                                        0 0 0x2 0x1>;  /* PA0 periph B with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
+                                               atmel,pins =
+                                                       <0 5 0x2 0x1    /* PA5 periph B with pullup */
+                                                        0 4 0x2 0x1    /* PA4 periph B with pullup */
+                                                        0 3 0x2 0x1>;  /* PA3 periph B with pullup */
+                                       };
+                               };
+
+                               pioA: gpio@fffff400 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff400 0x200>;
+                                       interrupts = <2 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioB: gpio@fffff600 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff600 0x200>;
+                                       interrupts = <3 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioC: gpio@fffff800 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff800 0x200>;
+                                       interrupts = <4 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
                        };
 
                        dbgu: serial@fffff200 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffff200 0x200>;
                                interrupts = <1 4 7>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
                        };
 
                                interrupts = <6 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
                        };
 
                                interrupts = <7 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
                        };
 
                                interrupts = <8 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
                        };
 
                                interrupts = <23 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart3>;
                                status = "disabled";
                        };
 
-                       usart4: serial@fffd4000 {
+                       uart0: serial@fffd4000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffd4000 0x200>;
                                interrupts = <24 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_uart0>;
                                status = "disabled";
                        };
 
-                       usart5: serial@fffd8000 {
+                       uart1: serial@fffd8000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffd8000 0x200>;
                                interrupts = <25 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_uart1>;
                                status = "disabled";
                        };
 
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xfffc4000 0x100>;
                                interrupts = <21 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_macb_rmii>;
                                status = "disabled";
                        };
 
                                status = "disabled";
                        };
 
+                       mmc0: mmc@fffa8000 {
+                               compatible = "atmel,hsmci";
+                               reg = <0xfffa8000 0x600>;
+                               interrupts = <9 4 0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
                        adc0: adc@fffe0000 {
                                compatible = "atmel,at91sam9260-adc";
                                reg = <0xfffe0000 0x100>;
                              >;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_nand>;
                        gpios = <&pioC 13 0
                                 &pioC 14 0
                                 0
index 3e6e5c1..66106ee 100644 (file)
                                reg = <0xfffffd10 0x10>;
                        };
 
-                       pioA: gpio@fffff200 {
-                               compatible = "atmel,at91rm9200-gpio";
-                               reg = <0xfffff200 0x100>;
-                               interrupts = <2 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                       };
+                       pinctrl@fffff200 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+                               ranges = <0xfffff200 0xfffff200 0xa00>;
 
-                       pioB: gpio@fffff400 {
-                               compatible = "atmel,at91rm9200-gpio";
-                               reg = <0xfffff400 0x100>;
-                               interrupts = <3 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                       };
+                               atmel,mux-mask = <
+                                     /*    A         B     */
+                                      0xfffffffb 0xffffe07f  /* pioA */
+                                      0x0007ffff 0x39072fff  /* pioB */
+                                      0xffffffff 0x3ffffff8  /* pioC */
+                                      0xfffffbff 0xffffffff  /* pioD */
+                                      0xffe00fff 0xfbfcff00  /* pioE */
+                                     >;
 
-                       pioC: gpio@fffff600 {
-                               compatible = "atmel,at91rm9200-gpio";
-                               reg = <0xfffff600 0x100>;
-                               interrupts = <4 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                       };
+                               /* shared pinctrl settings */
+                               dbgu {
+                                       pinctrl_dbgu: dbgu-0 {
+                                               atmel,pins =
+                                                       <2 30 0x1 0x0   /* PC30 periph A */
+                                                        2 31 0x1 0x1>; /* PC31 periph with pullup */
+                                       };
+                               };
 
-                       pioD: gpio@fffff800 {
-                               compatible = "atmel,at91rm9200-gpio";
-                               reg = <0xfffff800 0x100>;
-                               interrupts = <4 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                       };
+                               usart0 {
+                                       pinctrl_usart0: usart0-0 {
+                                               atmel,pins =
+                                                       <0 26 0x1 0x1   /* PA26 periph A with pullup */
+                                                        0 27 0x1 0x0>; /* PA27 periph A */
+                                       };
 
-                       pioE: gpio@fffffa00 {
-                               compatible = "atmel,at91rm9200-gpio";
-                               reg = <0xfffffa00 0x100>;
-                               interrupts = <4 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
+                                       pinctrl_usart0_rts: usart0_rts-0 {
+                                               atmel,pins =
+                                                       <0 28 0x1 0x0>; /* PA28 periph A */
+                                       };
+
+                                       pinctrl_usart0_cts: usart0_cts-0 {
+                                               atmel,pins =
+                                                       <0 29 0x1 0x0>; /* PA29 periph A */
+                                       };
+                               };
+
+                               usart1 {
+                                       pinctrl_usart1: usart1-0 {
+                                               atmel,pins =
+                                                       <3 0 0x1 0x1    /* PD0 periph A with pullup */
+                                                        3 1 0x1 0x0>;  /* PD1 periph A */
+                                       };
+
+                                       pinctrl_usart1_rts: usart1_rts-0 {
+                                               atmel,pins =
+                                                       <3 7 0x2 0x0>;  /* PD7 periph B */
+                                       };
+
+                                       pinctrl_usart1_cts: usart1_cts-0 {
+                                               atmel,pins =
+                                                       <3 8 0x2 0x0>;  /* PD8 periph B */
+                                       };
+                               };
+
+                               usart2 {
+                                       pinctrl_usart2: usart2-0 {
+                                               atmel,pins =
+                                                       <3 2 0x1 0x1    /* PD2 periph A with pullup */
+                                                        3 3 0x1 0x0>;  /* PD3 periph A */
+                                       };
+
+                                       pinctrl_usart2_rts: usart2_rts-0 {
+                                               atmel,pins =
+                                                       <3 5 0x2 0x0>;  /* PD5 periph B */
+                                       };
+
+                                       pinctrl_usart2_cts: usart2_cts-0 {
+                                               atmel,pins =
+                                                       <4 6 0x2 0x0>;  /* PD6 periph B */
+                                       };
+                               };
+
+                               nand {
+                                       pinctrl_nand: nand-0 {
+                                               atmel,pins =
+                                                       <0 22 0x0 0x1   /* PA22 gpio RDY pin pull_up*/
+                                                        3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
+                                       };
+                               };
+
+                               macb {
+                                       pinctrl_macb_rmii: macb_rmii-0 {
+                                               atmel,pins =
+                                                       <2 25 0x2 0x0   /* PC25 periph B */
+                                                        4 21 0x1 0x0   /* PE21 periph A */
+                                                        4 23 0x1 0x0   /* PE23 periph A */
+                                                        4 24 0x1 0x0   /* PE24 periph A */
+                                                        4 25 0x1 0x0   /* PE25 periph A */
+                                                        4 26 0x1 0x0   /* PE26 periph A */
+                                                        4 27 0x1 0x0   /* PE27 periph A */
+                                                        4 28 0x1 0x0   /* PE28 periph A */
+                                                        4 29 0x1 0x0   /* PE29 periph A */
+                                                        4 30 0x1 0x0>; /* PE30 periph A */
+                                       };
+
+                                       pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+                                               atmel,pins =
+                                                       <2 20 0x2 0x0   /* PC20 periph B */
+                                                        2 21 0x2 0x0   /* PC21 periph B */
+                                                        2 22 0x2 0x0   /* PC22 periph B */
+                                                        2 23 0x2 0x0   /* PC23 periph B */
+                                                        2 24 0x2 0x0   /* PC24 periph B */
+                                                        2 25 0x2 0x0   /* PC25 periph B */
+                                                        2 27 0x2 0x0   /* PC27 periph B */
+                                                        4 22 0x2 0x0>; /* PE22 periph B */
+                                       };
+                               };
+
+                               mmc0 {
+                                       pinctrl_mmc0_clk: mmc0_clk-0 {
+                                               atmel,pins =
+                                                       <0 12 0x1 0x0>; /* PA12 periph A */
+                                       };
+
+                                       pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
+                                               atmel,pins =
+                                                       <0 1 0x1 0x1    /* PA1 periph A with pullup */
+                                                        0 0 0x1 0x1>;  /* PA0 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+                                               atmel,pins =
+                                                       <0 3 0x1 0x1    /* PA3 periph A with pullup */
+                                                        0 4 0x1 0x1    /* PA4 periph A with pullup */
+                                                        0 5 0x1 0x1>;  /* PA5 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
+                                               atmel,pins =
+                                                       <0 16 0x1 0x1   /* PA16 periph A with pullup */
+                                                        0 17 0x1 0x1>; /* PA17 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
+                                               atmel,pins =
+                                                       <0 18 0x1 0x1   /* PA18 periph A with pullup */
+                                                        0 19 0x1 0x1   /* PA19 periph A with pullup */
+                                                        0 20 0x1 0x1>; /* PA20 periph A with pullup */
+                                       };
+                               };
+
+                               mmc1 {
+                                       pinctrl_mmc1_clk: mmc1_clk-0 {
+                                               atmel,pins =
+                                                       <0 6 0x1 0x0>;  /* PA6 periph A */
+                                       };
+
+                                       pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
+                                               atmel,pins =
+                                                       <0 7 0x1 0x1    /* PA7 periph A with pullup */
+                                                        0 8 0x1 0x1>;  /* PA8 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
+                                               atmel,pins =
+                                                       <0 9 0x1 0x1    /* PA9 periph A with pullup */
+                                                        0 10 0x1 0x1   /* PA10 periph A with pullup */
+                                                        0 11 0x1 0x1>; /* PA11 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
+                                               atmel,pins =
+                                                       <0 21 0x1 0x1   /* PA21 periph A with pullup */
+                                                        0 22 0x1 0x1>; /* PA22 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
+                                               atmel,pins =
+                                                       <0 23 0x1 0x1   /* PA23 periph A with pullup */
+                                                        0 24 0x1 0x1   /* PA24 periph A with pullup */
+                                                        0 25 0x1 0x1>; /* PA25 periph A with pullup */
+                                       };
+                               };
+
+                               pioA: gpio@fffff200 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff200 0x200>;
+                                       interrupts = <2 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioB: gpio@fffff400 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff400 0x200>;
+                                       interrupts = <3 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioC: gpio@fffff600 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff600 0x200>;
+                                       interrupts = <4 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioD: gpio@fffff800 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff800 0x200>;
+                                       interrupts = <4 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioE: gpio@fffffa00 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffffa00 0x200>;
+                                       interrupts = <4 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
                        };
 
                        dbgu: serial@ffffee00 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xffffee00 0x200>;
                                interrupts = <1 4 7>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
                        };
 
                                interrupts = <7 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
                        };
 
                                interrupts = <8 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
                        };
 
                                interrupts = <9 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
                        };
 
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xfffbc000 0x100>;
                                interrupts = <21 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_macb_rmii>;
                                status = "disabled";
                        };
 
                                #size-cells = <0>;
                                status = "disabled";
                        };
+
+                       mmc0: mmc@fff80000 {
+                               compatible = "atmel,hsmci";
+                               reg = <0xfff80000 0x600>;
+                               interrupts = <10 4 0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       mmc1: mmc@fff84000 {
+                               compatible = "atmel,hsmci";
+                               reg = <0xfff84000 0x600>;
+                               interrupts = <11 4 0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
                };
 
                nand0: nand@40000000 {
                              >;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_nand>;
                        gpios = <&pioA 22 0
                                 &pioD 15 0
                                 0
index f86ac4b..1eb0872 100644 (file)
                        };
 
                        usart0: serial@fff8c000 {
+                               pinctrl-0 = <
+                                       &pinctrl_usart0
+                                       &pinctrl_usart0_rts
+                                       &pinctrl_usart0_cts>;
                                status = "okay";
                        };
 
                                atmel,vbus-gpio = <&pioA 25 0>;
                                status = "okay";
                        };
+
+                       mmc0: mmc@fff80000 {
+                               pinctrl-0 = <
+                                       &pinctrl_board_mmc0
+                                       &pinctrl_mmc0_clk
+                                       &pinctrl_mmc0_slot0_cmd_dat0
+                                       &pinctrl_mmc0_slot0_dat1_3>;
+                               status = "okay";
+                               slot@0 {
+                                       reg = <0>;
+                                       bus-width = <4>;
+                                       cd-gpios = <&pioE 18 0>;
+                                       wp-gpios = <&pioE 19 0>;
+                               };
+                       };
+
+                       pinctrl@fffff200 {
+                               mmc0 {
+                                       pinctrl_board_mmc0: mmc0-board {
+                                               atmel,pins =
+                                                       <5 18 0x0 0x5   /* PE18 gpio CD pin pull up and deglitch */
+                                                        5 19 0x0 0x1>; /* PE19 gpio WP pin pull up */
+                                       };
+                               };
+                       };
                };
 
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
new file mode 100644 (file)
index 0000000..fbe7a70
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/include/ "at91sam9x5.dtsi"
+
+/ {
+       model = "Atmel AT91SAM9G15 SoC";
+       compatible = "atmel, at91sam9g15, atmel,at91sam9x5";
+
+       ahb {
+               apb {
+                       pinctrl@fffff400 {
+                               atmel,mux-mask = <
+                                     /*    A         B          C     */
+                                      0xffffffff 0xffe0399f 0x00000000  /* pioA */
+                                      0x00040000 0x00047e3f 0x00000000  /* pioB */
+                                      0xfdffffff 0x00000000 0xb83fffff  /* pioC */
+                                      0x003fffff 0x003f8000 0x00000000  /* pioD */
+                                     >;
+                       };
+               };
+       };
+};
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts
new file mode 100644 (file)
index 0000000..86dd3f6
--- /dev/null
@@ -0,0 +1,16 @@
+/*
+ * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9g15.dtsi"
+/include/ "at91sam9x5ek.dtsi"
+
+/ {
+       model = "Atmel AT91SAM9G25-EK";
+       compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+};
index f1b2e14..66467b1 100644 (file)
        model = "Atmel at91sam9g20ek 2 mmc";
        compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9";
 
+       ahb {
+               apb{
+                       mmc0: mmc@fffa8000 {
+                               /* clk already mux wuth slot0 */
+                               pinctrl-0 = <
+                                       &pinctrl_board_mmc0_slot0
+                                       &pinctrl_mmc0_slot0_cmd_dat0
+                                       &pinctrl_mmc0_slot0_dat1_3>;
+                               slot@0 {
+                                       reg = <0>;
+                                       bus-width = <4>;
+                                       cd-gpios = <&pioC 2 0>;
+                               };
+                       };
+
+                       pinctrl@fffff400 {
+                               mmc0_slot0 {
+                                       pinctrl_board_mmc0_slot0: mmc0_slot0-board {
+                                               atmel,pins =
+                                                       <2 2 0x0 0x5>;  /* PC2 gpio CD pin pull up and deglitch */
+                                       };
+                               };
+                       };
+               };
+       };
+
        leds {
                compatible = "gpio-leds";
 
index e6391a4..32a500a 100644 (file)
                        };
 
                        usart0: serial@fffb0000 {
+                               pinctrl-0 =
+                                       <&pinctrl_usart0
+                                        &pinctrl_usart0_rts
+                                        &pinctrl_usart0_cts
+                                        &pinctrl_usart0_dtr_dsr
+                                        &pinctrl_usart0_dcd
+                                        &pinctrl_usart0_ri>;
                                status = "okay";
                        };
 
                                atmel,vbus-gpio = <&pioC 5 0>;
                                status = "okay";
                        };
+
+                       mmc0: mmc@fffa8000 {
+                               pinctrl-0 = <
+                                       &pinctrl_board_mmc0_slot1
+                                       &pinctrl_mmc0_clk
+                                       &pinctrl_mmc0_slot1_cmd_dat0
+                                       &pinctrl_mmc0_slot1_dat1_3>;
+                               status = "okay";
+                               slot@1 {
+                                       reg = <1>;
+                                       bus-width = <4>;
+                                       cd-gpios = <&pioC 9 0>;
+                               };
+                       };
+
+                       pinctrl@fffff400 {
+                               mmc0_slot1 {
+                                       pinctrl_board_mmc0_slot1: mmc0_slot1-board {
+                                               atmel,pins =
+                                                       <2 9 0x0 0x5>;  /* PC9 gpio CD pin pull up and deglitch */
+                                       };
+                               };
+                       };
                };
 
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
new file mode 100644 (file)
index 0000000..05a718f
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/include/ "at91sam9x5.dtsi"
+
+/ {
+       model = "Atmel AT91SAM9G25 SoC";
+       compatible = "atmel, at91sam9g25, atmel,at91sam9x5";
+
+       ahb {
+               apb {
+                       pinctrl@fffff400 {
+                               atmel,mux-mask = <
+                                     /*    A         B          C     */
+                                      0xffffffff 0xffe0399f 0xc000001c  /* pioA */
+                                      0x0007ffff 0x8000fe3f 0x00000000  /* pioB */
+                                      0x80000000 0x07c0ffff 0xb83fffff  /* pioC */
+                                      0x003fffff 0x003f8000 0x00000000  /* pioD */
+                                     >;
+                       };
+               };
+       };
+};
index 877c08f..c5ab16f 100644 (file)
@@ -7,55 +7,10 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9x5.dtsi"
-/include/ "at91sam9x5cm.dtsi"
+/include/ "at91sam9g25.dtsi"
+/include/ "at91sam9x5ek.dtsi"
 
 / {
        model = "Atmel AT91SAM9G25-EK";
        compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
-
-       chosen {
-               bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
-       };
-
-       ahb {
-               apb {
-                       dbgu: serial@fffff200 {
-                               status = "okay";
-                       };
-
-                       usart0: serial@f801c000 {
-                               status = "okay";
-                       };
-
-                       macb0: ethernet@f802c000 {
-                               phy-mode = "rmii";
-                               status = "okay";
-                       };
-
-                       i2c0: i2c@f8010000 {
-                               status = "okay";
-                       };
-
-                       i2c1: i2c@f8014000 {
-                               status = "okay";
-                       };
-
-                       i2c2: i2c@f8018000 {
-                               status = "okay";
-                       };
-               };
-
-               usb0: ohci@00600000 {
-                       status = "okay";
-                       num-ports = <2>;
-                       atmel,vbus-gpio = <&pioD 19 1
-                                          &pioD 20 1
-                                         >;
-               };
-
-               usb1: ehci@00700000 {
-                       status = "okay";
-               };
-       };
 };
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
new file mode 100644 (file)
index 0000000..f9d14a7
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/include/ "at91sam9x5.dtsi"
+
+/ {
+       model = "Atmel AT91SAM9G35 SoC";
+       compatible = "atmel, at91sam9g35, atmel,at91sam9x5";
+
+       ahb {
+               apb {
+                       pinctrl@fffff400 {
+                               atmel,mux-mask = <
+                                     /*    A         B          C     */
+                                      0xffffffff 0xffe0399f 0xc000000c  /* pioA */
+                                      0x000406ff 0x00047e3f 0x00000000  /* pioB */
+                                      0xfdffffff 0x00000000 0xb83fffff  /* pioC */
+                                      0x003fffff 0x003f8000 0x00000000  /* pioD */
+                                     >;
+                       };
+               };
+       };
+};
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts
new file mode 100644 (file)
index 0000000..95944bd
--- /dev/null
@@ -0,0 +1,16 @@
+/*
+ * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9g35.dtsi"
+/include/ "at91sam9x5ek.dtsi"
+
+/ {
+       model = "Atmel AT91SAM9G35-EK";
+       compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+};
index 3add030..0741cae 100644 (file)
                                interrupts = <21 4 0>;
                        };
 
-                       pioA: gpio@fffff200 {
-                               compatible = "atmel,at91rm9200-gpio";
-                               reg = <0xfffff200 0x100>;
-                               interrupts = <2 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                       };
+                       pinctrl@fffff200 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+                               ranges = <0xfffff200 0xfffff200 0xa00>;
+
+                               atmel,mux-mask = <
+                                     /*    A         B     */
+                                      0xffffffff 0xffc003ff  /* pioA */
+                                      0xffffffff 0x800f8f00  /* pioB */
+                                      0xffffffff 0x00000e00  /* pioC */
+                                      0xffffffff 0xff0c1381  /* pioD */
+                                      0xffffffff 0x81ffff81  /* pioE */
+                                     >;
+
+                               /* shared pinctrl settings */
+                               dbgu {
+                                       pinctrl_dbgu: dbgu-0 {
+                                               atmel,pins =
+                                                       <1 12 0x1 0x0   /* PB12 periph A */
+                                                        1 13 0x1 0x0>; /* PB13 periph A */
+                                       };
+                               };
 
-                       pioB: gpio@fffff400 {
-                               compatible = "atmel,at91rm9200-gpio";
-                               reg = <0xfffff400 0x100>;
-                               interrupts = <3 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                       };
+                               usart0 {
+                                       pinctrl_usart0: usart0-0 {
+                                               atmel,pins =
+                                                       <1 19 0x1 0x1   /* PB19 periph A with pullup */
+                                                        1 18 0x1 0x0>; /* PB18 periph A */
+                                       };
+
+                                       pinctrl_usart0_rts: usart0_rts-0 {
+                                               atmel,pins =
+                                                       <1 17 0x2 0x0>; /* PB17 periph B */
+                                       };
+
+                                       pinctrl_usart0_cts: usart0_cts-0 {
+                                               atmel,pins =
+                                                       <1 15 0x2 0x0>; /* PB15 periph B */
+                                       };
+                               };
 
-                       pioC: gpio@fffff600 {
-                               compatible = "atmel,at91rm9200-gpio";
-                               reg = <0xfffff600 0x100>;
-                               interrupts = <4 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                       };
+                               uart1 {
+                                       pinctrl_usart1: usart1-0 {
+                                               atmel,pins =
+                                                       <1 4 0x1 0x1    /* PB4 periph A with pullup */
+                                                        1 5 0x1 0x0>;  /* PB5 periph A */
+                                       };
+
+                                       pinctrl_usart1_rts: usart1_rts-0 {
+                                               atmel,pins =
+                                                       <3 16 0x1 0x0>; /* PD16 periph A */
+                                       };
+
+                                       pinctrl_usart1_cts: usart1_cts-0 {
+                                               atmel,pins =
+                                                       <3 17 0x1 0x0>; /* PD17 periph A */
+                                       };
+                               };
 
-                       pioD: gpio@fffff800 {
-                               compatible = "atmel,at91rm9200-gpio";
-                               reg = <0xfffff800 0x100>;
-                               interrupts = <5 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                       };
+                               usart2 {
+                                       pinctrl_usart2: usart2-0 {
+                                               atmel,pins =
+                                                       <1 6 0x1 0x1    /* PB6 periph A with pullup */
+                                                        1 7 0x1 0x0>;  /* PB7 periph A */
+                                       };
+
+                                       pinctrl_usart2_rts: usart2_rts-0 {
+                                               atmel,pins =
+                                                       <2 9 0x2 0x0>;  /* PC9 periph B */
+                                       };
+
+                                       pinctrl_usart2_cts: usart2_cts-0 {
+                                               atmel,pins =
+                                                       <2 11 0x2 0x0>; /* PC11 periph B */
+                                       };
+                               };
 
-                       pioE: gpio@fffffa00 {
-                               compatible = "atmel,at91rm9200-gpio";
-                               reg = <0xfffffa00 0x100>;
-                               interrupts = <5 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
+                               usart3 {
+                                       pinctrl_usart3: usart3-0 {
+                                               atmel,pins =
+                                                       <1 8 0x1 0x1    /* PB9 periph A with pullup */
+                                                        1 9 0x1 0x0>;  /* PB8 periph A */
+                                       };
+
+                                       pinctrl_usart3_rts: usart3_rts-0 {
+                                               atmel,pins =
+                                                       <0 23 0x2 0x0>; /* PA23 periph B */
+                                       };
+
+                                       pinctrl_usart3_cts: usart3_cts-0 {
+                                               atmel,pins =
+                                                       <0 24 0x2 0x0>; /* PA24 periph B */
+                                       };
+                               };
+
+                               nand {
+                                       pinctrl_nand: nand-0 {
+                                               atmel,pins =
+                                                       <2 8 0x0 0x1    /* PC8 gpio RDY pin pull_up*/
+                                                        2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
+                                       };
+                               };
+
+                               macb {
+                                       pinctrl_macb_rmii: macb_rmii-0 {
+                                               atmel,pins =
+                                                       <0 10 0x1 0x0   /* PA10 periph A */
+                                                        0 11 0x1 0x0   /* PA11 periph A */
+                                                        0 12 0x1 0x0   /* PA12 periph A */
+                                                        0 13 0x1 0x0   /* PA13 periph A */
+                                                        0 14 0x1 0x0   /* PA14 periph A */
+                                                        0 15 0x1 0x0   /* PA15 periph A */
+                                                        0 16 0x1 0x0   /* PA16 periph A */
+                                                        0 17 0x1 0x0   /* PA17 periph A */
+                                                        0 18 0x1 0x0   /* PA18 periph A */
+                                                        0 19 0x1 0x0>; /* PA19 periph A */
+                                       };
+
+                                       pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+                                               atmel,pins =
+                                                       <0 6 0x2 0x0    /* PA6 periph B */
+                                                        0 7 0x2 0x0    /* PA7 periph B */
+                                                        0 8 0x2 0x0    /* PA8 periph B */
+                                                        0 9 0x2 0x0    /* PA9 periph B */
+                                                        0 27 0x2 0x0   /* PA27 periph B */
+                                                        0 28 0x2 0x0   /* PA28 periph B */
+                                                        0 29 0x2 0x0   /* PA29 periph B */
+                                                        0 30 0x2 0x0>; /* PA30 periph B */
+                                       };
+                               };
+
+                               mmc0 {
+                                       pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
+                                               atmel,pins =
+                                                       <0 0 0x1 0x0    /* PA0 periph A */
+                                                        0 1 0x1 0x1    /* PA1 periph A with pullup */
+                                                        0 2 0x1 0x1>;  /* PA2 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+                                               atmel,pins =
+                                                       <0 3 0x1 0x1    /* PA3 periph A with pullup */
+                                                        0 4 0x1 0x1    /* PA4 periph A with pullup */
+                                                        0 5 0x1 0x1>;  /* PA5 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
+                                               atmel,pins =
+                                                       <0 6 0x1 0x1    /* PA6 periph A with pullup */
+                                                        0 7 0x1 0x1    /* PA7 periph A with pullup */
+                                                        0 8 0x1 0x1    /* PA8 periph A with pullup */
+                                                        0 9 0x1 0x1>;  /* PA9 periph A with pullup */
+                                       };
+                               };
+
+                               mmc1 {
+                                       pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
+                                               atmel,pins =
+                                                       <0 31 0x1 0x0   /* PA31 periph A */
+                                                        0 22 0x1 0x1   /* PA22 periph A with pullup */
+                                                        0 23 0x1 0x1>; /* PA23 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
+                                               atmel,pins =
+                                                       <0 24 0x1 0x1   /* PA24 periph A with pullup */
+                                                        0 25 0x1 0x1   /* PA25 periph A with pullup */
+                                                        0 26 0x1 0x1>; /* PA26 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
+                                               atmel,pins =
+                                                       <0 27 0x1 0x1   /* PA27 periph A with pullup */
+                                                        0 28 0x1 0x1   /* PA28 periph A with pullup */
+                                                        0 29 0x1 0x1   /* PA29 periph A with pullup */
+                                                        0 20 0x1 0x1>; /* PA30 periph A with pullup */
+                                       };
+                               };
+
+                               pioA: gpio@fffff200 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff200 0x200>;
+                                       interrupts = <2 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioB: gpio@fffff400 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff400 0x200>;
+                                       interrupts = <3 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioC: gpio@fffff600 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff600 0x200>;
+                                       interrupts = <4 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioD: gpio@fffff800 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff800 0x200>;
+                                       interrupts = <5 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioE: gpio@fffffa00 {
+                                       compatible = "atmel,at91rm9200-gpio";
+                                       reg = <0xfffffa00 0x200>;
+                                       interrupts = <5 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
                        };
 
                        dbgu: serial@ffffee00 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xffffee00 0x200>;
                                interrupts = <1 4 7>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
                        };
 
                                interrupts = <7 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
                        };
 
                                interrupts = <8 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
                        };
 
                                interrupts = <9 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
                        };
 
                                interrupts = <10 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart3>;
                                status = "disabled";
                        };
 
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xfffbc000 0x100>;
                                interrupts = <25 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_macb_rmii>;
                                status = "disabled";
                        };
 
                                        trigger-value = <0x6>;
                                };
                        };
+
+                       mmc0: mmc@fff80000 {
+                               compatible = "atmel,hsmci";
+                               reg = <0xfff80000 0x600>;
+                               interrupts = <11 4 0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       mmc1: mmc@fffd0000 {
+                               compatible = "atmel,hsmci";
+                               reg = <0xfffd0000 0x600>;
+                               interrupts = <29 4 0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
                };
 
                nand0: nand@40000000 {
                              >;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_nand>;
                        gpios = <&pioC 8 0
                                 &pioC 14 0
                                 0
index 15e1dd4..20c3191 100644 (file)
                        };
 
                        usart1: serial@fff90000 {
+                               pinctrl-0 =
+                                       <&pinctrl_usart1
+                                        &pinctrl_usart1_rts
+                                        &pinctrl_usart1_cts>;
                                status = "okay";
                        };
 
                        i2c1: i2c@fff88000 {
                                status = "okay";
                        };
+
+                       mmc0: mmc@fff80000 {
+                               pinctrl-0 = <
+                                       &pinctrl_board_mmc0
+                                       &pinctrl_mmc0_slot0_clk_cmd_dat0
+                                       &pinctrl_mmc0_slot0_dat1_3>;
+                               status = "okay";
+                               slot@0 {
+                                       reg = <0>;
+                                       bus-width = <4>;
+                                       cd-gpios = <&pioD 10 0>;
+                               };
+                       };
+
+                       mmc1: mmc@fffd0000 {
+                               pinctrl-0 = <
+                                       &pinctrl_board_mmc1
+                                       &pinctrl_mmc1_slot0_clk_cmd_dat0
+                                       &pinctrl_mmc1_slot0_dat1_3>;
+                               status = "okay";
+                               slot@0 {
+                                       reg = <0>;
+                                       bus-width = <4>;
+                                       cd-gpios = <&pioD 11 0>;
+                                       wp-gpios = <&pioD 29 0>;
+                               };
+                       };
+
+                       pinctrl@fffff200 {
+                               mmc0 {
+                                       pinctrl_board_mmc0: mmc0-board {
+                                               atmel,pins =
+                                                       <3 10 0x0 0x5>; /* PD10 gpio CD pin pull up and deglitch */
+                                       };
+                               };
+
+                               mmc1 {
+                                       pinctrl_board_mmc1: mmc1-board {
+                                               atmel,pins =
+                                                       <3 11 0x0 0x5   /* PD11 gpio CD pin pull up and deglitch */
+                                                        3 29 0x0 0x1>; /* PD29 gpio WP pin pull up */
+                                       };
+                               };
+                       };
                };
 
                nand0: nand@40000000 {
index 82508d6..e9efb34 100644 (file)
                                reg = <0xfffffe10 0x10>;
                        };
 
+                       mmc0: mmc@f0008000 {
+                               compatible = "atmel,hsmci";
+                               reg = <0xf0008000 0x600>;
+                               interrupts = <12 4 0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
                        tcb0: timer@f8008000 {
                                compatible = "atmel,at91sam9x5-tcb";
                                reg = <0xf8008000 0x100>;
                                interrupts = <20 4 0>;
                        };
 
-                       pioA: gpio@fffff400 {
-                               compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                               reg = <0xfffff400 0x100>;
-                               interrupts = <2 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                       };
+                       pinctrl@fffff400 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+                               ranges = <0xfffff400 0xfffff400 0x800>;
 
-                       pioB: gpio@fffff600 {
-                               compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                               reg = <0xfffff600 0x100>;
-                               interrupts = <2 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                       };
+                               atmel,mux-mask = <
+                                     /*    A         B          C     */
+                                      0xffffffff 0xffe07983 0x00000000  /* pioA */
+                                      0x00040000 0x00047e0f 0x00000000  /* pioB */
+                                      0xfdffffff 0x07c00000 0xb83fffff  /* pioC */
+                                      0x003fffff 0x003f8000 0x00000000  /* pioD */
+                                     >;
 
-                       pioC: gpio@fffff800 {
-                               compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                               reg = <0xfffff800 0x100>;
-                               interrupts = <3 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                       };
+                               /* shared pinctrl settings */
+                               dbgu {
+                                       pinctrl_dbgu: dbgu-0 {
+                                               atmel,pins =
+                                                       <0 9 0x1 0x0    /* PA9 periph A */
+                                                        0 10 0x1 0x1>; /* PA10 periph with pullup */
+                                       };
+                               };
 
-                       pioD: gpio@fffffa00 {
-                               compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                               reg = <0xfffffa00 0x100>;
-                               interrupts = <3 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
+                               usart0 {
+                                       pinctrl_usart0: usart0-0 {
+                                               atmel,pins =
+                                                       <0 1 0x1 0x1    /* PA1 periph A with pullup */
+                                                        0 0 0x1 0x0>;  /* PA0 periph A */
+                                       };
+
+                                       pinctrl_usart0_rts: usart0_rts-0 {
+                                               atmel,pins =
+                                                       <0 2 0x1 0x0>;  /* PA2 periph A */
+                                       };
+
+                                       pinctrl_usart0_cts: usart0_cts-0 {
+                                               atmel,pins =
+                                                       <0 3 0x1 0x0>;  /* PA3 periph A */
+                                       };
+                               };
+
+                               usart1 {
+                                       pinctrl_usart1: usart1-0 {
+                                               atmel,pins =
+                                                       <0 6 0x1 0x1    /* PA6 periph A with pullup */
+                                                        0 5 0x1 0x0>;  /* PA5 periph A */
+                                       };
+                               };
+
+                               usart2 {
+                                       pinctrl_usart2: usart2-0 {
+                                               atmel,pins =
+                                                       <0 8 0x1 0x1    /* PA8 periph A with pullup */
+                                                        0 7 0x1 0x0>;  /* PA7 periph A */
+                                       };
+
+                                       pinctrl_usart2_rts: usart2_rts-0 {
+                                               atmel,pins =
+                                                       <1 0 0x2 0x0>;  /* PB0 periph B */
+                                       };
+
+                                       pinctrl_usart2_cts: usart2_cts-0 {
+                                               atmel,pins =
+                                                       <1 1 0x2 0x0>;  /* PB1 periph B */
+                                       };
+                               };
+
+                               usart3 {
+                                       pinctrl_usart3: usart3-0 {
+                                               atmel,pins =
+                                                       <2 23 0x2 0x1   /* PC23 periph B with pullup */
+                                                        2 22 0x2 0x0>; /* PC22 periph B */
+                                       };
+
+                                       pinctrl_usart3_rts: usart3_rts-0 {
+                                               atmel,pins =
+                                                       <2 24 0x2 0x0>; /* PC24 periph B */
+                                       };
+
+                                       pinctrl_usart3_cts: usart3_cts-0 {
+                                               atmel,pins =
+                                                       <2 25 0x2 0x0>; /* PC25 periph B */
+                                       };
+                               };
+
+                               uart0 {
+                                       pinctrl_uart0: uart0-0 {
+                                               atmel,pins =
+                                                       <2 9 0x3 0x1    /* PC9 periph C with pullup */
+                                                        2 8 0x3 0x0>;  /* PC8 periph C */
+                                       };
+                               };
+
+                               uart1 {
+                                       pinctrl_uart1: uart1-0 {
+                                               atmel,pins =
+                                                       <2 16 0x3 0x1   /* PC17 periph C with pullup */
+                                                        2 17 0x3 0x0>; /* PC16 periph C */
+                                       };
+                               };
+
+                               nand {
+                                       pinctrl_nand: nand-0 {
+                                               atmel,pins =
+                                                       <3 5 0x0 0x1    /* PD5 gpio RDY pin pull_up*/
+                                                        3 4 0x0 0x1>;  /* PD4 gpio enable pin pull_up */
+                                       };
+                               };
+
+                               mmc0 {
+                                       pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
+                                               atmel,pins =
+                                                       <0 17 0x1 0x0   /* PA17 periph A */
+                                                        0 16 0x1 0x1   /* PA16 periph A with pullup */
+                                                        0 15 0x1 0x1>; /* PA15 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+                                               atmel,pins =
+                                                       <0 18 0x1 0x1   /* PA18 periph A with pullup */
+                                                        0 19 0x1 0x1   /* PA19 periph A with pullup */
+                                                        0 20 0x1 0x1>; /* PA20 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
+                                               atmel,pins =
+                                                       <0 11 0x2 0x1   /* PA11 periph B with pullup */
+                                                        0 12 0x2 0x1   /* PA12 periph B with pullup */
+                                                        0 13 0x2 0x1   /* PA13 periph B with pullup */
+                                                        0 14 0x2 0x1>; /* PA14 periph B with pullup */
+                                       };
+                               };
+
+                               pioA: gpio@fffff400 {
+                                       compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff400 0x200>;
+                                       interrupts = <2 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioB: gpio@fffff600 {
+                                       compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff600 0x200>;
+                                       interrupts = <2 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioC: gpio@fffff800 {
+                                       compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff800 0x200>;
+                                       interrupts = <3 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioD: gpio@fffffa00 {
+                                       compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                       reg = <0xfffffa00 0x200>;
+                                       interrupts = <3 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
                        };
 
                        dbgu: serial@fffff200 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffff200 0x200>;
                                interrupts = <1 4 7>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
                        };
 
                                interrupts = <5 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
                        };
 
                                interrupts = <6 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
                        };
 
                                interrupts = <7 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
                        };
 
                                interrupts = <8 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart3>;
                                status = "disabled";
                        };
 
                               >;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_nand>;
                        gpios = <&pioD 5 0
                                 &pioD 4 0
                                 0
index 912b2c2..0376bf4 100644 (file)
                        i2c1: i2c@f8014000 {
                                status = "okay";
                        };
+
+                       mmc0: mmc@f0008000 {
+                               pinctrl-0 = <
+                                       &pinctrl_board_mmc0
+                                       &pinctrl_mmc0_slot0_clk_cmd_dat0
+                                       &pinctrl_mmc0_slot0_dat1_3>;
+                               status = "okay";
+                               slot@0 {
+                                       reg = <0>;
+                                       bus-width = <4>;
+                                       cd-gpios = <&pioA 7 0>;
+                               };
+                       };
+
+                       pinctrl@fffff400 {
+                               mmc0 {
+                                       pinctrl_board_mmc0: mmc0-board {
+                                               atmel,pins =
+                                                       <0 7 0x0 0x5>;  /* PA7 gpio CD pin pull up and deglitch */
+                                       };
+                               };
+                       };
                };
 
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
new file mode 100644 (file)
index 0000000..54eb33b
--- /dev/null
@@ -0,0 +1,49 @@
+/*
+ * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/include/ "at91sam9x5.dtsi"
+
+/ {
+       model = "Atmel AT91SAM9X25 SoC";
+       compatible = "atmel, at91sam9x25, atmel,at91sam9x5";
+
+       ahb {
+               apb {
+                       pinctrl@fffff400 {
+                               atmel,mux-mask = <
+                                     /*    A         B          C     */
+                                      0xffffffff 0xffe03fff 0xc000001c  /* pioA */
+                                      0x0007ffff 0x00047e3f 0x00000000  /* pioB */
+                                      0x80000000 0xfffd0000 0xb83fffff  /* pioC */
+                                      0x003fffff 0x003f8000 0x00000000  /* pioD */
+                                     >;
+
+                               macb1 {
+                                       pinctrl_macb1_rmii: macb1_rmii-0 {
+                                               atmel,pins =
+                                                       <2 16 0x2 0x0   /* PC16 periph B */
+                                                        2 18 0x2 0x0   /* PC18 periph B */
+                                                        2 19 0x2 0x0   /* PC19 periph B */
+                                                        2 20 0x2 0x0   /* PC20 periph B */
+                                                        2 21 0x2 0x0   /* PC21 periph B */
+                                                        2 27 0x2 0x0   /* PC27 periph B */
+                                                        2 28 0x2 0x0   /* PC28 periph B */
+                                                        2 29 0x2 0x0   /* PC29 periph B */
+                                                        2 30 0x2 0x0   /* PC30 periph B */
+                                                        2 31 0x2 0x0>; /* PC31 periph B */
+                                       };
+                               };
+                       };
+
+                       macb1: ethernet@f8030000 {
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_macb1_rmii>;
+                       };
+               };
+       };
+};
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
new file mode 100644 (file)
index 0000000..af907ea
--- /dev/null
@@ -0,0 +1,16 @@
+/*
+ * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9x25.dtsi"
+/include/ "at91sam9x5ek.dtsi"
+
+/ {
+       model = "Atmel AT91SAM9G25-EK";
+       compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
new file mode 100644 (file)
index 0000000..fb102d6
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/include/ "at91sam9x5.dtsi"
+
+/ {
+       model = "Atmel AT91SAM9X35 SoC";
+       compatible = "atmel, at91sam9x35, atmel,at91sam9x5";
+
+       ahb {
+               apb {
+                       pinctrl@fffff400 {
+                               atmel,mux-mask = <
+                                     /*    A         B          C     */
+                                      0xffffffff 0xffe03fff 0xc000000c  /* pioA */
+                                      0x000406ff 0x00047e3f 0x00000000  /* pioB */
+                                      0xfdffffff 0x00000000 0xb83fffff  /* pioC */
+                                      0x003fffff 0x003f8000 0x00000000  /* pioD */
+                                     >;
+                       };
+               };
+       };
+};
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts
new file mode 100644 (file)
index 0000000..5ccb607
--- /dev/null
@@ -0,0 +1,16 @@
+/*
+ * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9x35.dtsi"
+/include/ "at91sam9x5ek.dtsi"
+
+/ {
+       model = "Atmel AT91SAM9X35-EK";
+       compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+};
index 03fc136..7ee49e8 100644 (file)
                                interrupts = <21 4 0>;
                        };
 
-                       pioA: gpio@fffff400 {
-                               compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                               reg = <0xfffff400 0x100>;
-                               interrupts = <2 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                       };
+                       pinctrl@fffff400 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+                               ranges = <0xfffff400 0xfffff400 0x800>;
+
+                               /* shared pinctrl settings */
+                               dbgu {
+                                       pinctrl_dbgu: dbgu-0 {
+                                               atmel,pins =
+                                                       <0 9 0x1 0x0    /* PA9 periph A */
+                                                        0 10 0x1 0x1>; /* PA10 periph A with pullup */
+                                       };
+                               };
 
-                       pioB: gpio@fffff600 {
-                               compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                               reg = <0xfffff600 0x100>;
-                               interrupts = <2 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
+                               usart0 {
+                                       pinctrl_usart0: usart0-0 {
+                                               atmel,pins =
+                                                       <0 0 0x1 0x1    /* PA0 periph A with pullup */
+                                                        0 1 0x1 0x0>;  /* PA1 periph A */
+                                       };
+
+                                       pinctrl_usart0_rts: usart0_rts-0 {
+                                               atmel,pins =
+                                                       <0 2 0x1 0x0>;  /* PA2 periph A */
+                                       };
+
+                                       pinctrl_usart0_cts: usart0_cts-0 {
+                                               atmel,pins =
+                                                       <0 3 0x1 0x0>;  /* PA3 periph A */
+                                       };
+                               };
+
+                               usart1 {
+                                       pinctrl_usart1: usart1-0 {
+                                               atmel,pins =
+                                                       <0 5 0x1 0x1    /* PA5 periph A with pullup */
+                                                        0 6 0x1 0x0>;  /* PA6 periph A */
+                                       };
+
+                                       pinctrl_usart1_rts: usart1_rts-0 {
+                                               atmel,pins =
+                                                       <3 27 0x3 0x0>; /* PC27 periph C */
+                                       };
+
+                                       pinctrl_usart1_cts: usart1_cts-0 {
+                                               atmel,pins =
+                                                       <3 28 0x3 0x0>; /* PC28 periph C */
+                                       };
+                               };
+
+                               usart2 {
+                                       pinctrl_usart2: usart2-0 {
+                                               atmel,pins =
+                                                       <0 7 0x1 0x1    /* PA7 periph A with pullup */
+                                                        0 8 0x1 0x0>;  /* PA8 periph A */
+                                       };
+
+                                       pinctrl_uart2_rts: uart2_rts-0 {
+                                               atmel,pins =
+                                                       <0 0 0x2 0x0>;  /* PB0 periph B */
+                                       };
+
+                                       pinctrl_uart2_cts: uart2_cts-0 {
+                                               atmel,pins =
+                                                       <0 1 0x2 0x0>;  /* PB1 periph B */
+                                       };
+                               };
+
+                               usart3 {
+                                       pinctrl_uart3: usart3-0 {
+                                               atmel,pins =
+                                                       <3 23 0x2 0x1   /* PC22 periph B with pullup */
+                                                        3 23 0x2 0x0>; /* PC23 periph B */
+                                       };
+
+                                       pinctrl_usart3_rts: usart3_rts-0 {
+                                               atmel,pins =
+                                                       <3 24 0x2 0x0>; /* PC24 periph B */
+                                       };
+
+                                       pinctrl_usart3_cts: usart3_cts-0 {
+                                               atmel,pins =
+                                                       <3 25 0x2 0x0>; /* PC25 periph B */
+                                       };
+                               };
+
+                               uart0 {
+                                       pinctrl_uart0: uart0-0 {
+                                               atmel,pins =
+                                                       <3 8 0x3 0x0    /* PC8 periph C */
+                                                        3 9 0x3 0x1>;  /* PC9 periph C with pullup */
+                                       };
+                               };
+
+                               uart1 {
+                                       pinctrl_uart1: uart1-0 {
+                                               atmel,pins =
+                                                       <3 16 0x3 0x0   /* PC16 periph C */
+                                                        3 17 0x3 0x1>; /* PC17 periph C with pullup */
+                                       };
+                               };
+
+                               nand {
+                                       pinctrl_nand: nand-0 {
+                                               atmel,pins =
+                                                       <3 4 0x0 0x1    /* PD5 gpio RDY pin pull_up */
+                                                        3 5 0x0 0x1>;  /* PD4 gpio enable pin pull_up */
+                                       };
+                               };
+
+                               macb0 {
+                                       pinctrl_macb0_rmii: macb0_rmii-0 {
+                                               atmel,pins =
+                                                       <1 0 0x1 0x0    /* PB0 periph A */
+                                                        1 1 0x1 0x0    /* PB1 periph A */
+                                                        1 2 0x1 0x0    /* PB2 periph A */
+                                                        1 3 0x1 0x0    /* PB3 periph A */
+                                                        1 4 0x1 0x0    /* PB4 periph A */
+                                                        1 5 0x1 0x0    /* PB5 periph A */
+                                                        1 6 0x1 0x0    /* PB6 periph A */
+                                                        1 7 0x1 0x0    /* PB7 periph A */
+                                                        1 9 0x1 0x0    /* PB9 periph A */
+                                                        1 10 0x1 0x0>; /* PB10 periph A */
+                                       };
+
+                                       pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
+                                               atmel,pins =
+                                                       <1 8 0x1 0x0    /* PA8 periph A */
+                                                        1 11 0x1 0x0   /* PA11 periph A */
+                                                        1 12 0x1 0x0   /* PA12 periph A */
+                                                        1 13 0x1 0x0   /* PA13 periph A */
+                                                        1 14 0x1 0x0   /* PA14 periph A */
+                                                        1 15 0x1 0x0   /* PA15 periph A */
+                                                        1 16 0x1 0x0   /* PA16 periph A */
+                                                        1 17 0x1 0x0>; /* PA17 periph A */
+                                       };
+                               };
+
+                               mmc0 {
+                                       pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
+                                               atmel,pins =
+                                                       <0 17 0x1 0x0   /* PA17 periph A */
+                                                        0 16 0x1 0x1   /* PA16 periph A with pullup */
+                                                        0 15 0x1 0x1>; /* PA15 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+                                               atmel,pins =
+                                                       <0 18 0x1 0x1   /* PA18 periph A with pullup */
+                                                        0 19 0x1 0x1   /* PA19 periph A with pullup */
+                                                        0 20 0x1 0x1>; /* PA20 periph A with pullup */
+                                       };
+                               };
+
+                               mmc1 {
+                                       pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
+                                               atmel,pins =
+                                                       <0 13 0x2 0x0   /* PA13 periph B */
+                                                        0 12 0x2 0x1   /* PA12 periph B with pullup */
+                                                        0 11 0x2 0x1>; /* PA11 periph B with pullup */
+                                       };
+
+                                       pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
+                                               atmel,pins =
+                                                       <0 2 0x2 0x1    /* PA2 periph B with pullup */
+                                                        0 3 0x2 0x1    /* PA3 periph B with pullup */
+                                                        0 4 0x2 0x1>;  /* PA4 periph B with pullup */
+                                       };
+                               };
+
+                               pioA: gpio@fffff400 {
+                                       compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff400 0x200>;
+                                       interrupts = <2 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioB: gpio@fffff600 {
+                                       compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff600 0x200>;
+                                       interrupts = <2 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       #gpio-lines = <19>;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioC: gpio@fffff800 {
+                                       compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                       reg = <0xfffff800 0x200>;
+                                       interrupts = <3 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
+
+                               pioD: gpio@fffffa00 {
+                                       compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                       reg = <0xfffffa00 0x200>;
+                                       interrupts = <3 4 1>;
+                                       #gpio-cells = <2>;
+                                       gpio-controller;
+                                       #gpio-lines = <22>;
+                                       interrupt-controller;
+                                       #interrupt-cells = <2>;
+                               };
                        };
 
-                       pioC: gpio@fffff800 {
-                               compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                               reg = <0xfffff800 0x100>;
-                               interrupts = <3 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
+                       mmc0: mmc@f0008000 {
+                               compatible = "atmel,hsmci";
+                               reg = <0xf0008000 0x600>;
+                               interrupts = <12 4 0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
                        };
 
-                       pioD: gpio@fffffa00 {
-                               compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                               reg = <0xfffffa00 0x100>;
-                               interrupts = <3 4 1>;
-                               #gpio-cells = <2>;
-                               gpio-controller;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
+                       mmc1: mmc@f000c000 {
+                               compatible = "atmel,hsmci";
+                               reg = <0xf000c000 0x600>;
+                               interrupts = <26 4 0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
                        };
 
                        dbgu: serial@fffff200 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffff200 0x200>;
                                interrupts = <1 4 7>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
                        };
 
                                interrupts = <5 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
                        };
 
                                interrupts = <6 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
                        };
 
                                interrupts = <7 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
                        };
 
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xf802c000 0x100>;
                                interrupts = <24 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_macb0_rmii>;
                                status = "disabled";
                        };
 
                              >;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_nand>;
                        gpios = <&pioD 5 0
                                 &pioD 4 0
                                 0
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
new file mode 100644 (file)
index 0000000..8a7cf1d
--- /dev/null
@@ -0,0 +1,101 @@
+/*
+ * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "at91sam9x5cm.dtsi"
+
+/ {
+       model = "Atmel AT91SAM9X5-EK";
+       compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+
+       chosen {
+               bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
+       };
+
+       ahb {
+               apb {
+                       mmc0: mmc@f0008000 {
+                               pinctrl-0 = <
+                                       &pinctrl_board_mmc0
+                                       &pinctrl_mmc0_slot0_clk_cmd_dat0
+                                       &pinctrl_mmc0_slot0_dat1_3>;
+                               status = "okay";
+                               slot@0 {
+                                       reg = <0>;
+                                       bus-width = <4>;
+                                       cd-gpios = <&pioD 15 0>;
+                               };
+                       };
+
+                       mmc1: mmc@f000c000 {
+                               pinctrl-0 = <
+                                       &pinctrl_board_mmc1
+                                       &pinctrl_mmc1_slot0_clk_cmd_dat0
+                                       &pinctrl_mmc1_slot0_dat1_3>;
+                               status = "okay";
+                               slot@0 {
+                                       reg = <0>;
+                                       bus-width = <4>;
+                                       cd-gpios = <&pioD 14 0>;
+                               };
+                       };
+
+                       dbgu: serial@fffff200 {
+                               status = "okay";
+                       };
+
+                       usart0: serial@f801c000 {
+                               status = "okay";
+                       };
+
+                       macb0: ethernet@f802c000 {
+                               phy-mode = "rmii";
+                               status = "okay";
+                       };
+
+                       i2c0: i2c@f8010000 {
+                               status = "okay";
+                       };
+
+                       i2c1: i2c@f8014000 {
+                               status = "okay";
+                       };
+
+                       i2c2: i2c@f8018000 {
+                               status = "okay";
+                       };
+
+                       pinctrl@fffff400 {
+                               mmc0 {
+                                       pinctrl_board_mmc0: mmc0-board {
+                                               atmel,pins =
+                                                       <3 15 0x0 0x5>; /* PD15 gpio CD pin pull up and deglitch */
+                                       };
+                               };
+
+                               mmc1 {
+                                       pinctrl_board_mmc1: mmc1-board {
+                                               atmel,pins =
+                                                       <3 14 0x0 0x5>; /* PD14 gpio CD pin pull up and deglitch */
+                                       };
+                               };
+                       };
+               };
+
+               usb0: ohci@00600000 {
+                       status = "okay";
+                       num-ports = <2>;
+                       atmel,vbus-gpio = <&pioD 19 1
+                                          &pioD 20 1
+                                         >;
+               };
+
+               usb1: ehci@00700000 {
+                       status = "okay";
+               };
+       };
+};
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts
new file mode 100644 (file)
index 0000000..387fedb
--- /dev/null
@@ -0,0 +1,165 @@
+/*
+ * pm9g45.dts - Device Tree file for Ronetix pm9g45 board
+ *
+ *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+/include/ "at91sam9g45.dtsi"
+
+/ {
+       model = "Ronetix pm9g45";
+       compatible = "ronetix,pm9g45", "atmel,at91sam9g45", "atmel,at91sam9";
+
+       chosen {
+               bootargs = "console=ttyS0,115200";
+       };
+
+       memory {
+               reg = <0x70000000 0x8000000>;
+       };
+
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               main_clock: clock@0 {
+                       compatible = "atmel,osc", "fixed-clock";
+                       clock-frequency = <12000000>;
+               };
+       };
+
+       ahb {
+               apb {
+                       dbgu: serial@ffffee00 {
+                               status = "okay";
+                       };
+
+                       pinctrl@fffff200 {
+
+                               board {
+                                       pinctrl_board_nand: nand0-board {
+                                               atmel,pins =
+                                                       <3 3 0x0 0x1    /* PD3 gpio RDY pin pull_up*/
+                                                        2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
+                                       };
+                               };
+
+                               mmc {
+                                       pinctrl_board_mmc: mmc0-board {
+                                               atmel,pins =
+                                                       <3 6 0x0 0x5>;  /* PD6 gpio CD pin pull_up and deglitch */
+                                       };
+                               };
+                       };
+
+                       mmc0: mmc@fff80000 {
+                               pinctrl-0 = <
+                                       &pinctrl_board_mmc
+                                       &pinctrl_mmc0_slot0_clk_cmd_dat0
+                                       &pinctrl_mmc0_slot0_dat1_3>;
+                               status = "okay";
+                               slot@0 {
+                                       reg = <0>;
+                                       bus-width = <4>;
+                                       cd-gpios = <&pioD 6 0>;
+                               };
+                       };
+
+                       macb0: ethernet@fffbc000 {
+                               phy-mode = "rmii";
+                               status = "okay";
+                       };
+
+               };
+
+               nand0: nand@40000000 {
+                       nand-bus-width = <8>;
+                       nand-ecc-mode = "soft";
+                       nand-on-flash-bbt;
+                       pinctrl-0 = <&pinctrl_board_nand>;
+
+                       gpios = <&pioD 3 0
+                                &pioC 14 0
+                                0
+                               >;
+
+                       status = "okay";
+
+                       at91bootstrap@0 {
+                               label = "at91bootstrap";
+                               reg = <0x0 0x20000>;
+                       };
+
+                       barebox@20000 {
+                               label = "barebox";
+                               reg = <0x20000 0x40000>;
+                       };
+
+                       bareboxenv@60000 {
+                               label = "bareboxenv";
+                               reg = <0x60000 0x1A0000>;
+                       };
+
+                       kernel@200000 {
+                               label = "bareboxenv2";
+                               reg = <0x200000 0x300000>;
+                       };
+
+                       kernel@500000 {
+                               label = "root";
+                               reg = <0x500000 0x400000>;
+                       };
+
+                       data@900000 {
+                               label = "data";
+                               reg = <0x900000 0x8340000>;
+                       };
+               };
+
+               usb0: ohci@00700000 {
+                       status = "okay";
+                       num-ports = <2>;
+               };
+
+               usb1: ehci@00800000 {
+                       status = "okay";
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               led0 {
+                       label = "led0";
+                       gpios = <&pioD 0 1>;
+                       linux,default-trigger = "nand-disk";
+               };
+
+               led1 {
+                       label = "led1";
+                       gpios = <&pioD 31 0>;
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       gpio_keys {
+               compatible = "gpio-keys";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               right {
+                       label = "SW4";
+                       gpios = <&pioE 7 1>;
+                       linux,code = <106>;
+               };
+
+               up {
+                       label = "SW3";
+                       gpios = <&pioE 8 1>;
+                       linux,code = <103>;
+               };
+       };
+};
index dd4358b..2e4c572 100644 (file)
                               status = "okay";
                        };
 
+                       gpio@d8400000 {
+                              status = "okay";
+                       };
+
                        i2c0: i2c@e0280000 {
                               status = "okay";
                        };
index 419ea74..7cd25eb 100644 (file)
                        status = "disabled";
                };
 
+               pinmux: pinmux@e0700000 {
+                       compatible = "st,spear1310-pinmux";
+                       reg = <0xe0700000 0x1000>;
+                       #gpio-range-cells = <2>;
+               };
+
                spi1: spi@5d400000 {
                        compatible = "arm,pl022", "arm,primecell";
                        reg = <0x5d400000 0x1000>;
                        thermal@e07008c4 {
                                st,thermal-flags = <0x7000>;
                        };
+
+                       gpiopinctrl: gpio@d8400000 {
+                               compatible = "st,spear-plgpio";
+                               reg = <0xd8400000 0x1000>;
+                               interrupts = <0 100 0x4>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               gpio-ranges = <&pinmux 0 246>;
+                               status = "disabled";
+
+                               st-plgpio,ngpio = <246>;
+                               st-plgpio,enb-reg = <0xd0>;
+                               st-plgpio,wdata-reg = <0x90>;
+                               st-plgpio,dir-reg = <0xb0>;
+                               st-plgpio,ie-reg = <0x30>;
+                               st-plgpio,rdata-reg = <0x70>;
+                               st-plgpio,mis-reg = <0x10>;
+                               st-plgpio,eit-reg = <0x50>;
+                       };
                };
        };
 };
index c9a54e0..045f712 100644 (file)
                               status = "okay";
                        };
 
+                       gpio@e2800000 {
+                              status = "okay";
+                       };
+
                        i2c0: i2c@e0280000 {
                               status = "okay";
                        };
index d71fe2a..6c09eb0 100644 (file)
                        status = "disabled";
                };
 
+               pinmux: pinmux@e0700000 {
+                       compatible = "st,spear1340-pinmux";
+                       reg = <0xe0700000 0x1000>;
+                       #gpio-range-cells = <2>;
+               };
+
                spi1: spi@5d400000 {
                        compatible = "arm,pl022", "arm,primecell";
                        reg = <0x5d400000 0x1000>;
                        thermal@e07008c4 {
                                st,thermal-flags = <0x2a00>;
                        };
+
+                       gpiopinctrl: gpio@e2800000 {
+                               compatible = "st,spear-plgpio";
+                               reg = <0xe2800000 0x1000>;
+                               interrupts = <0 107 0x4>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               gpio-ranges = <&pinmux 0 252>;
+                               status = "disabled";
+
+                               st-plgpio,ngpio = <250>;
+                               st-plgpio,wdata-reg = <0x40>;
+                               st-plgpio,dir-reg = <0x00>;
+                               st-plgpio,ie-reg = <0x80>;
+                               st-plgpio,rdata-reg = <0x20>;
+                               st-plgpio,mis-reg = <0xa0>;
+                               st-plgpio,eit-reg = <0x60>;
+                       };
                };
        };
 };
index 62fc4fb..930303e 100644 (file)
                          0xb0000000 0xb0000000 0x10000000
                          0xd0000000 0xd0000000 0x30000000>;
 
-               pinmux@b4000000 {
+               pinmux: pinmux@b4000000 {
                        compatible = "st,spear310-pinmux";
                        reg = <0xb4000000 0x1000>;
+                       #gpio-range-cells = <2>;
                };
 
                fsmc: flash@44000000 {
                                reg = <0xb2200000 0x1000>;
                                status = "disabled";
                        };
+
+                       gpiopinctrl: gpio@b4000000 {
+                               compatible = "st,spear-plgpio";
+                               reg = <0xb4000000 0x1000>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               gpio-ranges = <&pinmux 0 102>;
+                               status = "disabled";
+
+                               st-plgpio,ngpio = <102>;
+                               st-plgpio,enb-reg = <0x10>;
+                               st-plgpio,wdata-reg = <0x20>;
+                               st-plgpio,dir-reg = <0x30>;
+                               st-plgpio,ie-reg = <0x50>;
+                               st-plgpio,rdata-reg = <0x40>;
+                               st-plgpio,mis-reg = <0x60>;
+                       };
                };
        };
 };
index 082328b..ad4bfc6 100644 (file)
                               status = "okay";
                        };
 
+                       gpio@b3000000 {
+                              status = "okay";
+                       };
+
                        i2c0: i2c@d0180000 {
                               status = "okay";
                        };
index 1f49d69..67d7ada 100644 (file)
                ranges = <0x40000000 0x40000000 0x80000000
                          0xd0000000 0xd0000000 0x30000000>;
 
-               pinmux@b3000000 {
+               pinmux: pinmux@b3000000 {
                        compatible = "st,spear320-pinmux";
                        reg = <0xb3000000 0x1000>;
+                       #gpio-range-cells = <2>;
                };
 
                clcd@90000000 {
                                reg = <0xa4000000 0x1000>;
                                status = "disabled";
                        };
+
+                       gpiopinctrl: gpio@b3000000 {
+                               compatible = "st,spear-plgpio";
+                               reg = <0xb3000000 0x1000>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               gpio-ranges = <&pinmux 0 102>;
+                               status = "disabled";
+
+                               st-plgpio,ngpio = <102>;
+                               st-plgpio,enb-reg = <0x24>;
+                               st-plgpio,wdata-reg = <0x34>;
+                               st-plgpio,dir-reg = <0x44>;
+                               st-plgpio,ie-reg = <0x64>;
+                               st-plgpio,rdata-reg = <0x54>;
+                               st-plgpio,mis-reg = <0x84>;
+                               st-plgpio,eit-reg = <0x94>;
+                       };
                };
        };
 };
index 67bc571..b175577 100644 (file)
@@ -111,6 +111,7 @@ CONFIG_I2C=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
+CONFIG_PINCTRL_AT91=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_AT91SAM9X_WATCHDOG=y
index 0436242..e34c1bd 100644 (file)
@@ -494,8 +494,17 @@ endif
 
 comment "Generic Board Type"
 
+config MACH_AT91RM9200_DT
+       bool "Atmel AT91RM9200 Evaluation Kits with device-tree support"
+       depends on SOC_AT91RM9200
+       select USE_OF
+       help
+         Select this if you want to experiment device-tree with
+         an Atmel RM9200 Evaluation Kit.
+
 config MACH_AT91SAM_DT
        bool "Atmel AT91SAM Evaluation Kits with device-tree support"
+       depends on SOC_AT91SAM9
        select USE_OF
        help
          Select this if you want to experiment device-tree with
index 3bb7a51..b38a1dc 100644 (file)
@@ -88,6 +88,7 @@ obj-$(CONFIG_MACH_SNAPPER_9260)       += board-snapper9260.o
 obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
 
 # AT91SAM board with device-tree
+obj-$(CONFIG_MACH_AT91RM9200_DT) += board-rm9200-dt.o
 obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
 
 # AT91X40 board-specific support
index 5269825..6cceb42 100644 (file)
@@ -194,6 +194,24 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_ID("pioB", &pioB_clk),
        CLKDEV_CON_ID("pioC", &pioC_clk),
        CLKDEV_CON_ID("pioD", &pioD_clk),
+       /* usart lookup table for DT entries */
+       CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
+       CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
+       CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
+       CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
+       CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
+       /* tc lookup table for DT entries */
+       CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
+       CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
+       CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
+       CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
+       CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
+       CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
+       CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -361,10 +379,10 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
        0       /* Advanced Interrupt Controller (IRQ6) */
 };
 
-struct at91_init_soc __initdata at91rm9200_soc = {
+AT91_SOC_START(rm9200)
        .map_io = at91rm9200_map_io,
        .default_irq_priority = at91rm9200_default_irq_priority,
        .ioremap_registers = at91rm9200_ioremap_registers,
        .register_clocks = at91rm9200_register_clocks,
        .init = at91rm9200_initialize,
-};
+AT91_SOC_END
index aaa443b..cafe988 100644 (file)
@@ -24,6 +24,9 @@
 #include <linux/irq.h>
 #include <linux/clockchips.h>
 #include <linux/export.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/mach/time.h>
 
@@ -91,7 +94,8 @@ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
 static struct irqaction at91rm9200_timer_irq = {
        .name           = "at91_tick",
        .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-       .handler        = at91rm9200_timer_interrupt
+       .handler        = at91rm9200_timer_interrupt,
+       .irq            = NR_IRQS_LEGACY + AT91_ID_SYS,
 };
 
 static cycle_t read_clk32k(struct clocksource *cs)
@@ -179,8 +183,60 @@ static struct clock_event_device clkevt = {
 void __iomem *at91_st_base;
 EXPORT_SYMBOL_GPL(at91_st_base);
 
+#ifdef CONFIG_OF
+static struct of_device_id at91rm9200_st_timer_ids[] = {
+       { .compatible = "atmel,at91rm9200-st" },
+       { /* sentinel */ }
+};
+
+static int __init of_at91rm9200_st_init(void)
+{
+       struct device_node *np;
+       int ret;
+
+       np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
+       if (!np)
+               goto err;
+
+       at91_st_base = of_iomap(np, 0);
+       if (!at91_st_base)
+               goto node_err;
+
+       /* Get the interrupts property */
+       ret = irq_of_parse_and_map(np, 0);
+       if (!ret)
+               goto ioremap_err;
+       at91rm9200_timer_irq.irq = ret;
+
+       of_node_put(np);
+
+       return 0;
+
+ioremap_err:
+       iounmap(at91_st_base);
+node_err:
+       of_node_put(np);
+err:
+       return -EINVAL;
+}
+#else
+static int __init of_at91rm9200_st_init(void)
+{
+       return -EINVAL;
+}
+#endif
+
 void __init at91rm9200_ioremap_st(u32 addr)
 {
+#ifdef CONFIG_OF
+       struct device_node *np;
+
+       np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
+       if (np) {
+               of_node_put(np);
+               return;
+       }
+#endif
        at91_st_base = ioremap(addr, 256);
        if (!at91_st_base)
                panic("Impossible to ioremap ST\n");
@@ -191,13 +247,16 @@ void __init at91rm9200_ioremap_st(u32 addr)
  */
 void __init at91rm9200_timer_init(void)
 {
+       /* For device tree enabled device: initialize here */
+       of_at91rm9200_st_init();
+
        /* Disable all timer interrupts, and clear any pending ones */
        at91_st_write(AT91_ST_IDR,
                AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
        at91_st_read(AT91_ST_SR);
 
        /* Make IRQs happen for the system timer */
-       setup_irq(NR_IRQS_LEGACY + AT91_ID_SYS, &at91rm9200_timer_irq);
+       setup_irq(at91rm9200_timer_irq.irq, &at91rm9200_timer_irq);
 
        /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
         * directly for the clocksource and all clockevents, after adjusting
index f820261..c9e029e 100644 (file)
@@ -230,11 +230,15 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
        CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
        CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
+       CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
        CLKDEV_CON_ID("pioA", &pioA_clk),
        CLKDEV_CON_ID("pioB", &pioB_clk),
        CLKDEV_CON_ID("pioC", &pioC_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -390,10 +394,10 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
        0,      /* Advanced Interrupt Controller */
 };
 
-struct at91_init_soc __initdata at91sam9260_soc = {
+AT91_SOC_START(sam9260)
        .map_io = at91sam9260_map_io,
        .default_irq_priority = at91sam9260_default_irq_priority,
        .ioremap_registers = at91sam9260_ioremap_registers,
        .register_clocks = at91sam9260_register_clocks,
        .init = at91sam9260_initialize,
-};
+AT91_SOC_END
index 04295c0..4d262f3 100644 (file)
@@ -334,10 +334,10 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
        0,      /* Advanced Interrupt Controller */
 };
 
-struct at91_init_soc __initdata at91sam9261_soc = {
+AT91_SOC_START(sam9261)
        .map_io = at91sam9261_map_io,
        .default_irq_priority = at91sam9261_default_irq_priority,
        .ioremap_registers = at91sam9261_ioremap_registers,
        .register_clocks = at91sam9261_register_clocks,
        .init = at91sam9261_initialize,
-};
+AT91_SOC_END
index d6f9c23..ed390f6 100644 (file)
@@ -211,7 +211,14 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
        CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
        CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
+       CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
+       CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
        CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -365,10 +372,10 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
        0,      /* Advanced Interrupt Controller (IRQ1) */
 };
 
-struct at91_init_soc __initdata at91sam9263_soc = {
+AT91_SOC_START(sam9263)
        .map_io = at91sam9263_map_io,
        .default_irq_priority = at91sam9263_default_irq_priority,
        .ioremap_registers = at91sam9263_ioremap_registers,
        .register_clocks = at91sam9263_register_clocks,
        .init = at91sam9263_initialize,
-};
+AT91_SOC_END
index 84af1b5..c5c2acc 100644 (file)
@@ -256,10 +256,18 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
        CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
        CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
+       CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
+       CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
        CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
        CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
+
        CLKDEV_CON_ID("pioA", &pioA_clk),
        CLKDEV_CON_ID("pioB", &pioB_clk),
        CLKDEV_CON_ID("pioC", &pioC_clk),
@@ -409,10 +417,10 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
        0,      /* Advanced Interrupt Controller (IRQ0) */
 };
 
-struct at91_init_soc __initdata at91sam9g45_soc = {
+AT91_SOC_START(sam9g45)
        .map_io = at91sam9g45_map_io,
        .default_irq_priority = at91sam9g45_default_irq_priority,
        .ioremap_registers = at91sam9g45_ioremap_registers,
        .register_clocks = at91sam9g45_register_clocks,
        .init = at91sam9g45_initialize,
-};
+AT91_SOC_END
index 732d3d3..70b3a99 100644 (file)
@@ -168,13 +168,14 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
        CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
        CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
+       CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk),
        CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
        CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
        CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
-       CLKDEV_CON_ID("pioA", &pioAB_clk),
-       CLKDEV_CON_ID("pioB", &pioAB_clk),
-       CLKDEV_CON_ID("pioC", &pioCD_clk),
-       CLKDEV_CON_ID("pioD", &pioCD_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
        /* additional fake clock for macb_hclk */
        CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
        CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
@@ -223,13 +224,10 @@ static void __init at91sam9n12_map_io(void)
 void __init at91sam9n12_initialize(void)
 {
        at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
-
-       /* Register GPIO subsystem (using DT) */
-       at91_gpio_init(NULL, 0);
 }
 
-struct at91_init_soc __initdata at91sam9n12_soc = {
+AT91_SOC_START(sam9n12)
        .map_io = at91sam9n12_map_io,
        .register_clocks = at91sam9n12_register_clocks,
        .init = at91sam9n12_initialize,
-};
+AT91_SOC_END
index 72e9084..cbe72e4 100644 (file)
@@ -338,10 +338,10 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
        0,      /* Advanced Interrupt Controller */
 };
 
-struct at91_init_soc __initdata at91sam9rl_soc = {
+AT91_SOC_START(sam9rl)
        .map_io = at91sam9rl_map_io,
        .default_irq_priority = at91sam9rl_default_irq_priority,
        .ioremap_registers = at91sam9rl_ioremap_registers,
        .register_clocks = at91sam9rl_register_clocks,
        .init = at91sam9rl_initialize,
-};
+AT91_SOC_END
index e503538..3c729f0 100644 (file)
@@ -229,15 +229,17 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
        CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
        CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
+       CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
+       CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
        CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
        CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
        CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
        CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
        CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
-       CLKDEV_CON_ID("pioA", &pioAB_clk),
-       CLKDEV_CON_ID("pioB", &pioAB_clk),
-       CLKDEV_CON_ID("pioC", &pioCD_clk),
-       CLKDEV_CON_ID("pioD", &pioCD_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
+       CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
        /* additional fake clock for macb_hclk */
        CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
        CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
@@ -313,18 +315,11 @@ static void __init at91sam9x5_map_io(void)
        at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
 }
 
-void __init at91sam9x5_initialize(void)
-{
-       /* Register GPIO subsystem (using DT) */
-       at91_gpio_init(NULL, 0);
-}
-
 /* --------------------------------------------------------------------
  *  Interrupt initialization
  * -------------------------------------------------------------------- */
 
-struct at91_init_soc __initdata at91sam9x5_soc = {
+AT91_SOC_START(sam9x5)
        .map_io = at91sam9x5_map_io,
        .register_clocks = at91sam9x5_register_clocks,
-       .init = at91sam9x5_initialize,
-};
+AT91_SOC_END
index e8f45c4..3b6a948 100644 (file)
@@ -30,8 +30,6 @@
 static const struct of_device_id irq_of_match[] __initconst = {
 
        { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
-       { .compatible = "atmel,at91rm9200-gpio", .data = at91_gpio_of_irq_setup },
-       { .compatible = "atmel,at91sam9x5-gpio", .data = at91_gpio_of_irq_setup },
        { /*sentinel*/ }
 };
 
diff --git a/arch/arm/mach-at91/board-rm9200-dt.c b/arch/arm/mach-at91/board-rm9200-dt.c
new file mode 100644 (file)
index 0000000..5f9ce3d
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ *  Setup code for AT91RM9200 Evaluation Kits with Device Tree support
+ *
+ *  Copyright (C) 2011 Atmel,
+ *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *                2012 Joachim Eastwood <manabian@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/setup.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include "at91_aic.h"
+#include "generic.h"
+
+
+static const struct of_device_id irq_of_match[] __initconst = {
+       { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
+       { /*sentinel*/ }
+};
+
+static void __init at91rm9200_dt_init_irq(void)
+{
+       of_irq_init(irq_of_match);
+}
+
+static void __init at91rm9200_dt_device_init(void)
+{
+       of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *at91rm9200_dt_board_compat[] __initdata = {
+       "atmel,at91rm9200",
+       NULL
+};
+
+DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
+       .timer          = &at91rm9200_timer,
+       .map_io         = at91_map_io,
+       .handle_irq     = at91_aic_handle_irq,
+       .init_early     = at91rm9200_dt_initialize,
+       .init_irq       = at91rm9200_dt_init_irq,
+       .init_machine   = at91rm9200_dt_device_init,
+       .dt_compat      = at91rm9200_dt_board_compat,
+MACHINE_END
index b62f560..fc593d6 100644 (file)
@@ -20,6 +20,7 @@ extern void __init at91_init_sram(int bank, unsigned long base,
 extern void __init at91rm9200_set_type(int type);
 extern void __init at91_initialize(unsigned long main_clock);
 extern void __init at91x40_initialize(unsigned long main_clock);
+extern void __init at91rm9200_dt_initialize(void);
 extern void __init at91_dt_initialize(void);
 
  /* Interrupts */
index be42cf0..c5d7e1e 100644 (file)
@@ -23,8 +23,6 @@
 #include <linux/io.h>
 #include <linux/irqdomain.h>
 #include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/of_gpio.h>
 
 #include <asm/mach/irq.h>
 
@@ -33,6 +31,8 @@
 
 #include "generic.h"
 
+#define MAX_NB_GPIO_PER_BANK   32
+
 struct at91_gpio_chip {
        struct gpio_chip        chip;
        struct at91_gpio_chip   *next;          /* Bank sharing same clock */
@@ -46,6 +46,7 @@ struct at91_gpio_chip {
 
 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
 
+static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
@@ -55,26 +56,27 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip,
                                        unsigned offset);
 static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
 
-#define AT91_GPIO_CHIP(name, nr_gpio)                                  \
+#define AT91_GPIO_CHIP(name)                                           \
        {                                                               \
                .chip = {                                               \
                        .label            = name,                       \
+                       .request          = at91_gpiolib_request,       \
                        .direction_input  = at91_gpiolib_direction_input, \
                        .direction_output = at91_gpiolib_direction_output, \
                        .get              = at91_gpiolib_get,           \
                        .set              = at91_gpiolib_set,           \
                        .dbg_show         = at91_gpiolib_dbg_show,      \
                        .to_irq           = at91_gpiolib_to_irq,        \
-                       .ngpio            = nr_gpio,                    \
+                       .ngpio            = MAX_NB_GPIO_PER_BANK,       \
                },                                                      \
        }
 
 static struct at91_gpio_chip gpio_chip[] = {
-       AT91_GPIO_CHIP("pioA", 32),
-       AT91_GPIO_CHIP("pioB", 32),
-       AT91_GPIO_CHIP("pioC", 32),
-       AT91_GPIO_CHIP("pioD", 32),
-       AT91_GPIO_CHIP("pioE", 32),
+       AT91_GPIO_CHIP("pioA"),
+       AT91_GPIO_CHIP("pioB"),
+       AT91_GPIO_CHIP("pioC"),
+       AT91_GPIO_CHIP("pioD"),
+       AT91_GPIO_CHIP("pioE"),
 };
 
 static int gpio_banks;
@@ -89,7 +91,7 @@ static unsigned long at91_gpio_caps;
 
 static inline void __iomem *pin_to_controller(unsigned pin)
 {
-       pin /= 32;
+       pin /= MAX_NB_GPIO_PER_BANK;
        if (likely(pin < gpio_banks))
                return gpio_chip[pin].regbase;
 
@@ -98,7 +100,7 @@ static inline void __iomem *pin_to_controller(unsigned pin)
 
 static inline unsigned pin_to_mask(unsigned pin)
 {
-       return 1 << (pin % 32);
+       return 1 << (pin % MAX_NB_GPIO_PER_BANK);
 }
 
 
@@ -713,80 +715,6 @@ postcore_initcall(at91_gpio_debugfs_init);
  */
 static struct lock_class_key gpio_lock_class;
 
-#if defined(CONFIG_OF)
-static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
-                                                       irq_hw_number_t hw)
-{
-       struct at91_gpio_chip   *at91_gpio = h->host_data;
-
-       irq_set_lockdep_class(virq, &gpio_lock_class);
-
-       /*
-        * Can use the "simple" and not "edge" handler since it's
-        * shorter, and the AIC handles interrupts sanely.
-        */
-       irq_set_chip_and_handler(virq, &gpio_irqchip,
-                                handle_simple_irq);
-       set_irq_flags(virq, IRQF_VALID);
-       irq_set_chip_data(virq, at91_gpio);
-
-       return 0;
-}
-
-static struct irq_domain_ops at91_gpio_ops = {
-       .map    = at91_gpio_irq_map,
-       .xlate  = irq_domain_xlate_twocell,
-};
-
-int __init at91_gpio_of_irq_setup(struct device_node *node,
-                                    struct device_node *parent)
-{
-       struct at91_gpio_chip   *prev = NULL;
-       int                     alias_idx = of_alias_get_id(node, "gpio");
-       struct at91_gpio_chip   *at91_gpio = &gpio_chip[alias_idx];
-
-       /* Setup proper .irq_set_type function */
-       if (has_pio3())
-               gpio_irqchip.irq_set_type = alt_gpio_irq_type;
-       else
-               gpio_irqchip.irq_set_type = gpio_irq_type;
-
-       /* Disable irqs of this PIO controller */
-       __raw_writel(~0, at91_gpio->regbase + PIO_IDR);
-
-       /* Setup irq domain */
-       at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
-                                               &at91_gpio_ops, at91_gpio);
-       if (!at91_gpio->domain)
-               panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
-                       at91_gpio->pioc_idx);
-
-       /* Setup chained handler */
-       if (at91_gpio->pioc_idx)
-               prev = &gpio_chip[at91_gpio->pioc_idx - 1];
-
-       /* The toplevel handler handles one bank of GPIOs, except
-        * on some SoC it can handles up to three...
-        * We only set up the handler for the first of the list.
-        */
-       if (prev && prev->next == at91_gpio)
-               return 0;
-
-       at91_gpio->pioc_virq = irq_create_mapping(irq_find_host(parent),
-                                                       at91_gpio->pioc_hwirq);
-       irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
-       irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
-
-       return 0;
-}
-#else
-int __init at91_gpio_of_irq_setup(struct device_node *node,
-                                    struct device_node *parent)
-{
-       return -EINVAL;
-}
-#endif
-
 /*
  * irqdomain initialization: pile up irqdomains on top of AIC range
  */
@@ -862,6 +790,16 @@ void __init at91_gpio_irq_setup(void)
 }
 
 /* gpiolib support */
+static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
+{
+       struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+       void __iomem *pio = at91_gpio->regbase;
+       unsigned mask = 1 << offset;
+
+       __raw_writel(mask, pio + PIO_PER);
+       return 0;
+}
+
 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
                                        unsigned offset)
 {
@@ -975,81 +913,11 @@ err:
        return -EINVAL;
 }
 
-#ifdef CONFIG_OF_GPIO