ARM: tegra11: clock: Use XUSB clock source integer divisors
Alex Frid [Wed, 5 Dec 2012 00:36:36 +0000 (16:36 -0800)]
Only integer divisors are allowed from now on for XUSB clock
sources.

Change-Id: I2f0888d4ab36f81196ecdcaadc2a7e27e689207d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/168559
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c

index 01c8490..edb9196 100644 (file)
@@ -6410,11 +6410,11 @@ struct clk tegra_list_clks[] = {
 #define XUSB_ID "tegra_xhci"
 
 static struct clk tegra_xusb_source_clks[] = {
-       PERIPH_CLK("xusb_host_src",     XUSB_ID, "host_src",    143,    0x600,  120000000, mux_clkm_pllp_pllc_pllre,    MUX | MUX8 | DIV_U71 | PERIPH_NO_RESET | PERIPH_ON_APB),
-       PERIPH_CLK("xusb_falcon_src",   XUSB_ID, "falcon_src",  143,    0x604,  350000000, mux_clkm_pllp_pllc_pllre,    MUX | MUX8 | DIV_U71 | PERIPH_NO_RESET),
-       PERIPH_CLK("xusb_fs_src",       XUSB_ID, "fs_src",      143,    0x608,   48000000, mux_clkm_48M_pllp_480M,      MUX | DIV_U71 | PERIPH_NO_RESET),
-       PERIPH_CLK("xusb_ss_src",       XUSB_ID, "ss_src",      143,    0x610,  120000000, mux_clkm_pllre_clk32_480M_pllc_ref,  MUX | MUX8 | DIV_U71 | PERIPH_NO_RESET),
-       PERIPH_CLK("xusb_dev_src",      XUSB_ID, "dev_src",     95,     0x60c,  120000000, mux_clkm_pllp_pllc_pllre,    MUX | MUX8 | DIV_U71 | PERIPH_NO_RESET | PERIPH_ON_APB),
+       PERIPH_CLK("xusb_host_src",     XUSB_ID, "host_src",    143,    0x600,  120000000, mux_clkm_pllp_pllc_pllre,    MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
+       PERIPH_CLK("xusb_falcon_src",   XUSB_ID, "falcon_src",  143,    0x604,  350000000, mux_clkm_pllp_pllc_pllre,    MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
+       PERIPH_CLK("xusb_fs_src",       XUSB_ID, "fs_src",      143,    0x608,   48000000, mux_clkm_48M_pllp_480M,      MUX | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
+       PERIPH_CLK("xusb_ss_src",       XUSB_ID, "ss_src",      143,    0x610,  120000000, mux_clkm_pllre_clk32_480M_pllc_ref,  MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
+       PERIPH_CLK("xusb_dev_src",      XUSB_ID, "dev_src",     95,     0x60c,  120000000, mux_clkm_pllp_pllc_pllre,    MUX | MUX8 | DIV_U71 |  DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
        {
                .name      = "xusb_hs_src",
                .lookup    = {