mmc: tegra: Use SDR104 UHS mode for SDR50 mode
Pavan Kunapuli [Mon, 13 Jan 2014 10:35:26 +0000 (15:35 +0530)]
Program SDR104 mode in the UHS_MODE_SEL register for SDR50 mode as well.
This is required for better timing and reliable transfers in SDR50 mode.

Bug 1423423

Reviewed-on: http://git-master/r/360182
(cherry picked from commit 52b973fb21acc16a5b6a05d321c6e425a2f63f9a)

Change-Id: I7e7b24fa2849daf83840aef4641e051b927e34a1
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/363813
(cherry picked from commit b9e63eb49cb2dcb6fa92c5382d3760b5182c033c)
Reviewed-on: http://git-master/r/410191
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

drivers/mmc/host/sdhci-tegra.c

index 1b62946..5a30f1a 100644 (file)
@@ -903,9 +903,11 @@ static int tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
 
        ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 
-       /* Select Bus Speed Mode for host */
-       /* For HS200 we need to set UHS_MODE_SEL to SDR104.
+       /* Select Bus Speed Mode for host
+        * For HS200 we need to set UHS_MODE_SEL to SDR104.
         * It works as SDR 104 in SD 4-bit mode and HS200 in eMMC 8-bit mode.
+        * SDR50 mode timing seems to have issues. Programming SDR104
+         * mode for SDR50 mode for reliable transfers over interface.
         */
        ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
        switch (uhs) {
@@ -916,7 +918,7 @@ static int tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
                ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
                break;
        case MMC_TIMING_UHS_SDR50:
-               ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
+               ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
                break;
        case MMC_TIMING_UHS_SDR104:
        case MMC_TIMING_MMC_HS200: