tegra: bonaire: set SDMMC max clk support to 26MHz
rrajk [Mon, 18 Feb 2013 06:51:51 +0000 (11:51 +0530)]
As 26MHz supply is available to SDMMC controller,
this hack is necessary to handle ambiguity of clk setting
for SDMMC controller. Setting to 26MHZ is handled in our driver

Bug 1218505

Change-Id: I049feb7515c642e6e09c3066ebfb2ce3d1fa96a2
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/201623
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

arch/arm/mach-tegra/board-bonaire.c

index 0610579..4af0340 100644 (file)
@@ -133,6 +133,9 @@ static __initdata struct tegra_clk_init_table bonaire_clk_init_table[] = {
        { "uartc",      "clk_m",        13000000,       true},
        { "uartd",      "clk_m",        13000000,       true},
        { "uarte",      "clk_m",        13000000,       true},
+       { "sdmmc1",     "clk_m",        26000000,       false},
+       { "sdmmc3",     "clk_m",        26000000,       false},
+       { "sdmmc4",     "clk_m",        26000000,       false},
        { "pll_m",      NULL,           0,              true},
        { "blink",      "clk_32k",      32768,          false},
        { "pll_p_out4", "pll_p",        24000000,       true },