arm: tegra: ardbeg: Support E1792
Seema Khowala [Tue, 6 Aug 2013 23:26:14 +0000 (16:26 -0700)]
E1792 is same as Sheild E1780 SKU1000 except
the Memory.E1792 has LPDDR3(EDFA164A2MA-JD-F,
LPDDR3 x32, 933Mhz, 16Gb) instead.
Default DDR voltage for E1733 and E1735 pmu
is 1.35V but lpddr3 supports 1.2V

Bug 1339736

Change-Id: Ie1e23e3512876940349ee6c4c915c890b5ebfdad
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/263470
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

arch/arm/mach-tegra/board-ardbeg-power.c
arch/arm/mach-tegra/tegra-board-id.h

index 10829af..6ccdfea 100644 (file)
@@ -362,7 +362,7 @@ int __init ardbeg_as3722_regulator_init(void)
 {
        void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
        u32 pmc_ctrl;
-
+       struct board_info board_info;
 
        /* AS3722: Normal state of INT request line is LOW.
         * configure the power management controller to trigger PMU
@@ -386,6 +386,13 @@ int __init ardbeg_as3722_regulator_init(void)
        as3722_sd1_reg_pdata.oc_trip_thres_perphase = 2500;
        as3722_sd1_reg_pdata.oc_alarm_thres_perphase = 0;
 
+       tegra_get_board_info(&board_info);
+       if (board_info.board_id == BOARD_E1792) {
+               /*Default DDR voltage is 1.35V but lpddr3 supports 1.2V*/
+               as3722_sd2_reg_idata.constraints.min_uV = 1200000;
+               as3722_sd2_reg_idata.constraints.max_uV = 1200000;
+       }
+
        pr_info("%s: i2c_register_board_info\n", __func__);
        i2c_register_board_info(4, as3722_regulators,
                        ARRAY_SIZE(as3722_regulators));
@@ -600,6 +607,7 @@ int __init ardbeg_tps65913_regulator_init(void)
        void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
        u32 pmc_ctrl;
        int i;
+       struct board_info board_info;
 
        /* TPS65913: Normal state of INT request line is LOW.
         * configure the power management controller to trigger PMU
@@ -621,6 +629,12 @@ int __init ardbeg_tps65913_regulator_init(void)
        /* Set vdd_gpu init uV to 1V */
        reg_idata_ti913_smps123.constraints.init_uV = 900000;
 
+       tegra_get_board_info(&board_info);
+       if (board_info.board_id == BOARD_E1792) {
+               /*Default DDR voltage is 1.35V but lpddr3 supports 1.2V*/
+               reg_idata_ti913_smps7.constraints.max_uV = 1200000;
+       }
+
        i2c_register_board_info(4, palma_ti913_device,
                        ARRAY_SIZE(palma_ti913_device));
        return 0;
index 3e65f3d..e229047 100644 (file)
@@ -45,6 +45,7 @@
 #define BOARD_P2560   0x0A00
 #define BOARD_E1780   0x06F4
 #define BOARD_E1781   0x06F5
+#define BOARD_E1792   0x0700
 #define BOARD_PM358   0x0166
 #define BOARD_PM359   0x0167
 #define BOARD_PM363   0x016B