ARM: tegra: detect platform at runtime.
Chetan Kumar N G [Mon, 17 Jun 2013 21:03:32 +0000 (14:03 -0700)]
This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: Ide06d8c77409b6f57d13b0a2055736092096ea7c
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/252559
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

arch/arm/mach-tegra/board-bonaire-power.c
arch/arm/mach-tegra/board-bonaire-sdhci.c
arch/arm/mach-tegra/board-bonaire.c
arch/arm/mach-tegra/pcie.c
arch/arm/mach-tegra/pinmux-t12-tables.c

index b8c9c26..9460858 100644 (file)
@@ -207,7 +207,6 @@ int __init bonaire_suspend_init(void)
        return 0;
 }
 
-#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
 
 #define COSIM_SHUTDOWN_REG         0x538f0ffc
 
@@ -224,4 +223,3 @@ int __init bonaire_power_off_init(void)
        pm_power_off = bonaire_power_off;
        return 0;
 }
-#endif
index 37ff445..e0bd8a3 100644 (file)
@@ -29,7 +29,7 @@
 #include <mach/irqs.h>
 #include <mach/iomap.h>
 #include <mach/sdhci.h>
-
+#include <mach/hardware.h>
 #include "gpio-names.h"
 #include "board.h"
 
@@ -92,11 +92,6 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
        .cd_gpio = -1,
        .wp_gpio = -1,
        .power_gpio = -1,
-#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
-       .mmc_data = {
-               .built_in = 1,
-       }
-#endif
 /*     .max_clk = 12000000, */
 };
 
@@ -104,11 +99,6 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data1 = {
        .cd_gpio = -1,
        .wp_gpio = -1,
        .power_gpio = -1,
-#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
-       .mmc_data = {
-               .built_in = 1,
-       }
-#endif
 /*     .max_clk = 12000000, */
 };
 
@@ -116,11 +106,6 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
        .cd_gpio = BONAIRE_SD_CD,
        .wp_gpio = BONAIRE_SD_WP,
        .power_gpio = -1,
-#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
-       .mmc_data = {
-               .built_in = 1,
-       }
-#endif
 /*     .max_clk = 12000000, */
 };
 
@@ -129,11 +114,6 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
        .wp_gpio = -1,
        .power_gpio = -1,
        .is_8bit = 1,
-#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
-       .mmc_data = {
-               .built_in = 1,
-       }
-#endif
 /*     .max_clk = 12000000, */
 };
 
@@ -179,6 +159,12 @@ static struct platform_device tegra_sdhci_device3 = {
 
 int __init bonaire_sdhci_init(void)
 {
+       if (tegra_cpu_is_asim()) {
+               tegra_sdhci_platform_data0.mmc_data.built_in = 1;
+               tegra_sdhci_platform_data1.mmc_data.built_in = 1;
+               tegra_sdhci_platform_data2.mmc_data.built_in = 1;
+               tegra_sdhci_platform_data3.mmc_data.built_in = 1;
+       }
        platform_device_register(&tegra_sdhci_device3);
        platform_device_register(&tegra_sdhci_device2);
 
index 234f5c4..87bbc16 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/board-bonaire.c
  *
- * Copyright (c) 2013, NVIDIA Corporation.
+ * Copyright (C) 2013 NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -589,17 +589,14 @@ static void __init tegra_bonaire_init(void)
        tegra_soc_device_init("bonaire");
        bonaire_apbdma_init();
 
-#ifdef CONFIG_TEGRA_FPGA_PLATFORM
-       if (tegra_platform_is_qt())
+       if (tegra_platform_is_fpga() && tegra_platform_is_qt())
                debug_uart_platform_data[0].uartclk =
                                                tegra_clk_measure_input_freq();
-#endif
 
        platform_add_devices(bonaire_devices, ARRAY_SIZE(bonaire_devices));
 
-#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
-       bonaire_power_off_init();
-#endif
+       if (tegra_cpu_is_asim())
+               bonaire_power_off_init();
        tegra_io_dpd_init();
        bonaire_hs_uart_init();
        bonaire_sdhci_init();
index 10b9bd5..e600276 100644 (file)
@@ -48,6 +48,7 @@
 #include <mach/powergate.h>
 #include <mach/pci.h>
 #include <mach/tegra_usb_pad_ctrl.h>
+#include <mach/hardware.h>
 
 #include "board.h"
 #include "iomap.h"
@@ -1012,41 +1013,45 @@ static int tegra_pcie_enable_controller(void)
        val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE |
                 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK);
 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
-#ifdef CONFIG_TEGRA_FPGA_PLATFORM
-       /* FPGA supports only x2_x1 bar config */
-       val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
-#else
-       /* Extract 2 upper bits from odmdata[28:30] and */
-       /* configure T124 pcie lanes in X2_X1/X4_X1 config based on them */
-       lane_owner = tegra_get_lane_owner_info() >> 1;
-       if (lane_owner == PCIE_LANES_X2_X1)
+       if (tegra_platform_is_fpga()) {
+               /* FPGA supports only x2_x1 bar config */
                val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
-       else {
+       } else {
+               /* Extract 2 upper bits from odmdata[28:30] and configure */
+               /* T124 pcie lanes in X2_X1/X4_X1 config based on them */
+               lane_owner = tegra_get_lane_owner_info() >> 1;
+               if (lane_owner == PCIE_LANES_X2_X1)
+                       val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
+               else {
 #define BOARD_PM359    0x0167
-               int err = 0;
-               struct board_info board_info;
-
-               tegra_get_board_info(&board_info);
-               val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
-               if ((board_info.board_id == BOARD_PM359) &&
-                       (lane_owner == PCIE_LANES_X4_X1)) {
-                       /* X1 works only on ERS-S board with X4_X1 config */
-                       val &= ~AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE;
-                       /* enable x1 slot for ERS-S if all lanes are config'd for PCIe */
-                       err = gpio_request(tegra_pcie.plat_data->gpio_x1_slot,
-                                       "pcie_x1_slot");
-                       if (err < 0)
-                               pr_err("%s: pcie_x1_slot gpio_request failed %d\n",
-                                       __func__, err);
-                       err = gpio_direction_output(
+                       int err = 0;
+                       struct board_info board_info;
+
+                       tegra_get_board_info(&board_info);
+                       val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
+                       if ((board_info.board_id == BOARD_PM359) &&
+                                       (lane_owner == PCIE_LANES_X4_X1)) {
+                               /* X1 works only on ERS-S board
+                                  with X4_X1 config */
+                               val &= ~AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE;
+                               /* enable x1 slot for ERS-S if all lanes
+                                  are config'd for PCIe */
+                               err = gpio_request(
+                                     tegra_pcie.plat_data->gpio_x1_slot,
+                                     "pcie_x1_slot");
+                               if (err < 0)
+                                       pr_err("%s: pcie_x1_slot gpio_request failed %d\n",
+                                                       __func__, err);
+                               err = gpio_direction_output(
                                        tegra_pcie.plat_data->gpio_x1_slot, 1);
-                       if (err < 0)
-                               pr_err("%s: pcie_x1_slot gpio_direction_output failed %d\n",
-                                       __func__, err);
-                       gpio_set_value_cansleep(tegra_pcie.plat_data->gpio_x1_slot, 1);
+                               if (err < 0)
+                                       pr_err("%s: pcie_x1_slot gpio_direction_output failed %d\n",
+                                                       __func__, err);
+                               gpio_set_value_cansleep(
+                                       tegra_pcie.plat_data->gpio_x1_slot, 1);
+                       }
                }
        }
-#endif
 #else
        val &= ~AFI_PCIE_CONFIG_PCIEC2_DISABLE_DEVICE;
        val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
@@ -1058,65 +1063,67 @@ static int tegra_pcie_enable_controller(void)
        afi_writel(val, AFI_FUSE);
 
        timeout = 0;
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
+       if (!tegra_platform_is_fpga()) {
 #ifndef CONFIG_ARCH_TEGRA_12x_SOC
-       /* override IDDQ to 1 on all 4 lanes */
-       val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L;
-       pads_writel(val, PADS_CTL);
-
-       /*
-        * set up PHY PLL inputs select PLLE output as refclock,
-        * set pll TX clock ref to div10 (not div5)
-        * set pll ref clock buf to enable.
-        */
-       val = pads_readl(PADS_PLL_CTL);
-       val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
+               /* override IDDQ to 1 on all 4 lanes */
+               val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L;
+               pads_writel(val, PADS_CTL);
+
+               /*
+                * set up PHY PLL inputs select PLLE output as refclock,
+                * set pll TX clock ref to div10 (not div5)
+                * set pll ref clock buf to enable.
+                */
+               val = pads_readl(PADS_PLL_CTL);
+               val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
-       val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10);
+               val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML
+                                | PADS_PLL_CTL_TXCLKREF_DIV10);
 #else
-       val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_BUF_EN);
+               val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML
+                                | PADS_PLL_CTL_TXCLKREF_BUF_EN);
 #endif
-       val |= PADS_PLL_CTL_RST_B4SM;
-       pads_writel(val, PADS_PLL_CTL);
-
-       /* put PLL into reset  */
-       val = pads_readl(PADS_PLL_CTL) & ~PADS_PLL_CTL_RST_B4SM;
-       pads_writel(val, PADS_PLL_CTL);
-
-       /* take PLL out of reset  */
-       val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM;
-       pads_writel(val, PADS_PLL_CTL);
-
-       /*
-        * Hack, set the clock voltage to the DEFAULT provided by hw folks.
-        * This doesn't exist in the documentation
-        */
-       pads_writel(0xfa5cfa5c, 0xc8);
-       pads_writel(0x0000FA5C, PADS_REFCLK_CFG1);
-
-       /* Wait for the PLL to lock */
-       timeout = 300;
-       do {
-               val = pads_readl(PADS_PLL_CTL);
-               usleep_range(1000, 1000);
-               if (--timeout == 0) {
-                       pr_err("Tegra PCIe error: timeout waiting for PLL\n");
-                       return -EBUSY;
-               }
-       } while (!(val & PADS_PLL_CTL_LOCKDET));
+               val |= PADS_PLL_CTL_RST_B4SM;
+               pads_writel(val, PADS_PLL_CTL);
+
+               /* put PLL into reset  */
+               val = pads_readl(PADS_PLL_CTL) & ~PADS_PLL_CTL_RST_B4SM;
+               pads_writel(val, PADS_PLL_CTL);
+
+               /* take PLL out of reset  */
+               val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM;
+               pads_writel(val, PADS_PLL_CTL);
+
+               /*
+                * Hack, set the clock voltage to the DEFAULT provided
+                * by hw folks. This doesn't exist in the documentation
+                */
+               pads_writel(0xfa5cfa5c, 0xc8);
+               pads_writel(0x0000FA5C, PADS_REFCLK_CFG1);
+
+               /* Wait for the PLL to lock */
+               timeout = 300;
+               do {
+                       val = pads_readl(PADS_PLL_CTL);
+                       usleep_range(1000, 1000);
+                       if (--timeout == 0) {
+                               pr_err("Tegra PCIe error: timeout waiting for PLL\n");
+                               return -EBUSY;
+                       }
+               } while (!(val & PADS_PLL_CTL_LOCKDET));
 
-       /* turn off IDDQ override */
-       val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L;
-       pads_writel(val, PADS_CTL);
+               /* turn off IDDQ override */
+               val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L;
+               pads_writel(val, PADS_CTL);
 #else
-       /* T124 PCIe pad programming is moved to XUSB_PADCTL space */
-       ret = pcie_phy_pad_enable(lane_owner);
-       if (ret) {
-               pr_err("%s unable to initalize pads\n", __func__);
-               return ret;
-       }
-#endif
+               /* T124 PCIe pad programming is moved to XUSB_PADCTL space */
+               ret = pcie_phy_pad_enable(lane_owner);
+               if (ret) {
+                       pr_err("%s unable to initalize pads\n", __func__);
+                       return ret;
+               }
 #endif
+       }
 
        /* Take the PCIe interface module out of reset */
        tegra_periph_reset_deassert(tegra_pcie.pcie_xclk);
@@ -1146,7 +1153,6 @@ static int tegra_pcie_enable_controller(void)
        return ret;
 }
 
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
 static int tegra_pcie_enable_regulators(void)
 {
        PR_FUNC_LINE;
@@ -1236,7 +1242,6 @@ static int tegra_pcie_disable_regulators(void)
 err_exit:
        return err;
 }
-#endif
 
 static int tegra_pcie_power_regate(void)
 {
@@ -1280,7 +1285,6 @@ void tegra_pcie_unmap_resources(void)
        }
 }
 
-#ifdef CONFIG_TEGRA_FPGA_PLATFORM
 static bool tegra_pcie_is_fpga_pcie(void)
 {
 #define CLK_RST_BOND_OUT_REG           0x60006078
@@ -1315,17 +1319,14 @@ static int tegra_pcie_fpga_phy_init(void)
 
        return 0;
 }
-#endif
 
 static void tegra_pcie_pme_turnoff(void)
 {
        unsigned int data;
 
        PR_FUNC_LINE;
-#ifdef CONFIG_TEGRA_FPGA_PLATFORM
-       if (!tegra_pcie_is_fpga_pcie())
+       if (tegra_platform_is_fpga() && !tegra_pcie_is_fpga_pcie())
                return;
-#endif
        data = afi_readl(AFI_PCIE_PME);
        data |= AFI_PCIE_PME_TURN_OFF;
        afi_writel(data, AFI_PCIE_PME);
@@ -1344,13 +1345,13 @@ static int tegra_pcie_power_on(void)
                goto err_exit;
        }
        tegra_pcie.pcie_power_enabled = 1;
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
-       err = tegra_pcie_enable_regulators();
-       if (err) {
-               pr_err("PCIE: Failed to enable regulators\n");
-               goto err_exit;
+       if (!tegra_platform_is_fpga()) {
+               err = tegra_pcie_enable_regulators();
+               if (err) {
+                       pr_err("PCIE: Failed to enable regulators\n");
+                       goto err_exit;
+               }
        }
-#endif
        err = tegra_pcie_power_regate();
        if (err) {
                pr_err("PCIE: Failed to power regate\n");
@@ -1361,13 +1362,13 @@ static int tegra_pcie_power_on(void)
                pr_err("PCIE: Failed to map resources\n");
                goto err_exit;
        }
-#ifdef CONFIG_TEGRA_FPGA_PLATFORM
-       err = tegra_pcie_fpga_phy_init();
-       if (err) {
-               pr_err("PCIE: Failed to initialize FPGA Phy\n");
-               goto err_exit;
+       if (tegra_platform_is_fpga()) {
+               err = tegra_pcie_fpga_phy_init();
+               if (err) {
+                       pr_err("PCIE: Failed to initialize FPGA Phy\n");
+                       goto err_exit;
+               }
        }
-#endif
 
 err_exit:
        return err;
@@ -1394,11 +1395,11 @@ static int tegra_pcie_power_off(void)
        if (err)
                goto err_exit;
 
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
-       err = tegra_pcie_disable_regulators();
-       if (err)
-               goto err_exit;
-#endif
+       if (!tegra_platform_is_fpga()) {
+               err = tegra_pcie_disable_regulators();
+               if (err)
+                       goto err_exit;
+       }
        tegra_pcie.pcie_power_enabled = 0;
 err_exit:
        return err;
@@ -1901,6 +1902,8 @@ static struct platform_driver __initdata tegra_pcie_driver = {
 
 static int __init tegra_pcie_init_driver(void)
 {
+       if (tegra_cpu_is_asim())
+               return 0;
        return platform_driver_register(&tegra_pcie_driver);
 }
 
index 45c723d..481dccd 100644 (file)
@@ -32,7 +32,7 @@
 
 #include <mach/pinmux.h>
 #include <mach/pinmux-t12.h>
-
+#include <mach/hardware.h>
 #include "gpio-names.h"
 #include "iomap.h"
 
@@ -144,9 +144,8 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
                .ioreset_bit = 8,                               \
        }
 
-#ifdef CONFIG_TEGRA_FPGA_PLATFORM
 /* !!!FIXME!!! FILL IN fSafe COLUMN IN TABLE ....... */
-#define PINGROUPS      \
+#define PINGROUPS_FPGA \
        /*       NAME             GPIO          VDD         f0          f1          f2          f3          fSafe       io      reg */\
        PINGROUP(ULPI_DATA0,      PO1,          BB,         SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3000),\
        PINGROUP(ULPI_DATA1,      PO2,          BB,         SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3004),\
@@ -323,7 +322,6 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
        PINGROUP(USB_VBUS_EN0,    PN4,          SYS,        RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x33f4),\
        PINGROUP(USB_VBUS_EN1,    PM5,          SYS,        RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x33f8),\
 
-#else
 
 /* !!!FIXME!!! FILL IN fSafe COLUMN IN TABLE ....... */
 #define PINGROUPS      \
@@ -520,13 +518,16 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
        PINGROUP(GPIO_PFF2,     PFF2,   PEXCTL, SATA,           RSVD1,          RSVD2,          RSVD3,          RSVD1,          INPUT,  0x3418),\
        PINGROUP(DP_HPD,        PFF0,   HV,     DP,             RSVD1,          RSVD2,          RSVD3,          RSVD,           INPUT,  0x3430),\
 
-#endif
 
-const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
-       PINGROUPS
+const struct tegra_pingroup_desc soc_pingroups_fpga[TEGRA_MAX_PINGROUP] = {
+       PINGROUPS_FPGA
 };
 
+const struct tegra_pingroup_desc soc_pingroups_non_fpga[TEGRA_MAX_PINGROUP] = {
+       PINGROUPS
+};
 
+const struct tegra_pingroup_desc *tegra_soc_pingroups;
 #undef PINGROUP
 
 /* HACK to workaround -1 index (for INVALID index) */
@@ -536,11 +537,13 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
 #define PINGROUP(pg_name, gpio_nr, vdd, f0, f1, f2, f3, fs, iod, reg)  \
        [TEGRA_GPIO_##gpio_nr] =  TEGRA_PINGROUP_ ##pg_name\
 
-const int gpio_to_pingroup[TEGRA_MAX_GPIO + 1] = {
-       PINGROUPS
-
+const int gpio_to_pingroup_fpga[TEGRA_MAX_GPIO + 1] = {
+       PINGROUPS_FPGA
 };
 
+const int gpio_to_pingroup_non_fpga[TEGRA_MAX_GPIO + 1] = {
+       PINGROUPS
+};
 #define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
        {                                                       \
                .pingroup = TEGRA_DRIVE_PINGROUP_##_name,       \
@@ -617,11 +620,18 @@ void tegra12x_pinmux_init(const struct tegra_pingroup_desc **pg,
                int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
                int *pgdrive_max, const int **gpiomap, int *gpiomap_max)
 {
-       *pg = tegra_soc_pingroups;
+       if (tegra_platform_is_fpga()) {
+               *pg = soc_pingroups_fpga;
+               *gpiomap = gpio_to_pingroup_fpga;
+               tegra_soc_pingroups = soc_pingroups_fpga;
+       } else {
+               *pg = soc_pingroups_non_fpga;
+               *gpiomap = gpio_to_pingroup_non_fpga;
+               tegra_soc_pingroups = soc_pingroups_non_fpga;
+       }
        *pg_max = TEGRA_MAX_PINGROUP;
        *pgdrive = tegra_soc_drive_pingroups;
        *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
-       *gpiomap = gpio_to_pingroup;
        *gpiomap_max = TEGRA_MAX_GPIO;
 
 #ifdef CONFIG_PM_SLEEP