ARM: tegra: power: clear TLBs & BTAC after re-enabling L1 cache
Jin Qian [Wed, 24 Aug 2011 20:51:43 +0000 (13:51 -0700)]
Change-Id: Ife9154a9fe0bad9be7039fac41c86df2f0b8ebef
Reviewed-on: http://git-master/r/49053
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R976249827c7a9fdd255e6f0968a8e26d1234528f

arch/arm/mach-tegra/sleep-t20.S

index 7b80f64..e718d3d 100644 (file)
@@ -230,6 +230,13 @@ ENTRY(tegra2_sleep_wfi)
 #else
        mcr     p15, 0, r11, c1, c0, 1  @ reenable coherency
 
+       /* Invalidate the TLBs & BTAC */
+       mov     r1, #0
+       mcr     p15, 0, r1, c8, c3, 0   @ invalidate shared TLBs
+       mcr     p15, 0, r1, c7, c1, 6   @ invalidate shared BTAC
+       dsb
+       isb
+
        @ the cpu was running with coherency disabled, caches may be out of date
 #ifdef MULTI_CACHE
        mov32   r10, cpu_cache