video: tegra: dc: Add panel depth value
Chao Xu [Mon, 10 Jun 2013 21:42:30 +0000 (14:42 -0700)]
eDP cacluation needs bpp value for the panel. Add it to the board file
so we can do the right calculations.

Change-Id: I0ec7e1aa46c57d6cfacd809828e9af153e4c2eb5
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/242520

arch/arm/mach-tegra/board-bonaire-panel.c
drivers/video/tegra/dc/dp.c
drivers/video/tegra/dc/sor.c
drivers/video/tegra/dc/sor.h

index 1958ec7..1891416 100644 (file)
@@ -678,6 +678,7 @@ static struct tegra_dc_out bonaire_disp_out = {
        .n_modes        = ARRAY_SIZE(bonaire_panel_modes),
        .out_pins       = edp_out_pins,
        .n_out_pins     = ARRAY_SIZE(edp_out_pins),
+       .depth          = 18,
 #elif defined(CONFIG_TEGRA_LVDS)
        .type           = TEGRA_DC_OUT_LVDS,
 
index 5aa6f90..4a1212d 100644 (file)
@@ -510,8 +510,8 @@ static void tegra_dc_dp_dump_link_cfg(struct tegra_dc_dp_data *dp,
                cfg->support_enhanced_framing ? "Y" : "N");
        dev_info(&dp->dc->ndev->dev, "           Bandwidth           %d\n",
                cfg->max_link_bw);
-       dev_info(&dp->dc->ndev->dev, "           BPP                 %d\n",
-               cfg->bytes_per_pixel);
+       dev_info(&dp->dc->ndev->dev, "           bpp                 %d\n",
+               cfg->bits_per_pixel);
        dev_info(&dp->dc->ndev->dev, "           EnhancedFraming     %s\n\n",
                cfg->enhanced_framing ? "Y" : "N");
        dev_info(&dp->dc->ndev->dev, "           Scramble_enabled    %s\n",
@@ -592,18 +592,18 @@ static bool tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
 
 
        if (!link_rate || !cfg->lane_count || !mode->pclk ||
-               !cfg->bytes_per_pixel)
+               !cfg->bits_per_pixel)
                return false;
 
-       if (mode->pclk * cfg->bytes_per_pixel >=
+       if (mode->pclk * cfg->bits_per_pixel >=
                8 * link_rate * cfg->lane_count)
                return false;
 
        num_linkclk_line = (u32)tegra_div64(
                (u64)link_rate * mode->h_active, mode->pclk);
 
-       ratio_f = (u64)mode->pclk * cfg->bytes_per_pixel * f;
-       /* ratio_f /= 8; */
+       ratio_f = (u64)mode->pclk * cfg->bits_per_pixel * f;
+       ratio_f /= 8;
        ratio_f = tegra_div64(ratio_f, link_rate * cfg->lane_count);
 
        for (i = 64; i >= 32; --i) {
@@ -686,9 +686,9 @@ static bool tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
 
        watermark_f = tegra_div64(ratio_f * cfg->tu_size * (f - ratio_f), f);
        cfg->watermark = (u32)tegra_div64(watermark_f + lowest_neg_error_f,
-               f) + 2 * cfg->bytes_per_pixel - 1;
-       num_symbols_per_line = (mode->h_active * cfg->bytes_per_pixel) /
-               cfg->lane_count;
+               f) + cfg->bits_per_pixel / 4 - 1;
+       num_symbols_per_line = (mode->h_active * cfg->bits_per_pixel) /
+               (8 * cfg->lane_count);
        if (cfg->watermark > 30) {
                dev_dbg(&dp->dc->ndev->dev,
                        "dp: sor setting: unable to get a good tusize, "
@@ -757,7 +757,7 @@ static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
        CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH,
                        &cfg->max_link_bw));
 
-       cfg->bytes_per_pixel = dp->dc->pdata->fb->bits_per_pixel / 8;
+       cfg->bits_per_pixel = dp->dc->pdata->default_out->depth;
 
        CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
                        &dpcd_data));
index f02cdc4..db777b1 100644 (file)
@@ -791,7 +791,7 @@ static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
                }
        }
 
-       reg_val |= (sor->dc->pdata->fb->bits_per_pixel > 18) ?
+       reg_val |= (sor->dc->pdata->default_out->depth > 18) ?
                NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 :
                NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444;
 
@@ -1053,7 +1053,7 @@ void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor,
                NV_SOR_LVDS_PD_TXDA_2_ENABLE |
                NV_SOR_LVDS_PD_TXDA_1_ENABLE |
                NV_SOR_LVDS_PD_TXDA_0_ENABLE;
-       if (!conforming && (sor->dc->pdata->fb->bits_per_pixel < 18))
+       if (!conforming && (sor->dc->pdata->default_out->depth == 18))
                reg_val |= (NV_SOR_LVDS_PD_TXDA_3_DISABLE);
 
        tegra_sor_writel(sor, NV_SOR_LVDS, reg_val);
index b7c614e..810a448 100644 (file)
@@ -44,7 +44,7 @@ struct tegra_dc_dp_link_config {
        u8      max_lane_count;
        bool    downspread;
        bool    support_enhanced_framing;
-       u32     bytes_per_pixel;
+       u32     bits_per_pixel;
        bool    alt_scramber_reset_cap; /* true for eDP */
        bool    only_enhanced_framing;  /* enhanced_frame_en ignored */