ARM: tegra11: clock: Change XUSB HS clock source
Alex Frid [Wed, 3 Apr 2013 03:29:28 +0000 (20:29 -0700)]
Used XUSB SS clock (with fixed 1:2 divider) as HS clock source instead
of PLLU secondary divider.

Bug 1250832

Change-Id: Iafc24b9a9208ea4184f5a3c04deca48a24ca73c4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/216360
(cherry picked from commit 49b23eed5d9cceb4c6258e2bbb805bbab33c2c92)
Reviewed-on: http://git-master/r/221374
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/tegra11_clocks.c

index 6d86dab..63451ab 100644 (file)
@@ -267,7 +267,7 @@ static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
        { "xusb_falcon_src",    "pll_re_vco",   224000000,      false},
        { "xusb_host_src",      "pll_re_vco",   112000000,      false},
        { "xusb_ss_src",        "pll_u_480M",   120000000,      false},
-       { "xusb_hs_src",        "pll_u_60M",    60000000,       false},
+       { "xusb_hs_src",        "xusb_ss_div2", 60000000,       false},
        { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
        { "sdmmc1",     "pll_p",        48000000,       false},
        { "sdmmc3",     "pll_p",        48000000,       false},
index dfda713..05bcfe3 100644 (file)
@@ -3940,9 +3940,8 @@ static void tegra11_periph_clk_init(struct clk *c)
                c->parent = mux->input;
        } else {
                if (c->flags & PLLU) {
-                       /* for xusb_hs clock enforce PLLU source during init */
+                       /* for xusb_hs clock enforce SS div2 source */
                        val &= ~periph_clk_source_mask(c);
-                       val |= c->inputs[0].value << periph_clk_source_shift(c);
                        clk_writel_delay(val, c->reg);
                }
                c->parent = c->inputs[0].input;
@@ -6463,13 +6462,6 @@ static struct clk_mux_sel mux_clk_32k[] = {
        { 0, 0},
 };
 
-/* xusb_hs has an alternative source, that is not used - therefore, xusb_hs
-   is modeled as a single source mux */
-static struct clk_mux_sel mux_pllu_60M[] = {
-       { .input = &tegra_pll_u_60M, .value = 1},
-       { 0, 0},
-};
-
 static struct raw_notifier_head emc_rate_change_nh;
 
 static struct clk tegra_clk_emc = {
@@ -6869,30 +6861,47 @@ static struct clk tegra_xusb_source_clks[] = {
        PERIPH_CLK("xusb_fs_src",       XUSB_ID, "fs_src",      143,    0x608,   48000000, mux_clkm_48M_pllp_480M,      MUX | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
        PERIPH_CLK("xusb_ss_src",       XUSB_ID, "ss_src",      143,    0x610,  120000000, mux_clkm_pllre_clk32_480M_pllc_ref,  MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
        PERIPH_CLK("xusb_dev_src",      XUSB_ID, "dev_src",     95,     0x60c,  120000000, mux_clkm_pllp_pllc_pllre,    MUX | MUX8 | DIV_U71 |  DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
-       {
-               .name      = "xusb_hs_src",
-               .lookup    = {
-                       .dev_id    = XUSB_ID,
-                       .con_id    = "hs_src",
-               },
-               .ops       = &tegra_periph_clk_ops,
-               .reg       = 0x610,
-               .inputs    = mux_pllu_60M,
-               .flags     = PLLU | PERIPH_NO_ENB,
-               .max_rate  = 60000000,
-               .u.periph = {
-                       .src_mask  = 0x1 << 25,
-                       .src_shift = 25,
-               },
-       },
        SHARED_EMC_CLK("xusb.emc",      XUSB_ID, "emc", &tegra_clk_emc, NULL,   0,      SHARED_BW, 0),
 };
 
+static struct clk tegra_xusb_ss_div2 = {
+       .name      = "xusb_ss_div2",
+       .ops       = &tegra_clk_m_div_ops,
+       .parent    = &tegra_xusb_source_clks[3],
+       .mul       = 1,
+       .div       = 2,
+       .state     = OFF,
+       .max_rate  = 60000000,
+};
+
+static struct clk_mux_sel mux_ss_div2_pllu_60M[] = {
+       { .input = &tegra_xusb_ss_div2, .value = 0},
+       { .input = &tegra_pll_u_60M,    .value = 1},
+       { 0, 0},
+};
+
+static struct clk tegra_xusb_hs_src = {
+       .name      = "xusb_hs_src",
+       .lookup    = {
+               .dev_id    = XUSB_ID,
+               .con_id    = "hs_src",
+       },
+       .ops       = &tegra_periph_clk_ops,
+       .reg       = 0x610,
+       .inputs    = mux_ss_div2_pllu_60M,
+       .flags     = PLLU | PERIPH_NO_ENB,
+       .max_rate  = 60000000,
+       .u.periph = {
+               .src_mask  = 0x1 << 25,
+               .src_shift = 25,
+       },
+};
+
 static struct clk_mux_sel mux_xusb_host[] = {
        { .input = &tegra_xusb_source_clks[0], .value = 0},
        { .input = &tegra_xusb_source_clks[1], .value = 1},
        { .input = &tegra_xusb_source_clks[2], .value = 2},
-       { .input = &tegra_xusb_source_clks[5], .value = 5},
+       { .input = &tegra_xusb_hs_src,         .value = 5},
        { 0, 0},
 };
 
@@ -6916,7 +6925,6 @@ static struct clk tegra_xusb_coupled_clks[] = {
        PERIPH_CLK_EX("xusb_dev",  XUSB_ID, "dev",  95, 0, 120000000, mux_xusb_dev,  0, &tegra_clk_coupled_gate_ops),
 };
 
-
 #define CLK_DUPLICATE(_name, _dev, _con)               \
        {                                               \
                .name   = _name,                        \
@@ -7772,6 +7780,20 @@ static void __init tegra11_cpu_car_ops_init(void)
        tegra_cpu_car_ops = &tegra11_cpu_car_ops;
 }
 
+static void tegra11_init_xusb_clocks(void)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(tegra_xusb_source_clks); i++)
+               tegra11_init_one_clock(&tegra_xusb_source_clks[i]);
+
+       tegra11_init_one_clock(&tegra_xusb_ss_div2);
+       tegra11_init_one_clock(&tegra_xusb_hs_src);
+
+       for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
+               tegra11_init_one_clock(&tegra_xusb_coupled_clks[i]);
+}
+
 void __init tegra11x_init_clocks(void)
 {
        int i;
@@ -7794,11 +7816,7 @@ void __init tegra11x_init_clocks(void)
        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
                tegra11_init_one_clock(&tegra_clk_out_list[i]);
 
-       for (i = 0; i < ARRAY_SIZE(tegra_xusb_source_clks); i++)
-               tegra11_init_one_clock(&tegra_xusb_source_clks[i]);
-
-       for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
-               tegra11_init_one_clock(&tegra_xusb_coupled_clks[i]);
+       tegra11_init_xusb_clocks();
 
        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);