pinctrl: palmas: add dt support for palmas pincontrol driver
Laxman Dewangan [Thu, 29 Aug 2013 16:02:34 +0000 (21:02 +0530)]
Add DT support for the palmas pincontrol driver. The driver can
be instantiated from DT as well as from board files.

Modify the boardfiles to align with changes.

Change-Id: I20a6ece4016b7028b3640ba7df4b798805d9e598
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267845

12 files changed:
Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt [new file with mode: 0644]
arch/arm/mach-tegra/board-ardbeg-power.c
arch/arm/mach-tegra/board-dalmore-power.c
arch/arm/mach-tegra/board-loki-power.c
arch/arm/mach-tegra/board-macallan-power.c
arch/arm/mach-tegra/board-pluto-power.c
arch/arm/mach-tegra/board-pmu-defines.h
arch/arm/mach-tegra/board-roth-power.c
arch/arm/mach-tegra/board-tn8-power.c
drivers/pinctrl/Kconfig
drivers/pinctrl/pinctrl-palmas.c
include/linux/mfd/palmas.h

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt
new file mode 100644 (file)
index 0000000..734d9b0
--- /dev/null
@@ -0,0 +1,96 @@
+Palmas Pincontrol bindings
+
+The pins of Palmas device can be set on different option and provides
+the configuration for Pull UP/DOWN, open drain etc.
+
+Required properties:
+- compatible: It must be one of following:
+  - "ti,palmas-pinctrl" for Palma series of the pincontrol.
+  - "ti,tps65913-pinctrl" for Palma series device TPS65913.
+  - "ti,tps80036-pinctrl" for Palma series device TPS80036.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Palmas's pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+list of pins. This configuration can include the mux function to select on
+those pin(s), and various pin configuration parameters, such as pull-up,
+open drain.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+Optional properties:
+- ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode.
+       Selection primary or secondary function associated to I2C2_SCL_SCE,
+       I2C2_SDA_SDO pin/pad for DVFS1 interface
+- ti,palmas-enable-dvfs2: Enable DVFS2. Configure pins for DVFS2 mode.
+       Selection primary or secondary function associated to GPADC_START
+       and SYSEN2 pin/pad for DVFS2 interface
+
+This binding uses the following generic properties as defined in
+pinctrl-bindings.txt:
+
+Required: pins
+Options: function, bias-disable, bias-pull-up, bias-pull-down,
+        bias-pin-default, drive-open-drain.
+
+Note that many of these properties are only valid for certain specific pins.
+See the Palmas device datasheet for complete details regarding which pins
+support which functionality.
+
+Valid values for pin names are:
+       gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, gpio9,
+       gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, vac, powergood,
+       nreswarm, pwrdown, gpadc_start, reset_in, nsleep, enable1, enable2,
+       int.
+
+Valid value of function names are:
+       gpio, led, pwm, regen, sysen, clk32kgaudio, id, vbus_det, chrg_det,
+       vac, vacok, powergood, usb_psel, msecure, pwrhold, int, nreswarm,
+       simrsto, simrsti, low_vbat, wireless_chrg1, rcm, pwrdown, gpadc_start,
+       reset_in, nsleep, enable.
+
+There are 4 special functions: opt0, opt1, opt2 and opt3. If any of these
+functions is selected then directly pins register will be written with 0, 1, 2
+or 3 respectively if it is valid for that pins or list of pins.
+
+Example:
+       palmas: tps65913 {
+               ....
+               pinctrl {
+                       compatible = "ti,tps65913-pinctrl";
+                       ti,palmas-enable-dvfs1;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&palmas_pins_state>;
+
+                       palmas_pins_state: pinmux {
+                               gpio0 {
+                                       pins = "gpio0";
+                                       function = "id";
+                                       bias-pull-up;
+                               };
+
+                               vac {
+                                       pins = "vac";
+                                       function = "vacok";
+                                       bias-pull-down;
+                               };
+
+                               gpio5 {
+                                       pins = "gpio5";
+                                       function = "opt0";
+                                       drive-open-drain = <1>;
+                               };
+                       };
+               };
+               ....
+       };
index 8055912..20c9d67 100644 (file)
@@ -548,16 +548,16 @@ static struct palmas_extcon_platform_data palmas_extcon_pdata = {
 };
 
 static struct palmas_pinctrl_config palmas_ti913_pincfg[] = {
-       PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO0, ID, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO5, CLK32KGAUDIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
+       PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
+       PALMAS_PINMUX("vac", "vac", NULL, NULL),
+       PALMAS_PINMUX("gpio0", "id", NULL, NULL),
+       PALMAS_PINMUX("gpio1", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio5", "clk32kgaudio", NULL, NULL),
+       PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
 };
 
 static struct palmas_pinctrl_platform_data palmas_ti913_pinctrl_pdata = {
index 778be4b..9899e5f 100644 (file)
@@ -763,16 +763,16 @@ static struct palmas_rtc_platform_data rtc_platform = {
 };
 
 static struct palmas_pinctrl_config palmas_pincfg[] = {
-       PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO0, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO5, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
+       PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
+       PALMAS_PINMUX("vac", "vac", NULL, NULL),
+       PALMAS_PINMUX("gpio0", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio1", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio5", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
 };
 
 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
index c27cdfc..a1b793f 100644 (file)
@@ -302,16 +302,16 @@ static struct palmas_reg_init *loki_reg_init[PALMAS_NUM_REGS] = {
 };
 
 static struct palmas_pinctrl_config palmas_pincfg[] = {
-       PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO0, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO5, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
+       PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
+       PALMAS_PINMUX("vac", "vac", NULL, NULL),
+       PALMAS_PINMUX("gpio0", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio1", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio5", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
 };
 
 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
index d94a883..437f01d 100644 (file)
@@ -374,16 +374,16 @@ static struct palmas_pmic_platform_data pmic_platform = {
 };
 
 static struct palmas_pinctrl_config palmas_pincfg[] = {
-       PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO0, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO5, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
+       PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
+       PALMAS_PINMUX("vac", "vac", NULL, NULL),
+       PALMAS_PINMUX("gpio0", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio1", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio5", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
 };
 
 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
index c5f0b33..7b9fefa 100644 (file)
@@ -634,16 +634,16 @@ static struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
 };
 
 static struct palmas_pinctrl_config palmas_pincfg[] = {
-       PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO0, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO5, CLK32KGAUDIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
+       PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
+       PALMAS_PINMUX("vac", "vac", NULL, NULL),
+       PALMAS_PINMUX("gpio0", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio1", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio5", "clk32kgaudio", NULL, NULL),
+       PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
 };
 
 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
index eea7845..a4367a7 100644 (file)
 
 #define PALMAS_PINMUX(_pin, _mux, _pud, _od)                           \
 {                                                                      \
-       .pin_name = PALMAS_PIN_NAME_##_pin,                             \
-       .pin_mux_option = PALMAS_PINMUX_##_mux,                         \
-       .pin_pull_up_dn = PALMAS_PIN_CONFIG_##_pud,                     \
-       .open_drain_state = PALMAS_PIN_CONFIG_OD_##_od,                 \
+       .pin = _pin,                                                    \
+       .function = _mux,                                               \
+       .prop_bias_pull = _pud,                                         \
+       .prop_open_drain = _od,                                         \
 }
 
 #define PALMAS_REGS_PDATA(_name, _minmv, _maxmv, _supply_reg,          \
index a6596d6..3dfc182 100644 (file)
@@ -400,16 +400,16 @@ static struct palmas_pmic_platform_data pmic_platform = {
 };
 
 static struct palmas_pinctrl_config palmas_pincfg[] = {
-       PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO0, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO5, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
+       PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
+       PALMAS_PINMUX("vac", "vac", NULL, NULL),
+       PALMAS_PINMUX("gpio0", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio1", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio5", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
 };
 
 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
index ecd6106..137011d 100644 (file)
@@ -360,16 +360,16 @@ static struct palmas_reg_init *tn8_reg_init[PALMAS_NUM_REGS] = {
 };
 
 static struct palmas_pinctrl_config palmas_pincfg[] = {
-       PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO0, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO5, CLK32KGAUDIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
-       PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
+       PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
+       PALMAS_PINMUX("vac", "vac", NULL, NULL),
+       PALMAS_PINMUX("gpio0", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio1", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio5", "clk32kgaudio", NULL, NULL),
+       PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
+       PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
 };
 
 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
index 8471c4b..0a3fb59 100644 (file)
@@ -233,6 +233,8 @@ config PINCTRL_MAX77660
 config PINCTRL_PALMAS
        tristate "PALMAS Pincontrol support"
        depends on MFD_PALMAS
+       select PINMUX
+       select GENERIC_PINCONF
        help
          PALMAS is a PMIC series from TI for smartphone and tablets. This PMIC
          has some pins i.e. named as GPIOx which can be act as GPIO or in
index 6a5525a..595fd7e 100644 (file)
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  * 02111-1307, USA
  */
+
 #include <linux/delay.h>
-#include <linux/mfd/palmas.h>
 #include <linux/module.h>
+#include <linux/mfd/palmas.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinmux.h>
 #include <linux/pm.h>
 #include <linux/slab.h>
 
-struct palmas_pinctrl {
-       struct device   *dev;
-       struct palmas   *palmas;
+#include "core.h"
+#include "pinconf.h"
+#include "pinctrl-utils.h"
+
+#define PALMAS_PIN_GPIO0_ID                            0
+#define PALMAS_PIN_GPIO1_VBUS_LED1_PWM1                        1
+#define PALMAS_PIN_GPIO2_REGEN_LED2_PWM2               2
+#define PALMAS_PIN_GPIO3_CHRG_DET                      3
+#define PALMAS_PIN_GPIO4_SYSEN1                                4
+#define PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL         5
+#define PALMAS_PIN_GPIO6_SYSEN2                                6
+#define PALMAS_PIN_GPIO7_MSECURE_PWRHOLD               7
+#define PALMAS_PIN_GPIO8_SIM1RSTI                      8
+#define PALMAS_PIN_GPIO9_LOW_VBAT                      9
+#define PALMAS_PIN_GPIO10_WIRELESS_CHRG1               10
+#define PALMAS_PIN_GPIO11_RCM                          11
+#define PALMAS_PIN_GPIO12_SIM2RSTO                     12
+#define PALMAS_PIN_GPIO13                              13
+#define PALMAS_PIN_GPIO14                              14
+#define PALMAS_PIN_GPIO15_SIM2RSTI                     15
+#define PALMAS_PIN_VAC                                 16
+#define PALMAS_PIN_POWERGOOD_USB_PSEL                  17
+#define PALMAS_PIN_NRESWARM                            18
+#define PALMAS_PIN_PWRDOWN                             19
+#define PALMAS_PIN_GPADC_START                         20
+#define PALMAS_PIN_RESET_IN                            21
+#define PALMAS_PIN_NSLEEP                              22
+#define PALMAS_PIN_ENABLE1                             23
+#define PALMAS_PIN_ENABLE2                             24
+#define PALMAS_PIN_INT                                 25
+#define PALMAS_PIN_NUM                                 (PALMAS_PIN_INT + 1)
+
+struct palmas_pin_function {
+       const char *name;
+       const char * const *groups;
+       unsigned ngroups;
+};
+
+struct palmas_pctrl_chip_info {
+       struct device *dev;
+       struct pinctrl_dev *pctl;
+       struct palmas *palmas;
+       int pins_current_opt[PALMAS_PIN_NUM];
+       const struct palmas_pin_function *functions;
+       unsigned num_functions;
+       const struct palmas_pingroup *pin_groups;
+       int num_pin_groups;
+       const struct pinctrl_pin_desc *pins;
+       unsigned num_pins;
+};
+
+static const struct pinctrl_pin_desc palmas_pins_desc[] = {
+       PINCTRL_PIN(PALMAS_PIN_GPIO0_ID, "gpio0"),
+       PINCTRL_PIN(PALMAS_PIN_GPIO1_VBUS_LED1_PWM1, "gpio1"),
+       PINCTRL_PIN(PALMAS_PIN_GPIO2_REGEN_LED2_PWM2, "gpio2"),
+       PINCTRL_PIN(PALMAS_PIN_GPIO3_CHRG_DET, "gpio3"),
+       PINCTRL_PIN(PALMAS_PIN_GPIO4_SYSEN1, "gpio4"),
+       PINCTRL_PIN(PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL, "gpio5"),
+       PINCTRL_PIN(PALMAS_PIN_GPIO6_SYSEN2, "gpio6"),
+       PINCTRL_PIN(PALMAS_PIN_GPIO7_MSECURE_PWRHOLD, "gpio7"),
+       PINCTRL_PIN(PALMAS_PIN_GPIO8_SIM1RSTI, "gpio8"),
+       PINCTRL_PIN(PALMAS_PIN_GPIO9_LOW_VBAT, "gpio9"),
+       PINCTRL_PIN(PALMAS_PIN_GPIO10_WIRELESS_CHRG1, "gpio10"),
+       PINCTRL_PIN(PALMAS_PIN_GPIO11_RCM, "gpio11"),
+       PINCTRL_PIN(PALMAS_PIN_GPIO12_SIM2RSTO, "gpio12"),
+       PINCTRL_PIN(PALMAS_PIN_GPIO13, "gpio13"),
+       PINCTRL_PIN(PALMAS_PIN_GPIO14, "gpio14"),
+       PINCTRL_PIN(PALMAS_PIN_GPIO15_SIM2RSTI, "gpio15"),
+       PINCTRL_PIN(PALMAS_PIN_VAC, "vac"),
+       PINCTRL_PIN(PALMAS_PIN_POWERGOOD_USB_PSEL, "powergood"),
+       PINCTRL_PIN(PALMAS_PIN_NRESWARM, "nreswarm"),
+       PINCTRL_PIN(PALMAS_PIN_PWRDOWN, "pwrdown"),
+       PINCTRL_PIN(PALMAS_PIN_GPADC_START, "gpadc_start"),
+       PINCTRL_PIN(PALMAS_PIN_RESET_IN, "reset_in"),
+       PINCTRL_PIN(PALMAS_PIN_NSLEEP, "nsleep"),
+       PINCTRL_PIN(PALMAS_PIN_ENABLE1, "enable1"),
+       PINCTRL_PIN(PALMAS_PIN_ENABLE2, "enable2"),
+       PINCTRL_PIN(PALMAS_PIN_INT, "int"),
+};
+
+static const char * const opt0_groups[] = {
+       "gpio0",
+       "gpio1",
+       "gpio2",
+       "gpio3",
+       "gpio4",
+       "gpio5",
+       "gpio6",
+       "gpio7",
+       "gpio8",
+       "gpio9",
+       "gpio10",
+       "gpio11",
+       "gpio12",
+       "gpio13",
+       "gpio14",
+       "gpio15",
+       "vac",
+       "powergood",
+       "nreswarm",
+       "pwrdown",
+       "gpadc_start",
+       "reset_in",
+       "nsleep",
+       "enable1",
+       "enable2",
+       "int",
+};
+
+static const char * const opt1_groups[] = {
+       "gpio0",
+       "gpio1",
+       "gpio2",
+       "gpio3",
+       "gpio4",
+       "gpio5",
+       "gpio6",
+       "gpio7",
+       "gpio8",
+       "gpio9",
+       "gpio10",
+       "gpio11",
+       "gpio12",
+       "gpio15",
+       "vac",
+       "powergood",
+};
+
+static const char * const opt2_groups[] = {
+       "gpio1",
+       "gpio2",
+       "gpio5",
+       "gpio7",
+};
+
+static const char * const opt3_groups[] = {
+       "gpio1",
+       "gpio2",
+};
+
+static const char * const gpio_groups[] = {
+       "gpio0",
+       "gpio1",
+       "gpio2",
+       "gpio3",
+       "gpio4",
+       "gpio5",
+       "gpio6",
+       "gpio7",
+       "gpio8",
+       "gpio9",
+       "gpio10",
+       "gpio11",
+       "gpio12",
+       "gpio13",
+       "gpio14",
+       "gpio15",
+};
+
+static const char * const led_groups[] = {
+       "gpio1",
+       "gpio2",
+};
+
+static const char * const pwm_groups[] = {
+       "gpio1",
+       "gpio2",
+};
+
+static const char * const regen_groups[] = {
+       "gpio2",
+};
+
+static const char * const sysen_groups[] = {
+       "gpio4",
+       "gpio6",
+};
+
+static const char * const clk32kgaudio_groups[] = {
+       "gpio5",
+};
+
+static const char * const id_groups[] = {
+       "gpio0",
+};
+
+static const char * const vbus_det_groups[] = {
+       "gpio1",
+};
+
+static const char * const chrg_det_groups[] = {
+       "gpio3",
+};
+
+static const char * const vac_groups[] = {
+       "vac",
+};
+
+static const char * const vacok_groups[] = {
+       "vac",
+};
+
+static const char * const powergood_groups[] = {
+       "powergood",
+};
+
+static const char * const usb_psel_groups[] = {
+       "gpio5",
+       "powergood",
+};
+
+static const char * const msecure_groups[] = {
+       "gpio7",
+};
+
+static const char * const pwrhold_groups[] = {
+       "gpio7",
+};
+
+static const char * const int_groups[] = {
+       "int",
+};
+
+static const char * const nreswarm_groups[] = {
+       "nreswarm",
+};
+
+static const char * const simrsto_groups[] = {
+       "gpio12",
+};
+
+static const char * const simrsti_groups[] = {
+       "gpio8",
+       "gpio15",
+};
+
+static const char * const low_vbat_groups[] = {
+       "gpio9",
+};
+
+static const char * const wireless_chrg1_groups[] = {
+       "gpio10",
+};
+
+static const char * const rcm_groups[] = {
+       "gpio11",
+};
+
+static const char * const pwrdown_groups[] = {
+       "pwrdown",
+};
+
+static const char * const gpadc_start_groups[] = {
+       "gpadc_start",
+};
+
+static const char * const reset_in_groups[] = {
+       "reset_in",
+};
+
+static const char * const nsleep_groups[] = {
+       "nsleep",
+};
+
+static const char * const enable_groups[] = {
+       "enable1",
+       "enable2",
+};
+
+#define FUNCTION_GROUPS                                        \
+       FUNCTION_GROUP(opt0, OPTION0),                  \
+       FUNCTION_GROUP(opt1, OPTION1),                  \
+       FUNCTION_GROUP(opt2, OPTION2),                  \
+       FUNCTION_GROUP(opt3, OPTION3),                  \
+       FUNCTION_GROUP(gpio, GPIO),                     \
+       FUNCTION_GROUP(led, LED),                       \
+       FUNCTION_GROUP(pwm, PWM),                       \
+       FUNCTION_GROUP(regen, REGEN),                   \
+       FUNCTION_GROUP(sysen, SYSEN),                   \
+       FUNCTION_GROUP(clk32kgaudio, CLK32KGAUDIO),     \
+       FUNCTION_GROUP(id, ID),                         \
+       FUNCTION_GROUP(vbus_det, VBUS_DET),             \
+       FUNCTION_GROUP(chrg_det, CHRG_DET),             \
+       FUNCTION_GROUP(vac, VAC),                       \
+       FUNCTION_GROUP(vacok, VACOK),                   \
+       FUNCTION_GROUP(powergood, POWERGOOD),           \
+       FUNCTION_GROUP(usb_psel, USB_PSEL),             \
+       FUNCTION_GROUP(msecure, MSECURE),               \
+       FUNCTION_GROUP(pwrhold, PWRHOLD),               \
+       FUNCTION_GROUP(int, INT),                       \
+       FUNCTION_GROUP(nreswarm, NRESWARM),             \
+       FUNCTION_GROUP(simrsto, SIMRSTO),               \
+       FUNCTION_GROUP(simrsti, SIMRSTI),               \
+       FUNCTION_GROUP(low_vbat, LOW_VBAT),             \
+       FUNCTION_GROUP(wireless_chrg1, WIRELESS_CHRG1), \
+       FUNCTION_GROUP(rcm, RCM),                       \
+       FUNCTION_GROUP(pwrdown, PWRDOWN),               \
+       FUNCTION_GROUP(gpadc_start, GPADC_START),       \
+       FUNCTION_GROUP(reset_in, RESET_IN),             \
+       FUNCTION_GROUP(nsleep, NSLEEP),                 \
+       FUNCTION_GROUP(enable, ENABLE)
+
+static const struct palmas_pin_function palmas_pin_function[] = {
+#undef FUNCTION_GROUP
+#define FUNCTION_GROUP(fname, mux)                     \
+       {                                               \
+               .name = #fname,                         \
+               .groups = fname##_groups,               \
+               .ngroups = ARRAY_SIZE(fname##_groups),  \
+       }
+
+       FUNCTION_GROUPS,
+};
+
+enum palmas_pinmux {
+#undef FUNCTION_GROUP
+#define FUNCTION_GROUP(fname, mux)     PALMAS_PINMUX_##mux
+       FUNCTION_GROUPS,
+       PALMAS_PINMUX_NA = 0xFFFF,
 };
 
 struct palmas_pins_pullup_dn_info {
@@ -49,65 +373,60 @@ struct palmas_pins_od_info {
 };
 
 struct palmas_pin_info {
-       int mux_opt;
-       struct palmas_pins_pullup_dn_info *pud_info;
-       struct palmas_pins_od_info *od_info;
+       enum palmas_pinmux mux_opt;
+       const struct palmas_pins_pullup_dn_info *pud_info;
+       const struct palmas_pins_od_info *od_info;
 };
 
-struct palmas_pinctrl_info {
-       const char *pin_name;
-       int pin_id;
-       int pin_rg_base;
-       int pin_reg_add;
-       int pin_reg_mask;
-       int pin_bit_shift;
-       struct palmas_pin_info *opt1;
-       struct palmas_pin_info *opt2;
-       struct palmas_pin_info *opt3;
-       struct palmas_pin_info *opt4;
-};
-
-#define PALMAS_NONE_BASE       -1
-
-#define PULL_UP_DN(_name, _rbase, _add, _mask, _nv, _uv, _dv)  \
-static struct palmas_pins_pullup_dn_info pu_pd_##_name##_info = {      \
-       .pullup_dn_reg_base = PALMAS_##_rbase##_BASE,           \
-       .pullup_dn_reg_add = _add,                              \
-       .pullup_dn_mask = _mask,                                \
-       .normal_val = _nv,                                      \
-       .pull_up_val = _uv,                                     \
-       .pull_dn_val = _dv,                                     \
+struct palmas_pingroup {
+       const char *name;
+       const unsigned pins[1];
+       unsigned npins;
+       unsigned mux_reg_base;
+       unsigned mux_reg_add;
+       unsigned mux_reg_mask;
+       unsigned mux_bit_shift;
+       const struct palmas_pin_info *opt[4];
+};
+
+#define PULL_UP_DN(_name, _rbase, _add, _mask, _nv, _uv, _dv)          \
+static const struct palmas_pins_pullup_dn_info pud_##_name##_info = {  \
+       .pullup_dn_reg_base = PALMAS_##_rbase##_BASE,                   \
+       .pullup_dn_reg_add = _add,                                      \
+       .pullup_dn_mask = _mask,                                        \
+       .normal_val = _nv,                                              \
+       .pull_up_val = _uv,                                             \
+       .pull_dn_val = _dv,                                             \
 }
 
-PULL_UP_DN(NRESWARM, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x2, 0x0, 0x2, -1);
-PULL_UP_DN(PWRDOWN, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x4, 0x0, -1, 0x4);
-PULL_UP_DN(GPADC_START, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x30, 0x0,
-               0x20, 0x10);
-PULL_UP_DN(RESET_IN, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x40, 0x0, -1, 0x40);
-PULL_UP_DN(NSLEEP, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x3, 0x0, 0x2, 0x1);
-PULL_UP_DN(ENABLE1, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0xC, 0x0, 0x8, 0x4);
-PULL_UP_DN(ENABLE2, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x30, 0x0, 0x20, 0x10);
-PULL_UP_DN(VACOK, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x40, 0x0, -1, 0x40);
-PULL_UP_DN(CHRG_DET, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x10, 0x0, -1, 0x10);
-PULL_UP_DN(PWRHOLD, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x4, 0x0, -1, 0x4);
-PULL_UP_DN(MSECURE, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x1, 0x0, -1, 0x1);
-PULL_UP_DN(ID, USB_OTG, PALMAS_USB_ID_CTRL_SET, 0x40, 0x0, 0x40, -1);
-PULL_UP_DN(GPIO0, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x04, 0, -1, 1);
-PULL_UP_DN(GPIO1, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x0C, 0, 0x8, 0x4);
-PULL_UP_DN(GPIO2, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x30, 0x0, 0x20, 0x10);
-PULL_UP_DN(GPIO3, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x40, 0x0, -1, 0x40);
-PULL_UP_DN(GPIO4, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x03, 0x0, 0x2, 0x1);
-PULL_UP_DN(GPIO5, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x0c, 0x0, 0x8, 0x4);
-PULL_UP_DN(GPIO6, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x30, 0x0, 0x20, 0x10);
-PULL_UP_DN(GPIO7, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x40, 0x0, -1, 0x40);
-PULL_UP_DN(GPIO9, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x0C, 0x0, 0x8, 0x4);
-PULL_UP_DN(GPIO10, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x30, 0x0, 0x20, 0x10);
-PULL_UP_DN(GPIO11, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0xC0, 0x0, 0x80, 0x40);
-PULL_UP_DN(GPIO13, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x04, 0x0, -1, 0x04);
-PULL_UP_DN(GPIO14, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x30, 0x0, 0x20, 0x10);
+PULL_UP_DN(nreswarm,   PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL1,       0x2,    0x0,    0x2,    -1);
+PULL_UP_DN(pwrdown,    PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL1,       0x4,    0x0,    -1,     0x4);
+PULL_UP_DN(gpadc_start,        PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL1,       0x30,   0x0,    0x20,   0x10);
+PULL_UP_DN(reset_in,   PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL1,       0x40,   0x0,    -1,     0x40);
+PULL_UP_DN(nsleep,     PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL2,       0x3,    0x0,    0x2,    0x1);
+PULL_UP_DN(enable1,    PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL2,       0xC,    0x0,    0x8,    0x4);
+PULL_UP_DN(enable2,    PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL2,       0x30,   0x0,    0x20,   0x10);
+PULL_UP_DN(vacok,      PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL3,       0x40,   0x0,    -1,     0x40);
+PULL_UP_DN(chrg_det,   PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL3,       0x10,   0x0,    -1,     0x10);
+PULL_UP_DN(pwrhold,    PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL3,       0x4,    0x0,    -1,     0x4);
+PULL_UP_DN(msecure,    PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL3,       0x1,    0x0,    -1,     0x1);
+PULL_UP_DN(id,         USB_OTG,        PALMAS_USB_ID_CTRL_SET,         0x40,   0x0,    0x40,   -1);
+PULL_UP_DN(gpio0,      GPIO,           PALMAS_PU_PD_GPIO_CTRL1,        0x04,   0,      -1,     1);
+PULL_UP_DN(gpio1,      GPIO,           PALMAS_PU_PD_GPIO_CTRL1,        0x0C,   0,      0x8,    0x4);
+PULL_UP_DN(gpio2,      GPIO,           PALMAS_PU_PD_GPIO_CTRL1,        0x30,   0x0,    0x20,   0x10);
+PULL_UP_DN(gpio3,      GPIO,           PALMAS_PU_PD_GPIO_CTRL1,        0x40,   0x0,    -1,     0x40);
+PULL_UP_DN(gpio4,      GPIO,           PALMAS_PU_PD_GPIO_CTRL2,        0x03,   0x0,    0x2,    0x1);
+PULL_UP_DN(gpio5,      GPIO,           PALMAS_PU_PD_GPIO_CTRL2,        0x0c,   0x0,    0x8,    0x4);
+PULL_UP_DN(gpio6,      GPIO,           PALMAS_PU_PD_GPIO_CTRL2,        0x30,   0x0,    0x20,   0x10);
+PULL_UP_DN(gpio7,      GPIO,           PALMAS_PU_PD_GPIO_CTRL2,        0x40,   0x0,    -1,     0x40);
+PULL_UP_DN(gpio9,      GPIO,           PALMAS_PU_PD_GPIO_CTRL3,        0x0C,   0x0,    0x8,    0x4);
+PULL_UP_DN(gpio10,     GPIO,           PALMAS_PU_PD_GPIO_CTRL3,        0x30,   0x0,    0x20,   0x10);
+PULL_UP_DN(gpio11,     GPIO,           PALMAS_PU_PD_GPIO_CTRL3,        0xC0,   0x0,    0x80,   0x40);
+PULL_UP_DN(gpio13,     GPIO,           PALMAS_PU_PD_GPIO_CTRL4,        0x04,   0x0,    -1,     0x04);
+PULL_UP_DN(gpio14,     GPIO,           PALMAS_PU_PD_GPIO_CTRL4,        0x30,   0x0,    0x20,   0x10);
 
 #define OD_INFO(_name, _rbase, _add, _mask, _ev, _dv)          \
-static struct palmas_pins_od_info od_##_name##_info = {                \
+static const struct palmas_pins_od_info od_##_name##_info = {  \
        .od_reg_base = PALMAS_##_rbase##_BASE,                  \
        .od_reg_add = _add,                                     \
        .od_mask = _mask,                                       \
@@ -115,351 +434,690 @@ static struct palmas_pins_od_info od_##_name##_info = {         \
        .od_disable = _dv,                                      \
 }
 
-OD_INFO(GPIO1, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x1, 0x1, 0x0);
-OD_INFO(GPIO2, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x2, 0x2, 0x0);
-OD_INFO(GPIO5, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x20, 0x20, 0x0);
-OD_INFO(GPIO10, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x04, 0x04, 0x0);
-OD_INFO(GPIO13, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x20, 0x20, 0x0);
-OD_INFO(INT, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x8, 0x8, 0x0);
-OD_INFO(PWM1, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x20, 0x20, 0x0);
-OD_INFO(VBUS_DET, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x40, 0x40, 0x0);
-OD_INFO(PWM2, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x80, 0x80, 0x0);
+OD_INFO(gpio1, GPIO,   PALMAS_OD_OUTPUT_GPIO_CTRL,     0x1,    0x1,    0x0);
+OD_INFO(gpio2, GPIO,   PALMAS_OD_OUTPUT_GPIO_CTRL,     0x2,    0x2,    0x0);
+OD_INFO(gpio5, GPIO,   PALMAS_OD_OUTPUT_GPIO_CTRL,     0x20,   0x20,   0x0);
+OD_INFO(gpio10,        GPIO,   PALMAS_OD_OUTPUT_GPIO_CTRL2,    0x04,   0x04,   0x0);
+OD_INFO(gpio13,        GPIO,   PALMAS_OD_OUTPUT_GPIO_CTRL2,    0x20,   0x20,   0x0);
+OD_INFO(int,           PU_PD_OD,       PALMAS_OD_OUTPUT_CTRL,  0x8,    0x8,    0x0);
+OD_INFO(pwm1,          PU_PD_OD,       PALMAS_OD_OUTPUT_CTRL,  0x20,   0x20,   0x0);
+OD_INFO(pwm2,          PU_PD_OD,       PALMAS_OD_OUTPUT_CTRL,  0x80,   0x80,   0x0);
+OD_INFO(vbus_det,      PU_PD_OD,       PALMAS_OD_OUTPUT_CTRL,  0x40,   0x40,   0x0);
 
 #define PIN_INFO(_name, _id, _pud_info, _od_info)              \
-static struct palmas_pin_info pin_##_name##_info = {           \
+static const struct palmas_pin_info pin_##_name##_info = {     \
        .mux_opt = PALMAS_PINMUX_##_id,                         \
        .pud_info = _pud_info,                                  \
        .od_info = _od_info                                     \
 }
 
-PIN_INFO(GPIO0,                GPIO,           &pu_pd_GPIO0_info,      NULL);
-PIN_INFO(GPIO1,                GPIO,           &pu_pd_GPIO1_info,      &od_GPIO1_info);
-PIN_INFO(GPIO2,                GPIO,           &pu_pd_GPIO2_info,      &od_GPIO2_info);
-PIN_INFO(GPIO3,                GPIO,           &pu_pd_GPIO3_info,      NULL);
-PIN_INFO(GPIO4,                GPIO,           &pu_pd_GPIO4_info,      NULL);
-PIN_INFO(GPIO5,                GPIO,           &pu_pd_GPIO5_info,      &od_GPIO5_info);
-PIN_INFO(GPIO6,                GPIO,           &pu_pd_GPIO6_info,      NULL);
-PIN_INFO(GPIO7,                GPIO,           &pu_pd_GPIO7_info,      NULL);
-PIN_INFO(GPIO8,                GPIO,           NULL,                   NULL);
-PIN_INFO(GPIO9,                GPIO,           &pu_pd_GPIO9_info,      NULL);
-PIN_INFO(GPIO10,       GPIO,           &pu_pd_GPIO10_info,
-               &od_GPIO10_info);
-PIN_INFO(GPIO11,       GPIO,           &pu_pd_GPIO11_info,     NULL);
-PIN_INFO(GPIO12,       GPIO,           NULL,                   NULL);
-PIN_INFO(GPIO13,       GPIO,           &pu_pd_GPIO13_info,
-               &od_GPIO13_info);
-PIN_INFO(GPIO14,       GPIO,           &pu_pd_GPIO14_info,     NULL);
-PIN_INFO(GPIO15,       GPIO,           NULL,                   NULL);
-PIN_INFO(ID,           ID,             &pu_pd_ID_info,         NULL);
-PIN_INFO(LED1,         LED,            NULL,                   NULL);
-PIN_INFO(LED2,         LED,            NULL,                   NULL);
-PIN_INFO(REGEN,                REGEN,          NULL,                   NULL);
-PIN_INFO(SYSEN1,       SYSEN,          NULL,                   NULL);
-PIN_INFO(SYSEN2,       SYSEN,          NULL,                   NULL);
-PIN_INFO(INT,          INT,            NULL,                   &od_INT_info);
-PIN_INFO(PWM1,         PWM,            NULL,                   &od_PWM1_info);
-PIN_INFO(PWM2,         PWM,            NULL,                   &od_PWM2_info);
-PIN_INFO(VACOK,                VACOK,          &pu_pd_VACOK_info,      NULL);
-PIN_INFO(CHRG_DET,     CHRG_DET,       &pu_pd_CHRG_DET_info,   NULL);
-PIN_INFO(PWRHOLD,      PWRHOLD,        &pu_pd_PWRHOLD_info,    NULL);
-PIN_INFO(MSECURE,      MSECURE,        &pu_pd_MSECURE_info,    NULL);
-PIN_INFO(NRESWARM,     RESVD,          &pu_pd_NRESWARM_info,   NULL);
-PIN_INFO(PWRDOWN,      RESVD,          &pu_pd_PWRDOWN_info,    NULL);
-PIN_INFO(GPADC_START,  RESVD,          &pu_pd_GPADC_START_info, NULL);
-PIN_INFO(RESET_IN,     RESVD,          &pu_pd_RESET_IN_info,   NULL);
-PIN_INFO(NSLEEP,       RESVD,          &pu_pd_NSLEEP_info,     NULL);
-PIN_INFO(ENABLE1,      RESVD,          &pu_pd_ENABLE1_info,    NULL);
-PIN_INFO(ENABLE2,      RESVD,          &pu_pd_ENABLE2_info,    NULL);
-PIN_INFO(CLK32KGAUDIO, CLK32KGAUDIO,   NULL,                   NULL);
-PIN_INFO(USB_PSEL,     USB_PSEL,       NULL,                   NULL);
-PIN_INFO(VAC,          VAC,            NULL,                   NULL);
-PIN_INFO(POWERGOOD,    POWERGOOD,      NULL,                   NULL);
-PIN_INFO(VBUS_DET,     VBUS_DET,       NULL,           &od_VBUS_DET_info);
-PIN_INFO(SIM1RSTI,     SIM1RSTI,       NULL,                   NULL);
-PIN_INFO(LOW_VBAT,     LOW_VBAT,       NULL,                   NULL);
-PIN_INFO(WIRELESS_CHRG1, WIRELESS_CHRG1,       NULL,           NULL);
-PIN_INFO(RCM,          RCM,            NULL,                   NULL);
-PIN_INFO(SIM2RSTO,     SIM2RSTO,       NULL,                   NULL);
-PIN_INFO(SIM2RSTI,     SIM2RSTI,       NULL,                   NULL);
-
-#define PALMAS_PIN(_pin, _rbase, _add, _mask, _bshift, o1, o2, o3, o4) \
-[PALMAS_PIN_NAME_##_pin] = {                                   \
-               .pin_name = "palmas_pin_"#_pin,                 \
-               .pin_id = PALMAS_PIN_NAME_##_pin,               \
-               .pin_rg_base = PALMAS_##_rbase##_BASE,          \
-               .pin_reg_add = _add,                            \
-               .pin_reg_mask = _mask,                          \
-               .pin_bit_shift = _bshift,                       \
-               .opt1 = o1,                                     \
-               .opt2 = o2,                                     \
-               .opt3 = o3,                                     \
-               .opt4 = o4,                                     \
+PIN_INFO(gpio0,                GPIO,           &pud_gpio0_info,        NULL);
+PIN_INFO(gpio1,                GPIO,           &pud_gpio1_info,        &od_gpio1_info);
+PIN_INFO(gpio2,                GPIO,           &pud_gpio2_info,        &od_gpio2_info);
+PIN_INFO(gpio3,                GPIO,           &pud_gpio3_info,        NULL);
+PIN_INFO(gpio4,                GPIO,           &pud_gpio4_info,        NULL);
+PIN_INFO(gpio5,                GPIO,           &pud_gpio5_info,        &od_gpio5_info);
+PIN_INFO(gpio6,                GPIO,           &pud_gpio6_info,        NULL);
+PIN_INFO(gpio7,                GPIO,           &pud_gpio7_info,        NULL);
+PIN_INFO(gpio8,                GPIO,           NULL,                   NULL);
+PIN_INFO(gpio9,                GPIO,           &pud_gpio9_info,        NULL);
+PIN_INFO(gpio10,       GPIO,           &pud_gpio10_info,       &od_gpio10_info);
+PIN_INFO(gpio11,       GPIO,           &pud_gpio11_info,       NULL);
+PIN_INFO(gpio12,       GPIO,           NULL,                   NULL);
+PIN_INFO(gpio13,       GPIO,           &pud_gpio13_info,       &od_gpio13_info);
+PIN_INFO(gpio14,       GPIO,           &pud_gpio14_info,       NULL);
+PIN_INFO(gpio15,       GPIO,           NULL,                   NULL);
+PIN_INFO(id,           ID,             &pud_id_info,           NULL);
+PIN_INFO(led1,         LED,            NULL,                   NULL);
+PIN_INFO(led2,         LED,            NULL,                   NULL);
+PIN_INFO(regen,                REGEN,          NULL,                   NULL);
+PIN_INFO(sysen1,       SYSEN,          NULL,                   NULL);
+PIN_INFO(sysen2,       SYSEN,          NULL,                   NULL);
+PIN_INFO(int,          INT,            NULL,                   &od_int_info);
+PIN_INFO(pwm1,         PWM,            NULL,                   &od_pwm1_info);
+PIN_INFO(pwm2,         PWM,            NULL,                   &od_pwm2_info);
+PIN_INFO(vacok,                VACOK,          &pud_vacok_info,        NULL);
+PIN_INFO(chrg_det,     CHRG_DET,       &pud_chrg_det_info,     NULL);
+PIN_INFO(pwrhold,      PWRHOLD,        &pud_pwrhold_info,      NULL);
+PIN_INFO(msecure,      MSECURE,        &pud_msecure_info,      NULL);
+PIN_INFO(nreswarm,     NA,             &pud_nreswarm_info,     NULL);
+PIN_INFO(pwrdown,      NA,             &pud_pwrdown_info,      NULL);
+PIN_INFO(gpadc_start,  NA,             &pud_gpadc_start_info,  NULL);
+PIN_INFO(reset_in,     NA,             &pud_reset_in_info,     NULL);
+PIN_INFO(nsleep,       NA,             &pud_nsleep_info,       NULL);
+PIN_INFO(enable1,      NA,             &pud_enable1_info,      NULL);
+PIN_INFO(enable2,      NA,             &pud_enable2_info,      NULL);
+PIN_INFO(clk32kgaudio, CLK32KGAUDIO,   NULL,                   NULL);
+PIN_INFO(usb_psel,     USB_PSEL,       NULL,                   NULL);
+PIN_INFO(vac,          VAC,            NULL,                   NULL);
+PIN_INFO(powergood,    POWERGOOD,      NULL,                   NULL);
+PIN_INFO(vbus_det,     VBUS_DET,       NULL,                   &od_vbus_det_info);
+PIN_INFO(sim1rsti,     SIMRSTI,        NULL,                   NULL);
+PIN_INFO(low_vbat,     LOW_VBAT,       NULL,                   NULL);
+PIN_INFO(rcm,          RCM,            NULL,                   NULL);
+PIN_INFO(sim2rsto,     SIMRSTO,        NULL,                   NULL);
+PIN_INFO(sim2rsti,     SIMRSTI,        NULL,                   NULL);
+PIN_INFO(wireless_chrg1,       WIRELESS_CHRG1, NULL,           NULL);
+
+#define PALMAS_PRIMARY_SECONDARY_NONE  0
+#define PALMAS_NONE_BASE               0
+#define PALMAS_PRIMARY_SECONDARY_INPUT3 PALMAS_PU_PD_INPUT_CTRL3
+
+#define PALMAS_PINGROUP(pg_name, pin_id, base, reg, _mask, _bshift, o0, o1, o2, o3)  \
+       {                                                               \
+               .name = #pg_name,                                       \
+               .pins = {PALMAS_PIN_##pin_id},                          \
+               .npins = 1,                                             \
+               .mux_reg_base = PALMAS_##base##_BASE,                   \
+               .mux_reg_add = PALMAS_PRIMARY_SECONDARY_##reg,          \
+               .mux_reg_mask = _mask,                                  \
+               .mux_bit_shift = _bshift,                               \
+               .opt = {                                                \
+                       o0,                                             \
+                       o1,                                             \
+                       o2,                                             \
+                       o3,                                             \
+               },                                                      \
+       }
+
+static const struct palmas_pingroup tps65913_pingroups[] = {
+       PALMAS_PINGROUP(gpio0,  GPIO0_ID,                       PU_PD_OD,       PAD1,   0x4,    0x2,    &pin_gpio0_info,        &pin_id_info,           NULL,           NULL),
+       PALMAS_PINGROUP(gpio1,  GPIO1_VBUS_LED1_PWM1,           PU_PD_OD,       PAD1,   0x18,   0x3,    &pin_gpio1_info,        &pin_vbus_det_info,     &pin_led1_info, &pin_pwm1_info),
+       PALMAS_PINGROUP(gpio2,  GPIO2_REGEN_LED2_PWM2,          PU_PD_OD,       PAD1,   0x60,   0x5,    &pin_gpio2_info,        &pin_regen_info,        &pin_led2_info, &pin_pwm2_info),
+       PALMAS_PINGROUP(gpio3,  GPIO3_CHRG_DET,                 PU_PD_OD,       PAD1,   0x80,   0x7,    &pin_gpio3_info,        &pin_chrg_det_info,     NULL,           NULL),
+       PALMAS_PINGROUP(gpio4,  GPIO4_SYSEN1,                   PU_PD_OD,       PAD1,   0x01,   0x0,    &pin_gpio4_info,        &pin_sysen1_info,       NULL,           NULL),
+       PALMAS_PINGROUP(gpio5,  GPIO5_CLK32KGAUDIO_USB_PSEL,    PU_PD_OD,       PAD2,   0x6,    0x1,    &pin_gpio5_info,        &pin_clk32kgaudio_info, &pin_usb_psel_info,     NULL),
+       PALMAS_PINGROUP(gpio6,  GPIO6_SYSEN2,                   PU_PD_OD,       PAD2,   0x08,   0x3,    &pin_gpio6_info,        &pin_sysen2_info,       NULL,           NULL),
+       PALMAS_PINGROUP(gpio7,  GPIO7_MSECURE_PWRHOLD,          PU_PD_OD,       PAD2,   0x30,   0x4,    &pin_gpio7_info,        &pin_msecure_info,      &pin_pwrhold_info,      NULL),
+       PALMAS_PINGROUP(vac,    VAC,                            PU_PD_OD,       PAD1,   0x02,   0x1,    &pin_vac_info,          &pin_vacok_info,        NULL,           NULL),
+       PALMAS_PINGROUP(powergood,      POWERGOOD_USB_PSEL,     PU_PD_OD,       PAD1,   0x01,   0x0,    &pin_powergood_info,    &pin_usb_psel_info,     NULL,   NULL),
+       PALMAS_PINGROUP(nreswarm,       NRESWARM,               NONE,           NONE,   0x0,    0x0,    &pin_nreswarm_info,     NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(pwrdown,        PWRDOWN,                NONE,           NONE,   0x0,    0x0,    &pin_pwrdown_info,      NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(gpadc_start,    GPADC_START,            NONE,           NONE,   0x0,    0x0,    &pin_gpadc_start_info,  NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(reset_in,       RESET_IN,               NONE,           NONE,   0x0,    0x0,    &pin_reset_in_info,     NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(nsleep,         NSLEEP,                 NONE,           NONE,   0x0,    0x0,    &pin_nsleep_info,       NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(enable1,        ENABLE1,                NONE,           NONE,   0x0,    0x0,    &pin_enable1_info,      NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(enable2,        ENABLE2,                NONE,           NONE,   0x0,    0x0,    &pin_enable2_info,      NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(int,            INT,                    NONE,           NONE,   0x0,    0x0,    &pin_int_info,          NULL,                   NULL,           NULL),
+};
+
+static const struct palmas_pingroup tps80036_pingroups[] = {
+       PALMAS_PINGROUP(gpio0,  GPIO0_ID,                       PU_PD_OD,       PAD1,   0x4,    0x2,    &pin_gpio0_info,        &pin_id_info,           NULL,           NULL),
+       PALMAS_PINGROUP(gpio1,  GPIO1_VBUS_LED1_PWM1,           PU_PD_OD,       PAD1,   0x18,   0x3,    &pin_gpio1_info,        &pin_vbus_det_info,     &pin_led1_info, &pin_pwm1_info),
+       PALMAS_PINGROUP(gpio2,  GPIO2_REGEN_LED2_PWM2,          PU_PD_OD,       PAD1,   0x60,   0x5,    &pin_gpio2_info,        &pin_regen_info,        &pin_led2_info, &pin_pwm2_info),
+       PALMAS_PINGROUP(gpio3,  GPIO3_CHRG_DET,                 PU_PD_OD,       PAD1,   0x80,   0x7,    &pin_gpio3_info,        &pin_chrg_det_info,     NULL,           NULL),
+       PALMAS_PINGROUP(gpio4,  GPIO4_SYSEN1,                   PU_PD_OD,       PAD1,   0x01,   0x0,    &pin_gpio4_info,        &pin_sysen1_info,       NULL,           NULL),
+       PALMAS_PINGROUP(gpio5,  GPIO5_CLK32KGAUDIO_USB_PSEL,    PU_PD_OD,       PAD2,   0x6,    0x1,    &pin_gpio5_info,        &pin_clk32kgaudio_info, &pin_usb_psel_info,     NULL),
+       PALMAS_PINGROUP(gpio6,  GPIO6_SYSEN2,                   PU_PD_OD,       PAD2,   0x08,   0x3,    &pin_gpio6_info,        &pin_sysen2_info,       NULL,           NULL),
+       PALMAS_PINGROUP(gpio7,  GPIO7_MSECURE_PWRHOLD,          PU_PD_OD,       PAD2,   0x30,   0x4,    &pin_gpio7_info,        &pin_msecure_info,      &pin_pwrhold_info,      NULL),
+       PALMAS_PINGROUP(gpio8,  GPIO8_SIM1RSTI,                 PU_PD_OD,       PAD4,   0x01,   0x0,    &pin_gpio8_info,        &pin_sim1rsti_info,     NULL,           NULL),
+       PALMAS_PINGROUP(gpio9,  GPIO9_LOW_VBAT,                 PU_PD_OD,       PAD4,   0x02,   0x1,    &pin_gpio9_info,        &pin_low_vbat_info,     NULL,           NULL),
+       PALMAS_PINGROUP(gpio10, GPIO10_WIRELESS_CHRG1,          PU_PD_OD,       PAD4,   0x04,   0x2,    &pin_gpio10_info,       &pin_wireless_chrg1_info,       NULL,   NULL),
+       PALMAS_PINGROUP(gpio11, GPIO11_RCM,                     PU_PD_OD,       PAD4,   0x08,   0x3,    &pin_gpio11_info,       &pin_rcm_info,          NULL,           NULL),
+       PALMAS_PINGROUP(gpio12, GPIO12_SIM2RSTO,                PU_PD_OD,       PAD4,   0x10,   0x4,    &pin_gpio12_info,       &pin_sim2rsto_info,     NULL,           NULL),
+       PALMAS_PINGROUP(gpio13, GPIO13,                         NONE,           NONE,   0x00,   0x0,    &pin_gpio13_info,       NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(gpio14, GPIO14,                         NONE,           NONE,   0x00,   0x0,    &pin_gpio14_info,       NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(gpio15, GPIO15_SIM2RSTI,                PU_PD_OD,       PAD4,   0x80,   0x7,    &pin_gpio15_info,       &pin_sim2rsti_info,     NULL,           NULL),
+       PALMAS_PINGROUP(vac,    VAC,                            PU_PD_OD,       PAD1,   0x02,   0x1,    &pin_vac_info,          &pin_vacok_info,        NULL,           NULL),
+       PALMAS_PINGROUP(powergood,      POWERGOOD_USB_PSEL,     PU_PD_OD,       PAD1,   0x01,   0x0,    &pin_powergood_info,    &pin_usb_psel_info,     NULL,   NULL),
+       PALMAS_PINGROUP(nreswarm,       NRESWARM,               NONE,           NONE,   0x0,    0x0,    &pin_nreswarm_info,     NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(pwrdown,        PWRDOWN,                NONE,           NONE,   0x0,    0x0,    &pin_pwrdown_info,      NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(gpadc_start,    GPADC_START,            NONE,           NONE,   0x0,    0x0,    &pin_gpadc_start_info,  NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(reset_in,       RESET_IN,               NONE,           NONE,   0x0,    0x0,    &pin_reset_in_info,     NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(nsleep,         NSLEEP,                 NONE,           NONE,   0x0,    0x0,    &pin_nsleep_info,       NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(enable1,        ENABLE1,                NONE,           NONE,   0x0,    0x0,    &pin_enable1_info,      NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(enable2,        ENABLE2,                NONE,           NONE,   0x0,    0x0,    &pin_enable2_info,      NULL,                   NULL,           NULL),
+       PALMAS_PINGROUP(int,            INT,                    NONE,           NONE,   0x0,    0x0,    &pin_int_info,          NULL,                   NULL,           NULL),
+};
+
+static int palmas_pinctrl_get_pin_mux(struct palmas_pctrl_chip_info *pci)
+{
+       const struct palmas_pingroup *g;
+       unsigned int val;
+       int ret;
+       int i;
+
+       for (i = 0; i < pci->num_pin_groups; ++i) {
+               g = &pci->pin_groups[i];
+               if (g->mux_reg_base == PALMAS_NONE_BASE) {
+                       pci->pins_current_opt[i] = 0;
+                       continue;
+               }
+               ret = palmas_read(pci->palmas, g->mux_reg_base,
+                               g->mux_reg_add, &val);
+               if (ret < 0) {
+                       dev_err(pci->dev, "mux_reg 0x%02x read failed: %d\n",
+                                       g->mux_reg_add, ret);
+                       return ret;
+               }
+               val &= g->mux_reg_mask;
+               pci->pins_current_opt[i] = val >> g->mux_bit_shift;
+       }
+       return 0;
 }
 
-static struct palmas_pinctrl_info palmas_pinctrl_info[PALMAS_PIN_NAME_MAX] = {
-       PALMAS_PIN(GPIO0, PU_PD_OD, PALMAS_PRIMARY_SECONDARY_PAD1, 0x04, 0x2,
-               &pin_GPIO0_info, &pin_ID_info, NULL, NULL),
-       PALMAS_PIN(GPIO1, PU_PD_OD, PALMAS_PRIMARY_SECONDARY_PAD1, 0x18, 0x3,
-               &pin_GPIO1_info, &pin_VBUS_DET_info, &pin_LED1_info,
-               &pin_PWM1_info),
-       PALMAS_PIN(GPIO2, PU_PD_OD, PALMAS_PRIMARY_SECONDARY_PAD1, 0x60, 0x5,
-               &pin_GPIO2_info, &pin_REGEN_info, &pin_LED2_info,
-               &pin_PWM2_info),
-       PALMAS_PIN(GPIO3, PU_PD_OD, PALMAS_PRIMARY_SECONDARY_PAD1, 0x80, 0x7,
-               &pin_GPIO3_info, &pin_CHRG_DET_info, NULL, NULL),
-       PALMAS_PIN(GPIO4, PU_PD_OD, PALMAS_PRIMARY_SECONDARY_PAD2, 0x01, 0x0,
-               &pin_GPIO4_info, &pin_SYSEN1_info, NULL, NULL),
-       PALMAS_PIN(GPIO5, PU_PD_OD, PALMAS_PRIMARY_SECONDARY_PAD2, 0x06, 0x1,
-               &pin_GPIO5_info, &pin_CLK32KGAUDIO_info, &pin_USB_PSEL_info,
-               NULL),
-       PALMAS_PIN(GPIO6, PU_PD_OD, PALMAS_PRIMARY_SECONDARY_PAD2, 0x8, 3,
-                &pin_GPIO6_info, &pin_SYSEN2_info, NULL, NULL),
-       PALMAS_PIN(GPIO7, PU_PD_OD, PALMAS_PRIMARY_SECONDARY_PAD2, 0x30, 4,
-               &pin_GPIO7_info, &pin_MSECURE_info, &pin_PWRHOLD_info, NULL),
-       PALMAS_PIN(GPIO8, PU_PD_OD, PALMAS_PRIMARY_SECONDARY_PAD4, 0x01, 0,
-               &pin_GPIO8_info, &pin_SIM1RSTI_info, NULL, NULL),
-       PALMAS_PIN(GPIO9, PU_PD_OD, PALMAS_PRIMARY_SECONDARY_PAD4, 0x02, 1,
-               &pin_GPIO9_info, &pin_LOW_VBAT_info, NULL, NULL),
-       PALMAS_PIN(GPIO10, PU_PD_OD, PALMAS_PRIMARY_SECONDARY_PAD4, 0x04, 2,
-               &pin_GPIO10_info, &pin_WIRELESS_CHRG1_info, NULL, NULL),
-       PALMAS_PIN(GPIO11, PU_PD_OD, PALMAS_PRIMARY_SECONDARY_PAD4, 0x08, 3,
-               &pin_GPIO11_info, &pin_RCM_info, NULL, NULL),
-       PALMAS_PIN(GPIO12, PU_PD_OD, PALMAS_PRIMARY_SECONDARY_PAD4, 0x10, 4,
-               &pin_GPIO12_info, &pin_SIM2RSTO_info, NULL, NULL),
-       PALMAS_PIN(GPIO13, NONE, 0, 0, 0,
-               &pin_GPIO13_info, NULL, NULL, NULL),
-       PALMAS_PIN(GPIO14, NONE, 0, 0, 0,
-               &pin_GPIO14_info, NULL, NULL, NULL),
-       PALMAS_PIN(GPIO15, PU_PD_OD, PALMAS_PRIMARY_SECONDARY_PAD4, 0x80, 7,
-               &pin_GPIO15_info, &pin_SIM2RSTI_info, NULL, NULL),
-       PALMAS_PIN(VAC, PU_PD_OD, 0x6, 0x2, 1,
-               &pin_VAC_info, &pin_VACOK_info, NULL, NULL),
-       PALMAS_PIN(POWERGOOD, PU_PD_OD, 0x6, 0x1, 0,
-               &pin_POWERGOOD_info, &pin_USB_PSEL_info, NULL, NULL),
-       PALMAS_PIN(NRESWARM, NONE, 0, 0, 0,
-               &pin_NRESWARM_info, NULL, NULL, NULL),
-       PALMAS_PIN(PWRDOWN, NONE, 0, 0, 0,
-               &pin_PWRDOWN_info, NULL, NULL, NULL),
-       PALMAS_PIN(GPADC_START, NONE, 0, 0, 0,
-               &pin_GPADC_START_info, NULL, NULL, NULL),
-       PALMAS_PIN(RESET_IN, NONE, 0, 0, 0,
-               &pin_RESET_IN_info, NULL, NULL, NULL),
-       PALMAS_PIN(NSLEEP, NONE, 0, 0, 0,
-               &pin_NSLEEP_info, NULL, NULL, NULL),
-       PALMAS_PIN(ENABLE1, NONE, 0, 0, 0,
-               &pin_ENABLE1_info, NULL, NULL, NULL),
-       PALMAS_PIN(ENABLE2, NONE, 0, 0, 0,
-               &pin_ENABLE2_info, NULL, NULL, NULL),
-       PALMAS_PIN(INT, NONE, 0, 0, 0,
-               &pin_INT_info, NULL, NULL, NULL),
-};
-
-static int palmas_set_single_pin_config(struct palmas_pinctrl *pinctrl,
-       struct palmas_pinctrl_config *muxcfg)
+static int palmas_pinctrl_set_dvfs1(struct palmas_pctrl_chip_info *pci,
+               bool enable)
 {
-       int pin_id = muxcfg->pin_name;
-       int pin_option = muxcfg->pin_mux_option;
-       int pull_up_dn = muxcfg->pin_pull_up_dn;
-       int od_config = muxcfg->open_drain_state;
-       struct palmas_pin_info *opt;
-       struct palmas_pinctrl_info *pin_cfg;
-       struct palmas_pins_pullup_dn_info *pud_info;
-       struct palmas_pins_od_info *od_info;
-       int opt_nr;
-       int ret = 0;
+       int ret;
        int val;
 
-       if ((pin_id < 0) || (pin_id >= PALMAS_PIN_NAME_MAX)) {
-               dev_err(pinctrl->dev, "Pin id %d is out of range\n", pin_id);
-               return -EINVAL;
-       }
+       val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 : 0;
+       ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
+                       PALMAS_PRIMARY_SECONDARY_PAD3,
+                       PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1, val);
+       if (ret < 0)
+               dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
+       return ret;
+}
 
-       pin_cfg = &palmas_pinctrl_info[pin_id];
-       if (pin_id != pin_cfg->pin_id) {
-               dev_err(pinctrl->dev,
-                       "Pin Config table for pin %s is out of sync\n",
-                       pin_cfg->pin_name);
-               return -EINVAL;
-       }
+static int palmas_pinctrl_set_dvfs2(struct palmas_pctrl_chip_info *pci,
+               bool enable)
+{
+       int ret;
+       int val;
 
-       opt = NULL;
-       opt_nr = -1;
-       if (pin_cfg->opt1 && (pin_cfg->opt1->mux_opt == pin_option)) {
-               opt = pin_cfg->opt1;
-               opt_nr = 0;
-       } else if (pin_cfg->opt2 && (pin_cfg->opt2->mux_opt == pin_option)) {
-               opt = pin_cfg->opt2;
-               opt_nr = 1;
-       } else if (pin_cfg->opt3 && (pin_cfg->opt3->mux_opt == pin_option)) {
-               opt = pin_cfg->opt3;
-               opt_nr = 2;
-       } else if (pin_cfg->opt4 && (pin_cfg->opt4->mux_opt == pin_option)) {
-               opt = pin_cfg->opt4;
-               opt_nr = 3;
+       val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 : 0;
+       ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
+                       PALMAS_PRIMARY_SECONDARY_PAD3,
+                       PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2, val);
+       if (ret < 0)
+               dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
+       return ret;
+}
+
+static int palmas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+       struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
+
+       return pci->num_pin_groups;
+}
+
+static const char *palmas_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+               unsigned group)
+{
+       struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
+
+       return pci->pin_groups[group].name;
+}
+
+static int palmas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+               unsigned group, const unsigned **pins, unsigned *num_pins)
+{
+       struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
+
+       *pins = pci->pin_groups[group].pins;
+       *num_pins = pci->pin_groups[group].npins;
+       return 0;
+}
+
+static const struct pinctrl_ops palmas_pinctrl_ops = {
+       .get_groups_count = palmas_pinctrl_get_groups_count,
+       .get_group_name = palmas_pinctrl_get_group_name,
+       .get_group_pins = palmas_pinctrl_get_group_pins,
+       .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+       .dt_free_map = pinctrl_utils_dt_free_map,
+};
+
+static int palmas_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+       struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
+
+       return pci->num_functions;
+}
+
+static const char *palmas_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
+                       unsigned function)
+{
+       struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
+
+       return pci->functions[function].name;
+}
+
+static int palmas_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
+               unsigned function, const char * const **groups,
+               unsigned * const num_groups)
+{
+       struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
+
+       *groups = pci->functions[function].groups;
+       *num_groups = pci->functions[function].ngroups;
+       return 0;
+}
+
+static int palmas_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
+               unsigned group)
+{
+       struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
+       const struct palmas_pingroup *g;
+       int i;
+       int ret;
+
+       g = &pci->pin_groups[group];
+
+       /* If direct option is provided here */
+       if (function <= PALMAS_PINMUX_OPTION3) {
+               if (!g->opt[function]) {
+                       dev_err(pci->dev, "Pin %s does not support option %d\n",
+                               g->name, function);
+                       return -EINVAL;
+               }
+               i = function;
+       } else {
+               for (i = 0; i < ARRAY_SIZE(g->opt); i++) {
+                       if (!g->opt[i])
+                               continue;
+                       if (g->opt[i]->mux_opt == function)
+                               break;
+               }
+               if (WARN_ON(i == ARRAY_SIZE(g->opt))) {
+                       dev_err(pci->dev, "Pin %s does not support option %d\n",
+                               g->name, function);
+                       return -EINVAL;
+               }
        }
 
-       if (!opt) {
-               dev_err(pinctrl->dev, "Pin %s does not have pinmux option %d\n",
-                       pin_cfg->pin_name, pin_option);
-               return -EINVAL;
+       if (g->mux_reg_base == PALMAS_NONE_BASE) {
+               if (WARN_ON(i != 0))
+                       return -EINVAL;
+               return 0;
        }
 
-       if (pin_cfg->pin_rg_base == PALMAS_NONE_BASE)
-               goto skip_pinmux_config;
+       dev_dbg(pci->dev, "%s(): Base0x%02x:0x%02x:0x%02x:0x%02x\n",
+                       __func__, g->mux_reg_base, g->mux_reg_add,
+                       g->mux_reg_mask, i << g->mux_bit_shift);
 
-       ret = palmas_update_bits(pinctrl->palmas, pin_cfg->pin_rg_base,
-                       pin_cfg->pin_reg_add, pin_cfg->pin_reg_mask,
-                       opt_nr << pin_cfg->pin_bit_shift);
+       ret = palmas_update_bits(pci->palmas, g->mux_reg_base, g->mux_reg_add,
+                       g->mux_reg_mask, i << g->mux_bit_shift);
        if (ret < 0) {
-               dev_err(pinctrl->dev, "Reg 0x%03x update failed, %d\n",
-                       pin_cfg->pin_rg_base + pin_cfg->pin_reg_add, ret);
+               dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
+                               g->mux_reg_add, ret);
                return ret;
        }
+       pci->pins_current_opt[group] = i;
+       return 0;
+}
 
-skip_pinmux_config:
-       pud_info = opt->pud_info;
-       if (pull_up_dn == PALMAS_PIN_CONFIG_DEFAULT)
-               goto skip_pud_config;
+static const struct pinmux_ops palmas_pinmux_ops = {
+       .get_functions_count = palmas_pinctrl_get_funcs_count,
+       .get_function_name = palmas_pinctrl_get_func_name,
+       .get_function_groups = palmas_pinctrl_get_func_groups,
+       .enable = palmas_pinctrl_enable,
+};
 
-       if (pud_info->pullup_dn_reg_base == PALMAS_NONE_BASE) {
-               dev_err(pinctrl->dev, "Pin %s up/dn option not available\n",
-                       pin_cfg->pin_name);
-               return -EINVAL;
+static int palmas_pinconf_get(struct pinctrl_dev *pctldev,
+                       unsigned pin, unsigned long *config)
+{
+       struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
+       enum pin_config_param param = pinconf_to_config_param(*config);
+       const struct palmas_pingroup *g;
+       const struct palmas_pin_info *opt;
+       unsigned int val;
+       int ret;
+       int base, add;
+       int rval;
+       int arg;
+       int group_nr;
+
+       for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
+               if (pci->pin_groups[group_nr].pins[0] == pin)
+                       break;
        }
 
-       switch (pull_up_dn) {
-       case PALMAS_PIN_CONFIG_NORMAL:
-               val = pud_info->normal_val;
-               break;
-       case PALMAS_PIN_CONFIG_PULL_UP:
-               val = pud_info->pull_up_val;
+       if (group_nr == pci->num_pin_groups) {
+               dev_err(pci->dev,
+                       "Pinconf is not supported for pin-id %d\n", pin);
+               return -ENOTSUPP;
+       }
+
+       g = &pci->pin_groups[group_nr];
+       opt = g->opt[pci->pins_current_opt[group_nr]];
+       if (!opt) {
+               dev_err(pci->dev,
+                       "Pinconf is not supported for pin %s\n", g->name);
+               return -ENOTSUPP;
+       }
+
+       switch (param) {
+       case PIN_CONFIG_BIAS_DISABLE:
+       case PIN_CONFIG_BIAS_PULL_UP:
+       case PIN_CONFIG_BIAS_PULL_DOWN:
+               if (!opt->pud_info) {
+                       dev_err(pci->dev,
+                               "PULL control not supported for pin %s\n",
+                               g->name);
+                       return -ENOTSUPP;
+               }
+               base = opt->pud_info->pullup_dn_reg_base;
+               add = opt->pud_info->pullup_dn_reg_add;
+               ret = palmas_read(pci->palmas, base, add, &val);
+               if (ret < 0) {
+                       dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
+                               add, ret);
+                       return ret;
+               }
+
+               rval = val & opt->pud_info->pullup_dn_mask;
+               arg = 0;
+               if ((opt->pud_info->normal_val >= 0) &&
+                               (opt->pud_info->normal_val == rval) &&
+                               (param == PIN_CONFIG_BIAS_DISABLE))
+                       arg = 1;
+               else if ((opt->pud_info->pull_up_val >= 0) &&
+                               (opt->pud_info->pull_up_val == rval) &&
+                               (param == PIN_CONFIG_BIAS_PULL_UP))
+                       arg = 1;
+               else if ((opt->pud_info->pull_dn_val >= 0) &&
+                               (opt->pud_info->pull_dn_val == rval) &&
+                               (param == PIN_CONFIG_BIAS_PULL_DOWN))
+                       arg = 1;
                break;
-       case PALMAS_PIN_CONFIG_PULL_DOWN:
-               val = pud_info->pull_dn_val;
+
+       case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+               if (!opt->od_info) {
+                       dev_err(pci->dev,
+                               "OD control not supported for pin %s\n",
+                               g->name);
+                       return -ENOTSUPP;
+               }
+               base = opt->od_info->od_reg_base;
+               add = opt->od_info->od_reg_add;
+               ret = palmas_read(pci->palmas, base, add, &val);
+               if (ret < 0) {
+                       dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
+                               add, ret);
+                       return ret;
+               }
+               rval = val & opt->od_info->od_mask;
+               arg = -1;
+               if ((opt->od_info->od_disable >= 0) &&
+                               (opt->od_info->od_disable == rval))
+                       arg = 0;
+               else if ((opt->od_info->od_enable >= 0) &&
+                                       (opt->od_info->od_enable == rval))
+                       arg = 1;
+               if (arg < 0) {
+                       dev_err(pci->dev,
+                               "OD control not supported for pin %s\n",
+                               g->name);
+                       return -ENOTSUPP;
+               }
                break;
+
        default:
-               dev_err(pinctrl->dev, "Invalid option of pull-up-dn %d\n",
-                       pull_up_dn);
-               return -EINVAL;
+               dev_err(pci->dev, "Properties not supported\n");
+               return -ENOTSUPP;
        }
-       if (val == -1) {
-               dev_err(pinctrl->dev,
-                       "Pull up/dn option %d is not supported\n", pull_up_dn);
-               return -EINVAL;
+
+       *config = pinconf_to_config_packed(param, (u16)arg);
+       return 0;
+}
+
+static int palmas_pinconf_set(struct pinctrl_dev *pctldev,
+                       unsigned pin, unsigned long config)
+{
+       struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
+       enum pin_config_param param = pinconf_to_config_param(config);
+       u16 param_val = pinconf_to_config_argument(config);
+       const struct palmas_pingroup *g;
+       const struct palmas_pin_info *opt;
+       int ret;
+       int base, add, mask;
+       int rval;
+       int group_nr;
+
+       for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
+               if (pci->pin_groups[group_nr].pins[0] == pin)
+                       break;
        }
 
-       ret = palmas_update_bits(pinctrl->palmas, pud_info->pullup_dn_reg_base,
-                       pud_info->pullup_dn_reg_add, pud_info->pullup_dn_mask,
-                       val);
-       if (ret < 0) {
-               dev_err(pinctrl->dev, "reg 0x%03x update failed %d\n",
-                       pud_info->pullup_dn_reg_base +
-                               pud_info->pullup_dn_reg_add, ret);
-               return ret;
+       if (group_nr == pci->num_pin_groups) {
+               dev_err(pci->dev,
+                       "Pinconf is not supported for pin-id %d\n", pin);
+               return -ENOTSUPP;
        }
 
-skip_pud_config:
-       od_info = opt->od_info;
-       if (od_config == PALMAS_PIN_CONFIG_OD_DEFAULT)
-               goto skip_od_config;
+       g = &pci->pin_groups[group_nr];
+       opt = g->opt[pci->pins_current_opt[group_nr]];
+       if (!opt) {
+               dev_err(pci->dev,
+                       "Pinconf is not supported for pin %s\n", g->name);
+               return -ENOTSUPP;
+       }
 
-       switch (od_config) {
-       case PALMAS_PIN_CONFIG_OD_ENABLE:
-               val = opt->od_info->od_enable;
+       switch (param) {
+       case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
+               return 0;
+       case PIN_CONFIG_BIAS_DISABLE:
+       case PIN_CONFIG_BIAS_PULL_UP:
+       case PIN_CONFIG_BIAS_PULL_DOWN:
+               if (!opt->pud_info) {
+                       dev_err(pci->dev,
+                               "PULL control not supported for pin %s\n",
+                               g->name);
+                       return -ENOTSUPP;
+               }
+               base = opt->pud_info->pullup_dn_reg_base;
+               add = opt->pud_info->pullup_dn_reg_add;
+               mask = opt->pud_info->pullup_dn_mask;
+
+               if (param == PIN_CONFIG_BIAS_DISABLE)
+                       rval = opt->pud_info->normal_val;
+               else if (param == PIN_CONFIG_BIAS_PULL_UP)
+                       rval = opt->pud_info->pull_up_val;
+               else
+                       rval = opt->pud_info->pull_dn_val;
+
+               if (rval < 0) {
+                       dev_err(pci->dev,
+                               "PULL control not supported for pin %s\n",
+                               g->name);
+                       return -ENOTSUPP;
+               }
                break;
-       case PALMAS_PIN_CONFIG_OD_DISABLE:
-               val = opt->od_info->od_disable;
+
+       case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+               if (!opt->od_info) {
+                       dev_err(pci->dev,
+                               "OD control not supported for pin %s\n",
+                               g->name);
+                       return -ENOTSUPP;
+               }
+               base = opt->od_info->od_reg_base;
+               add = opt->od_info->od_reg_add;
+               mask = opt->od_info->od_mask;
+               if (param_val == 0)
+                       rval = opt->od_info->od_disable;
+               else
+                       rval = opt->od_info->od_enable;
+               if (rval < 0) {
+                       dev_err(pci->dev,
+                               "OD control not supported for pin %s\n",
+                               g->name);
+                       return -ENOTSUPP;
+               }
                break;
        default:
-               dev_err(pinctrl->dev, "Invalid option of OD %d\n", od_config);
-               return -EINVAL;
+               dev_err(pci->dev, "Properties not supported\n");
+               return -ENOTSUPP;
        }
 
-       if (opt->od_info->od_reg_base == PALMAS_NONE_BASE) {
-               dev_err(pinctrl->dev, "Pin %s OD option not available\n",
-                       pin_cfg->pin_name);
-               return -EINVAL;
-       }
-
-       ret = palmas_update_bits(pinctrl->palmas, od_info->od_reg_base,
-               od_info->od_reg_add, od_info->od_mask, val);
+       dev_dbg(pci->dev, "%s(): Add0x%02x:0x%02x:0x%02x:0x%02x\n",
+                       __func__, base, add, mask, rval);
+       ret = palmas_update_bits(pci->palmas, base, add, mask, rval);
        if (ret < 0) {
-               dev_err(pinctrl->dev, "Reg 0x%03x update failed. %d\n",
-                       od_info->od_reg_base + od_info->od_reg_add, ret);
+               dev_err(pci->dev, "Reg 0x%02x update failed: %d\n", add, ret);
                return ret;
        }
-
-skip_od_config:
-       return ret;
+       return 0;
 }
 
-static int palmas_set_dvfs1(struct palmas_pinctrl *pinctrl, bool enable)
+static int palmas_pinconf_group_get(struct pinctrl_dev *pctldev,
+                               unsigned group, unsigned long *config)
 {
-       int ret;
-       int val;
-
-       val = (enable) ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 : 0;
-       ret = palmas_update_bits(pinctrl->palmas, PALMAS_PU_PD_OD_BASE,
-                       PALMAS_PRIMARY_SECONDARY_PAD3,
-                       PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1, val);
-       if (ret < 0)
-               dev_err(pinctrl->dev, "SECONDARY_PAD3 update failed %d\n", ret);
-       return ret;
+       dev_err(pctldev->dev, "palmas_pinconf_group_get op not supported\n");
+       return -ENOTSUPP;
 }
 
-static int palmas_set_dvfs2(struct palmas_pinctrl *pinctrl, bool enable)
+static int palmas_pinconf_group_set(struct pinctrl_dev *pctldev,
+                               unsigned group, unsigned long config)
 {
-       int ret;
-       int val;
-
-       val = (enable) ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 : 0;
-       ret = palmas_update_bits(pinctrl->palmas, PALMAS_PU_PD_OD_BASE,
-                       PALMAS_PRIMARY_SECONDARY_PAD3,
-                       PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2, val);
-       if (ret < 0)
-               dev_err(pinctrl->dev, "SECONDARY_PAD3 update failed %d\n", ret);
-       return ret;
+       dev_err(pctldev->dev, "palmas_pinconf_group_set op not supported\n");
+       return -ENOTSUPP;
 }
 
-static int palmas_pinctrl_probe(struct platform_device *pdev)
+static const struct pinconf_ops palmas_pinconf_ops = {
+       .pin_config_get = palmas_pinconf_get,
+       .pin_config_set = palmas_pinconf_set,
+       .pin_config_group_get = palmas_pinconf_group_get,
+       .pin_config_group_set = palmas_pinconf_group_set,
+};
+
+static struct pinctrl_desc palmas_pinctrl_desc = {
+       .pctlops = (struct pinctrl_ops *)&palmas_pinctrl_ops,
+       .pmxops = (struct pinmux_ops *)&palmas_pinmux_ops,
+       .confops = (struct pinconf_ops *)&palmas_pinconf_ops,
+       .owner = THIS_MODULE,
+};
+
+struct palmas_pinctrl_data {
+       const struct palmas_pingroup *pin_groups;
+       int num_pin_groups;
+};
+
+static struct palmas_pinctrl_data tps65913_pinctrl_data = {
+       .pin_groups = tps65913_pingroups,
+       .num_pin_groups = ARRAY_SIZE(tps65913_pingroups),
+};
+
+static struct palmas_pinctrl_data tps80036_pinctrl_data = {
+       .pin_groups = tps80036_pingroups,
+       .num_pin_groups = ARRAY_SIZE(tps80036_pingroups),
+};
+
+static struct of_device_id palmas_pinctrl_of_match[] = {
+       { .compatible = "ti,palmas-pinctrl", .data = &tps65913_pinctrl_data},
+       { .compatible = "ti,tps65913-pinctrl", .data = &tps65913_pinctrl_data},
+       { .compatible = "ti,tps80036-pinctrl", .data = &tps80036_pinctrl_data},
+       { },
+};
+MODULE_DEVICE_TABLE(of, palmas_pinctrl_of_match);
+
+static int palmas_pinctrl_set_single_pin_config(
+       struct palmas_pctrl_chip_info *pci,
+       struct palmas_pinctrl_config *muxcfg)
 {
-       struct palmas_platform_data *pdata;
-       struct palmas_pinctrl_platform_data *pctrl_pdata;
-       struct palmas_pinctrl *pinctrl;
-       struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
+       int pin_id;
+       int group_nr;
+       int param_val;
+       int param;
+       int ret = 0;
+       int mux_opt;
        int i;
-       int ret;
-       unsigned int reg;
+       unsigned long config;
 
-       pdata = dev_get_platdata(pdev->dev.parent);
-       if (!pdata || !pdata->pinctrl_pdata) {
-               dev_err(&pdev->dev, "No Platform data\n");
+       if (!muxcfg->pin) {
+               dev_err(pci->dev, "No pin name\n");
                return -EINVAL;
        }
 
-       pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
-       if (!pinctrl) {
-               dev_err(&pdev->dev, "Memory allocation for pinctrl failed\n");
-               return -ENOMEM;
+       pin_id = pin_get_from_name(pci->pctl, muxcfg->pin);
+       if (pin_id < 0) {
+               dev_err(pci->dev, " Pin %s not found\n", muxcfg->pin);
+               return ret;
        }
 
-       pinctrl->dev = &pdev->dev;
-       pinctrl->palmas = palmas;
-       pctrl_pdata = pdata->pinctrl_pdata;
-       for (i = 0; i < pctrl_pdata->num_pinctrl; ++i) {
-               struct palmas_pinctrl_config *pcfg =  &pctrl_pdata->pincfg[i];
+       /* Configure function */
+       if (!muxcfg->function)
+               goto skip_function;
 
-               palmas_set_single_pin_config(pinctrl, pcfg);
+       for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
+               if (pci->pin_groups[group_nr].pins[0] == pin_id)
+                       break;
        }
 
-       palmas_set_dvfs1(pinctrl, pctrl_pdata->dvfs1_enable);
-       palmas_set_dvfs2(pinctrl, pctrl_pdata->dvfs2_enable);
+       if (group_nr == pci->num_pin_groups) {
+               dev_err(pci->dev,
+                       "Pinconf is not supported for pin-id %d\n", pin_id);
+               return -ENOTSUPP;
+       }
+
+       mux_opt = -1;
+       for (i = 0; i < pci->num_functions; ++i) {
+               if (!strcmp(muxcfg->function, pci->functions[i].name)) {
+                       mux_opt = i;
+                       break;
+               }
+       }
+       if (mux_opt < 0) {
+               dev_err(pci->dev, "Pinmux function %s not supported\n",
+                       muxcfg->function);
+               return -EINVAL;
+       }
+
+       ret = palmas_pinctrl_enable(pci->pctl, mux_opt, group_nr);
+       if (ret < 0) {
+               dev_err(pci->dev,
+                       "Pinconf config for pin %s failed %d\n",
+                       muxcfg->pin, ret);
+               return ret;
+       }
+
+skip_function:
+
+       /* Configure bias pull */
+       if (!muxcfg->prop_bias_pull)
+               goto skip_bias_pull;
+       if (!strcmp(muxcfg->prop_bias_pull, "pull-up"))
+               param = PIN_CONFIG_BIAS_PULL_UP;
+       else if (!strcmp(muxcfg->prop_bias_pull, "pull-down"))
+               param = PIN_CONFIG_BIAS_PULL_DOWN;
+       else if (!strcmp(muxcfg->prop_bias_pull, "normal"))
+               param = PIN_CONFIG_BIAS_DISABLE;
+       else {
+               dev_err(pci->dev, "Unknown bias-pull setting %s\n",
+                       muxcfg->prop_bias_pull);
+               goto skip_bias_pull;
+       }
+       config = pinconf_to_config_packed(param, 0);
+       ret = palmas_pinconf_set(pci->pctl, pin_id, config);
+       if (ret < 0) {
+               dev_err(pci->dev, "bias-pull setting failed: %d\n", ret);
+               return ret;
+       }
+
+skip_bias_pull:
+       /* Configure open drain */
+       if (!muxcfg->prop_open_drain)
+               goto skip_open_drain;
+       param = PIN_CONFIG_DRIVE_OPEN_DRAIN;
+       if (!strcmp(muxcfg->prop_bias_pull, "enable"))
+               param_val = 1;
+       else
+               param_val = 0;
+       config = pinconf_to_config_packed(param, param_val);
+       ret = palmas_pinconf_set(pci->pctl, pin_id, config);
+       if (ret < 0) {
+               dev_err(pci->dev, "Opendrain setting failed: %d\n", ret);
+               return ret;
+       }
+
+skip_open_drain:
+       return ret;
+}
+
+static int palmas_pinctrl_init_muxed_parameter(
+       struct palmas_pctrl_chip_info *pci)
+{
+       struct palmas *palmas = pci->palmas;
+       unsigned int reg;
+       int ret;
 
        /* PAD1 muxing */
-       ret = palmas_read(pinctrl->palmas, PALMAS_PU_PD_OD_BASE,
+       ret = palmas_read(palmas, PALMAS_PU_PD_OD_BASE,
                                PALMAS_PRIMARY_SECONDARY_PAD1, &reg);
        if (ret < 0) {
-               dev_err(&pdev->dev, "SECONDARY_PAD1 read failed %d\n", ret);
+               dev_err(pci->dev, "SECONDARY_PAD1 read failed %d\n", ret);
                return ret;
        }
        if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0))
@@ -484,10 +1142,10 @@ static int palmas_pinctrl_probe(struct platform_device *pdev)
                palmas->gpio_muxed |= PALMAS_GPIO_3_MUXED;
 
        /* PAD2 muxing */
-       ret = palmas_read(pinctrl->palmas, PALMAS_PU_PD_OD_BASE,
+       ret = palmas_read(palmas, PALMAS_PU_PD_OD_BASE,
                                PALMAS_PRIMARY_SECONDARY_PAD2, &reg);
        if (ret < 0) {
-               dev_err(&pdev->dev, "SECONDARY_PAD2 read failed %d\n", ret);
+               dev_err(pci->dev, "SECONDARY_PAD2 read failed %d\n", ret);
                return ret;
        }
        if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4))
@@ -500,20 +1158,20 @@ static int palmas_pinctrl_probe(struct platform_device *pdev)
                palmas->gpio_muxed |= PALMAS_GPIO_7_MUXED;
 
        /* PAD3 muxing */
-       ret = palmas_read(pinctrl->palmas, PALMAS_PU_PD_OD_BASE,
+       ret = palmas_read(palmas, PALMAS_PU_PD_OD_BASE,
                                PALMAS_PRIMARY_SECONDARY_PAD3, &reg);
        if (ret < 0) {
-               dev_err(&pdev->dev, "SECONDARY_PAD3 read failed %d\n", ret);
+               dev_err(pci->dev, "SECONDARY_PAD3 read failed %d\n", ret);
                return ret;
        }
        if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2))
                palmas->gpio_muxed |= PALMAS_GPIO_6_MUXED;
 
        /* PAD4 muxing */
-       ret = palmas_read(pinctrl->palmas, PALMAS_PU_PD_OD_BASE,
+       ret = palmas_read(palmas, PALMAS_PU_PD_OD_BASE,
                                PALMAS_PRIMARY_SECONDARY_PAD4, &reg);
        if (ret < 0) {
-               dev_err(&pdev->dev, "SECONDARY_PAD4 read failed %d\n", ret);
+               dev_err(pci->dev, "SECONDARY_PAD4 read failed %d\n", ret);
                return ret;
        }
        if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_8_MASK))
@@ -531,18 +1189,129 @@ static int palmas_pinctrl_probe(struct platform_device *pdev)
        if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_15_MASK))
                palmas->gpio_muxed |= PALMAS_GPIO_15_MUXED;
 
-       dev_info(palmas->dev, "Muxing GPIO %x, PWM %x, LED %x\n",
+       dev_info(pci->dev, "Muxing GPIO %x, PWM %x, LED %x\n",
                palmas->gpio_muxed, palmas->pwm_muxed, palmas->led_muxed);
 
        return 0;
 }
 
+static int palmas_pinctrl_probe(struct platform_device *pdev)
+{
+       struct palmas_pctrl_chip_info *pci;
+       const struct palmas_pinctrl_data *pinctrl_data = &tps65913_pinctrl_data;
+       struct palmas_pinctrl_platform_data *pctrl_pdata = NULL;
+       struct palmas_platform_data *pdata;
+       int ret;
+       bool enable_dvfs1 = false;
+       bool enable_dvfs2 = false;
+       struct palmas *palmas;
+       int i;
+
+       pdata = dev_get_platdata(pdev->dev.parent);
+       if (pdata)
+               pctrl_pdata = pdata->pinctrl_pdata;
+       palmas = dev_get_drvdata(pdev->dev.parent);
+
+       if (pdev->dev.of_node) {
+               const struct of_device_id *match;
+               match = of_match_device(palmas_pinctrl_of_match, &pdev->dev);
+               pinctrl_data = match->data;
+               enable_dvfs1 = of_property_read_bool(pdev->dev.of_node,
+                                       "ti,palmas-enable-dvfs1");
+               enable_dvfs2 = of_property_read_bool(pdev->dev.of_node,
+                                       "ti,palmas-enable-dvfs2");
+       } else {
+               if (palmas->id == TPS80036)
+                       pinctrl_data = &tps80036_pinctrl_data;
+               else
+                       pinctrl_data = &tps65913_pinctrl_data;
+       }
+
+       if (pctrl_pdata) {
+               enable_dvfs1 = pctrl_pdata->dvfs1_enable;
+               enable_dvfs2 = pctrl_pdata->dvfs2_enable;
+       }
+
+       pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
+       if (!pci) {
+               dev_err(&pdev->dev, "Malloc for pci failed\n");
+               return -ENOMEM;
+       }
+
+       pci->dev = &pdev->dev;
+       pci->palmas = palmas;
+
+       pci->pins = palmas_pins_desc;
+       pci->num_pins = ARRAY_SIZE(palmas_pins_desc);
+       pci->functions = palmas_pin_function;
+       pci->num_functions = ARRAY_SIZE(palmas_pin_function);
+       pci->pin_groups = pinctrl_data->pin_groups;
+       pci->num_pin_groups = pinctrl_data->num_pin_groups;
+
+       platform_set_drvdata(pdev, pci);
+
+       palmas_pinctrl_set_dvfs1(pci, enable_dvfs1);
+       palmas_pinctrl_set_dvfs2(pci, enable_dvfs2);
+       ret = palmas_pinctrl_get_pin_mux(pci);
+       if (ret < 0) {
+               dev_err(&pdev->dev,
+                       "Reading pinctrol option register failed: %d\n", ret);
+               return ret;
+       }
+
+       palmas_pinctrl_desc.name = dev_name(&pdev->dev);
+       palmas_pinctrl_desc.pins = palmas_pins_desc;
+       palmas_pinctrl_desc.npins = ARRAY_SIZE(palmas_pins_desc);
+       pci->pctl = pinctrl_register(&palmas_pinctrl_desc, &pdev->dev, pci);
+       if (!pci->pctl) {
+               dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
+               return -ENODEV;
+       }
+
+       if (pctrl_pdata) {
+               for (i = 0; i < pctrl_pdata->num_pinctrl; ++i) {
+                       struct palmas_pinctrl_config *pcfg;
+
+                       pcfg =  &pctrl_pdata->pincfg[i];
+                       ret = palmas_pinctrl_set_single_pin_config(pci, pcfg);
+                       if (ret < 0) {
+                               dev_err(&pdev->dev,
+                                  "palmas pinctrl pin-%d config failed %d\n",
+                                   i, ret);
+                               goto scrub;
+                       }
+               }
+       }
+
+       ret = palmas_pinctrl_init_muxed_parameter(pci);
+       if (ret < 0) {
+               dev_err(&pdev->dev,
+                       "palmas pinctrl muxed init failed: %d\n", ret);
+               goto scrub;
+       }
+
+       return 0;
+scrub:
+       pinctrl_unregister(pci->pctl);
+       return ret;
+}
+
+static int palmas_pinctrl_remove(struct platform_device *pdev)
+{
+       struct palmas_pctrl_chip_info *pci = platform_get_drvdata(pdev);
+
+       pinctrl_unregister(pci->pctl);
+       return 0;
+}
+
 static struct platform_driver palmas_pinctrl_driver = {
-       .probe = palmas_pinctrl_probe,
        .driver = {
                .name = "palmas-pinctrl",
                .owner = THIS_MODULE,
+               .of_match_table = palmas_pinctrl_of_match,
        },
+       .probe = palmas_pinctrl_probe,
+       .remove = palmas_pinctrl_remove,
 };
 
 static int __init palmas_pinctrl_init(void)
@@ -557,7 +1326,7 @@ static void __exit palmas_pinctrl_exit(void)
 }
 module_exit(palmas_pinctrl_exit);
 
-MODULE_DESCRIPTION("palmas pin control driver");
+MODULE_DESCRIPTION("Palmas pin control driver");
 MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
 MODULE_ALIAS("platform:palmas-pinctrl");
 MODULE_LICENSE("GPL v2");
index 244b14b..22c3dfd 100644 (file)
@@ -537,6 +537,10 @@ struct palmas_pinctrl_config {
        int pin_mux_option;
        int open_drain_state;
        int pin_pull_up_dn;
+       const char *pin;
+       const char *function;
+       const char *prop_bias_pull;
+       const char *prop_open_drain;
 };
 
 struct palmas_pinctrl_platform_data {
@@ -4121,88 +4125,6 @@ enum {
        PALMAS_SLEEP_REQSTR_ID_MAX,
 };
 
-/* Palmas Pinmux option */
-enum {
-       PALMAS_PINMUX_GPIO = 0,
-       PALMAS_PINMUX_LED,
-       PALMAS_PINMUX_PWM,
-       PALMAS_PINMUX_REGEN,
-       PALMAS_PINMUX_SYSEN,
-       PALMAS_PINMUX_CLK32KGAUDIO,
-       PALMAS_PINMUX_ID,
-       PALMAS_PINMUX_VBUS_DET,
-       PALMAS_PINMUX_CHRG_DET,
-       PALMAS_PINMUX_VAC,
-       PALMAS_PINMUX_VACOK,
-       PALMAS_PINMUX_POWERGOOD,
-       PALMAS_PINMUX_USB_PSEL,
-       PALMAS_PINMUX_MSECURE,
-       PALMAS_PINMUX_PWRHOLD,
-       PALMAS_PINMUX_INT,
-       PALMAS_PINMUX_DVFS2,
-       PALMAS_PINMUX_DVFS1,
-       PALMAS_PINMUX_NRESWARM,
-       PALMAS_PINMUX_SIM1RSTO,
-       PALMAS_PINMUX_SIM1RSTI,
-       PALMAS_PINMUX_LOW_VBAT,
-       PALMAS_PINMUX_WIRELESS_CHRG1,
-       PALMAS_PINMUX_RCM,
-       PALMAS_PINMUX_SIM2RSTO,
-       PALMAS_PINMUX_SIM2RSTI,
-       PALMAS_PINMUX_PWRDOWN,
-       PALMAS_PINMUX_GPADC_START,
-       PALMAS_PINMUX_RESET_IN,
-       PALMAS_PINMUX_NSLEEP,
-       PALMAS_PINMUX_ENABLE1,
-       PALMAS_PINMUX_ENABLE2,
-       PALMAS_PINMUX_RESVD = 0x2000,
-       PALMAS_PINMUX_DEFAULT = 0x4000,
-       PALMAS_PINMUX_INVALID = 0x8000,
-};
-
-/* Palmas Pinmux Pullup/pulldown/opendrain configuration. */
-enum {
-       PALMAS_PIN_CONFIG_DEFAULT,
-       PALMAS_PIN_CONFIG_NORMAL,
-       PALMAS_PIN_CONFIG_PULL_UP,
-       PALMAS_PIN_CONFIG_PULL_DOWN,
-
-       PALMAS_PIN_CONFIG_OD_DEFAULT,
-       PALMAS_PIN_CONFIG_OD_ENABLE,
-       PALMAS_PIN_CONFIG_OD_DISABLE,
-};
-
-/* Palmas Pins name */
-enum {
-       PALMAS_PIN_NAME_GPIO0,
-       PALMAS_PIN_NAME_GPIO1,
-       PALMAS_PIN_NAME_GPIO2,
-       PALMAS_PIN_NAME_GPIO3,
-       PALMAS_PIN_NAME_GPIO4,
-       PALMAS_PIN_NAME_GPIO5,
-       PALMAS_PIN_NAME_GPIO6,
-       PALMAS_PIN_NAME_GPIO7,
-       PALMAS_PIN_NAME_GPIO8,
-       PALMAS_PIN_NAME_GPIO9,
-       PALMAS_PIN_NAME_GPIO10,
-       PALMAS_PIN_NAME_GPIO11,
-       PALMAS_PIN_NAME_GPIO12,
-       PALMAS_PIN_NAME_GPIO13,
-       PALMAS_PIN_NAME_GPIO14,
-       PALMAS_PIN_NAME_GPIO15,
-       PALMAS_PIN_NAME_VAC,
-       PALMAS_PIN_NAME_POWERGOOD,
-       PALMAS_PIN_NAME_NRESWARM,
-       PALMAS_PIN_NAME_PWRDOWN,
-       PALMAS_PIN_NAME_GPADC_START,
-       PALMAS_PIN_NAME_RESET_IN,
-       PALMAS_PIN_NAME_NSLEEP,
-       PALMAS_PIN_NAME_ENABLE1,
-       PALMAS_PIN_NAME_ENABLE2,
-       PALMAS_PIN_NAME_INT,
-       PALMAS_PIN_NAME_MAX,
-};
-
 extern int palmas_ext_power_req_config(struct palmas *palmas,
                int id,  int ext_pwr_ctrl, bool enable);