ARM: tegra: pinmux: Add Tegra12x pinmux tables
Mark Stadler [Tue, 31 Jul 2012 23:18:13 +0000 (16:18 -0700)]
Change-Id: I021b1bed4e84a8d47463b8ee289ff400d9767767
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/82930
Signed-off-by: Mark Stadler <mastadler@nvidia.com>

arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/devices.c
arch/arm/mach-tegra/include/mach/pinmux-t12.h [new file with mode: 0644]
arch/arm/mach-tegra/include/mach/pinmux.h
arch/arm/mach-tegra/pinmux-t12-tables.c [new file with mode: 0644]
arch/arm/mach-tegra/pinmux.c

index d2941ba..4d58f43 100644 (file)
@@ -119,6 +119,7 @@ obj-y                                       += tegra_emc.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pinmux-tegra20-tables.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += pinmux-tegra30-tables.o
 obj-$(CONFIG_ARCH_TEGRA_11x_SOC)        += pinmux-t11-tables.o
+obj-$(CONFIG_ARCH_TEGRA_12x_SOC)        += pinmux-t12-tables.o
 obj-$(CONFIG_ARCH_TEGRA_14x_SOC)        += pinmux-t14-tables.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)                += tegra20_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)                += tegra30_speedo.o
index 9cf76e5..b4e13ac 100644 (file)
@@ -175,6 +175,8 @@ struct platform_device tegra_pinmux_device = {
        .name           = "tegra20-pinmux-ctl",
 #elif defined(CONFIG_ARCH_TEGRA_11x_SOC)
        .name           = "tegra11x-pinmux-ctl",
+#elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
+       .name           = "tegra12x-pinmux",
 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
        .name           = "tegra14x-pinmux",
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t12.h b/arch/arm/mach-tegra/include/mach/pinmux-t12.h
new file mode 100644 (file)
index 0000000..ed35837
--- /dev/null
@@ -0,0 +1,243 @@
+/*
+ * linux/arch/arm/mach-tegra/include/mach/pinmux-t12.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011-2012 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_PINMUX_T12_H
+#define __MACH_TEGRA_PINMUX_T12_H
+
+void tegra12x_default_pinmux(void);
+
+enum tegra_pingroup {
+       TEGRA_PINGROUP_ULPI_DATA0,
+       TEGRA_PINGROUP_ULPI_DATA1,
+       TEGRA_PINGROUP_ULPI_DATA2,
+       TEGRA_PINGROUP_ULPI_DATA3,
+       TEGRA_PINGROUP_ULPI_DATA4,
+       TEGRA_PINGROUP_ULPI_DATA5,
+       TEGRA_PINGROUP_ULPI_DATA6,
+       TEGRA_PINGROUP_ULPI_DATA7,
+       TEGRA_PINGROUP_ULPI_CLK,
+       TEGRA_PINGROUP_ULPI_DIR,
+       TEGRA_PINGROUP_ULPI_NXT,
+       TEGRA_PINGROUP_ULPI_STP,
+       TEGRA_PINGROUP_DAP3_FS,
+       TEGRA_PINGROUP_DAP3_DIN,
+       TEGRA_PINGROUP_DAP3_DOUT,
+       TEGRA_PINGROUP_DAP3_SCLK,
+       TEGRA_PINGROUP_GPIO_PV0,
+       TEGRA_PINGROUP_GPIO_PV1,
+       TEGRA_PINGROUP_SDMMC1_CLK,
+       TEGRA_PINGROUP_SDMMC1_CMD,
+       TEGRA_PINGROUP_SDMMC1_DAT3,
+       TEGRA_PINGROUP_SDMMC1_DAT2,
+       TEGRA_PINGROUP_SDMMC1_DAT1,
+       TEGRA_PINGROUP_SDMMC1_DAT0,
+       TEGRA_PINGROUP_CLK2_OUT,
+       TEGRA_PINGROUP_CLK2_REQ,
+       TEGRA_PINGROUP_HDMI_INT,
+       TEGRA_PINGROUP_DDC_SCL,
+       TEGRA_PINGROUP_DDC_SDA,
+       TEGRA_PINGROUP_UART2_RXD,
+       TEGRA_PINGROUP_UART2_TXD,
+       TEGRA_PINGROUP_UART2_RTS_N,
+       TEGRA_PINGROUP_UART2_CTS_N,
+       TEGRA_PINGROUP_UART3_TXD,
+       TEGRA_PINGROUP_UART3_RXD,
+       TEGRA_PINGROUP_UART3_CTS_N,
+       TEGRA_PINGROUP_UART3_RTS_N,
+       TEGRA_PINGROUP_GPIO_PU0,
+       TEGRA_PINGROUP_GPIO_PU1,
+       TEGRA_PINGROUP_GPIO_PU2,
+       TEGRA_PINGROUP_GPIO_PU3,
+       TEGRA_PINGROUP_GPIO_PU4,
+       TEGRA_PINGROUP_GPIO_PU5,
+       TEGRA_PINGROUP_GPIO_PU6,
+       TEGRA_PINGROUP_GEN1_I2C_SDA,
+       TEGRA_PINGROUP_GEN1_I2C_SCL,
+       TEGRA_PINGROUP_DAP4_FS,
+       TEGRA_PINGROUP_DAP4_DIN,
+       TEGRA_PINGROUP_DAP4_DOUT,
+       TEGRA_PINGROUP_DAP4_SCLK,
+       TEGRA_PINGROUP_CLK3_OUT,
+       TEGRA_PINGROUP_CLK3_REQ,
+       TEGRA_PINGROUP_GMI_WP_N,
+       TEGRA_PINGROUP_GMI_IORDY,
+       TEGRA_PINGROUP_GMI_WAIT,
+       TEGRA_PINGROUP_GMI_ADV_N,
+       TEGRA_PINGROUP_GMI_CLK,
+       TEGRA_PINGROUP_GMI_CS0_N,
+       TEGRA_PINGROUP_GMI_CS1_N,
+       TEGRA_PINGROUP_GMI_CS2_N,
+       TEGRA_PINGROUP_GMI_CS3_N,
+       TEGRA_PINGROUP_GMI_CS4_N,
+       TEGRA_PINGROUP_GMI_CS6_N,
+       TEGRA_PINGROUP_GMI_CS7_N,
+       TEGRA_PINGROUP_GMI_AD0,
+       TEGRA_PINGROUP_GMI_AD1,
+       TEGRA_PINGROUP_GMI_AD2,
+       TEGRA_PINGROUP_GMI_AD3,
+       TEGRA_PINGROUP_GMI_AD4,
+       TEGRA_PINGROUP_GMI_AD5,
+       TEGRA_PINGROUP_GMI_AD6,
+       TEGRA_PINGROUP_GMI_AD7,
+       TEGRA_PINGROUP_GMI_AD8,
+       TEGRA_PINGROUP_GMI_AD9,
+       TEGRA_PINGROUP_GMI_AD10,
+       TEGRA_PINGROUP_GMI_AD11,
+       TEGRA_PINGROUP_GMI_AD12,
+       TEGRA_PINGROUP_GMI_AD13,
+       TEGRA_PINGROUP_GMI_AD14,
+       TEGRA_PINGROUP_GMI_AD15,
+       TEGRA_PINGROUP_GMI_A16,
+       TEGRA_PINGROUP_GMI_A17,
+       TEGRA_PINGROUP_GMI_A18,
+       TEGRA_PINGROUP_GMI_A19,
+       TEGRA_PINGROUP_GMI_WR_N,
+       TEGRA_PINGROUP_GMI_OE_N,
+       TEGRA_PINGROUP_GMI_DQS_P,
+       TEGRA_PINGROUP_GMI_DQS = TEGRA_PINGROUP_GMI_DQS_P,
+       TEGRA_PINGROUP_GMI_RST_N,
+       TEGRA_PINGROUP_GEN2_I2C_SCL,
+       TEGRA_PINGROUP_GEN2_I2C_SDA,
+       TEGRA_PINGROUP_SDMMC4_CLK,
+       TEGRA_PINGROUP_SDMMC4_CMD,
+       TEGRA_PINGROUP_SDMMC4_DAT0,
+       TEGRA_PINGROUP_SDMMC4_DAT1,
+       TEGRA_PINGROUP_SDMMC4_DAT2,
+       TEGRA_PINGROUP_SDMMC4_DAT3,
+       TEGRA_PINGROUP_SDMMC4_DAT4,
+       TEGRA_PINGROUP_SDMMC4_DAT5,
+       TEGRA_PINGROUP_SDMMC4_DAT6,
+       TEGRA_PINGROUP_SDMMC4_DAT7,
+       TEGRA_PINGROUP_SDMMC4_RST_N,
+       TEGRA_PINGROUP_CAM_MCLK,
+       TEGRA_PINGROUP_GPIO_PCC1,
+       TEGRA_PINGROUP_GPIO_PBB0,
+       TEGRA_PINGROUP_CAM_I2C_SCL,
+       TEGRA_PINGROUP_CAM_I2C_SDA,
+       TEGRA_PINGROUP_GPIO_PBB3,
+       TEGRA_PINGROUP_GPIO_PBB4,
+       TEGRA_PINGROUP_GPIO_PBB5,
+       TEGRA_PINGROUP_GPIO_PBB6,
+       TEGRA_PINGROUP_GPIO_PBB7,
+       TEGRA_PINGROUP_GPIO_PCC2,
+       TEGRA_PINGROUP_JTAG_RTCK,
+       TEGRA_PINGROUP_PWR_I2C_SCL,
+       TEGRA_PINGROUP_PWR_I2C_SDA,
+       TEGRA_PINGROUP_KB_ROW0,
+       TEGRA_PINGROUP_KB_ROW1,
+       TEGRA_PINGROUP_KB_ROW2,
+       TEGRA_PINGROUP_KB_ROW3,
+       TEGRA_PINGROUP_KB_ROW4,
+       TEGRA_PINGROUP_KB_ROW5,
+       TEGRA_PINGROUP_KB_ROW6,
+       TEGRA_PINGROUP_KB_ROW7,
+       TEGRA_PINGROUP_KB_ROW8,
+       TEGRA_PINGROUP_KB_ROW9,
+       TEGRA_PINGROUP_KB_ROW10,
+       TEGRA_PINGROUP_KB_COL0,
+       TEGRA_PINGROUP_KB_COL1,
+       TEGRA_PINGROUP_KB_COL2,
+       TEGRA_PINGROUP_KB_COL3,
+       TEGRA_PINGROUP_KB_COL4,
+       TEGRA_PINGROUP_KB_COL5,
+       TEGRA_PINGROUP_KB_COL6,
+       TEGRA_PINGROUP_KB_COL7,
+       TEGRA_PINGROUP_CLK_32K_OUT,
+       TEGRA_PINGROUP_SYS_CLK_REQ,
+       TEGRA_PINGROUP_CORE_PWR_REQ,
+       TEGRA_PINGROUP_CPU_PWR_REQ,
+       TEGRA_PINGROUP_PWR_INT_N,
+       TEGRA_PINGROUP_CLK_32K_IN,
+       TEGRA_PINGROUP_OWR,
+       TEGRA_PINGROUP_DAP1_FS,
+       TEGRA_PINGROUP_DAP1_DIN,
+       TEGRA_PINGROUP_DAP1_DOUT,
+       TEGRA_PINGROUP_DAP1_SCLK,
+       TEGRA_PINGROUP_CLK1_REQ,
+       TEGRA_PINGROUP_CLK1_OUT,
+       TEGRA_PINGROUP_SPDIF_IN,
+       TEGRA_PINGROUP_SPDIF_OUT,
+       TEGRA_PINGROUP_DAP2_FS,
+       TEGRA_PINGROUP_DAP2_DIN,
+       TEGRA_PINGROUP_DAP2_DOUT,
+       TEGRA_PINGROUP_DAP2_SCLK,
+       TEGRA_PINGROUP_SPI2_MOSI,
+       TEGRA_PINGROUP_SPI2_MISO,
+       TEGRA_PINGROUP_SPI2_CS0_N,
+       TEGRA_PINGROUP_SPI2_SCK,
+       TEGRA_PINGROUP_SPI1_MOSI,
+       TEGRA_PINGROUP_SPI1_SCK,
+       TEGRA_PINGROUP_SPI1_CS0_N,
+       TEGRA_PINGROUP_SPI1_MISO,
+       TEGRA_PINGROUP_SDMMC3_CLK,
+       TEGRA_PINGROUP_SDMMC3_CMD,
+       TEGRA_PINGROUP_SDMMC3_DAT0,
+       TEGRA_PINGROUP_SDMMC3_DAT1,
+       TEGRA_PINGROUP_SDMMC3_DAT2,
+       TEGRA_PINGROUP_SDMMC3_DAT3,
+       TEGRA_PINGROUP_HDMI_CEC,
+       TEGRA_PINGROUP_SDMMC1_WP_N,
+       TEGRA_PINGROUP_SDMMC3_CD_N,
+       TEGRA_PINGROUP_SPI1_CS1_N,
+       TEGRA_PINGROUP_SPI1_CS2_N,
+       TEGRA_PINGROUP_USB_VBUS_EN0,
+       TEGRA_PINGROUP_USB_VBUS_EN1,
+       TEGRA_MAX_PINGROUP,
+};
+
+enum tegra_drive_pingroup {
+       TEGRA_DRIVE_PINGROUP_AO1 = 0,
+       TEGRA_DRIVE_PINGROUP_AO2,
+       TEGRA_DRIVE_PINGROUP_AT1,
+       TEGRA_DRIVE_PINGROUP_AT2,
+       TEGRA_DRIVE_PINGROUP_AT3,
+       TEGRA_DRIVE_PINGROUP_AT4,
+       TEGRA_DRIVE_PINGROUP_AT5,
+       TEGRA_DRIVE_PINGROUP_CDEV1,
+       TEGRA_DRIVE_PINGROUP_CDEV2,
+       TEGRA_DRIVE_PINGROUP_CSUS,
+       TEGRA_DRIVE_PINGROUP_DAP1,
+       TEGRA_DRIVE_PINGROUP_DAP2,
+       TEGRA_DRIVE_PINGROUP_DAP3,
+       TEGRA_DRIVE_PINGROUP_DAP4,
+       TEGRA_DRIVE_PINGROUP_DBG,
+       TEGRA_DRIVE_PINGROUP_SDIO3,
+       TEGRA_DRIVE_PINGROUP_SPI,
+       TEGRA_DRIVE_PINGROUP_UAA,
+       TEGRA_DRIVE_PINGROUP_UAB,
+       TEGRA_DRIVE_PINGROUP_UART2,
+       TEGRA_DRIVE_PINGROUP_UART3,
+       TEGRA_DRIVE_PINGROUP_SDIO1,
+       TEGRA_DRIVE_PINGROUP_CRT,
+       TEGRA_DRIVE_PINGROUP_DDC,
+       TEGRA_DRIVE_PINGROUP_GMA,
+       TEGRA_DRIVE_PINGROUP_GME,
+       TEGRA_DRIVE_PINGROUP_GMF,
+       TEGRA_DRIVE_PINGROUP_GMG,
+       TEGRA_DRIVE_PINGROUP_GMH,
+       TEGRA_DRIVE_PINGROUP_OWR,
+       TEGRA_DRIVE_PINGROUP_UAD,
+       TEGRA_DRIVE_PINGROUP_GPV,
+       TEGRA_DRIVE_PINGROUP_DEV3,
+       TEGRA_DRIVE_PINGROUP_CEC,
+       TEGRA_DRIVE_PINGROUP_AT6,
+       TEGRA_DRIVE_PINGROUP_DAP5,
+       TEGRA_DRIVE_PINGROUP_VBUS,
+       TEGRA_MAX_DRIVE_PINGROUP,
+};
+
+#endif
index 860ae4f..187e7a4 100644 (file)
 #ifndef __MACH_TEGRA_PINMUX_H
 #define __MACH_TEGRA_PINMUX_H
 
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+#include "pinmux-t2.h"
+#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
+#include "pinmux-t3.h"
+#elif defined(CONFIG_ARCH_TEGRA_11x_SOC)
+#include "pinmux-t11.h"
+#elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
+#include "pinmux-t12.h"
+#elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
+#include "pinmux-t14.h"
+#else
+#error "Undefined Tegra architecture"
+#endif
+
 #define TEGRA_MUX_LIST \
        TEGRA_MUX(NONE) \
        TEGRA_MUX(AHB_CLK) \
@@ -480,6 +494,10 @@ void tegra11x_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
        const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max,
        const int **gpiomap, int *gpiomap_max);
 
+void tegra12x_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
+       const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max,
+       const int **gpiomap, int *gpiomap_max);
+
 void tegra14x_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
        const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max,
        const int **gpiomap, int *gpiomap_max);
diff --git a/arch/arm/mach-tegra/pinmux-t12-tables.c b/arch/arm/mach-tegra/pinmux-t12-tables.c
new file mode 100644 (file)
index 0000000..d7e3cab
--- /dev/null
@@ -0,0 +1,424 @@
+/*
+ * linux/arch/arm/mach-tegra/pinmux-t12-tables.c
+ *
+ * Common pinmux configurations for Tegra 12x SoCs
+ *
+ * Copyright (C) 2011-2012 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/syscore_ops.h>
+#include <linux/bug.h>
+#include <linux/bitops.h>
+
+#include <mach/pinmux.h>
+#include <mach/pinmux-t12.h>
+
+#include "gpio-names.h"
+#include "iomap.h"
+
+#define PINGROUP_REG_A 0x868
+#define MUXCTL_REG_A   0x3000
+
+#define SET_DRIVE_PINGROUP(pg_name, r, drv_down_offset, drv_down_mask, drv_up_offset, drv_up_mask,     \
+       slew_rise_offset, slew_rise_mask, slew_fall_offset, slew_fall_mask)     \
+       [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {                  \
+               .name = #pg_name,                               \
+               .reg_bank = 0,                                  \
+               .reg = ((r) - PINGROUP_REG_A),                  \
+               .drvup_offset = drv_up_offset,                  \
+               .drvup_mask = drv_up_mask,                      \
+               .drvdown_offset = drv_down_offset,              \
+               .drvdown_mask = drv_down_mask,                  \
+               .slewrise_offset = slew_rise_offset,            \
+               .slewrise_mask = slew_rise_mask,                \
+               .slewfall_offset = slew_fall_offset,            \
+               .slewfall_mask = slew_fall_mask,                \
+       }
+
+#define DEFAULT_DRIVE_PINGROUP(pg_name, r)             \
+       [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {          \
+               .name = #pg_name,                       \
+               .reg_bank = 0,                          \
+               .reg = ((r) - PINGROUP_REG_A),          \
+               .drvup_offset = 20,                     \
+               .drvup_mask = 0x1f,                     \
+               .drvdown_offset = 12,                   \
+               .drvdown_mask = 0x1f,                   \
+               .slewrise_offset = 28,                  \
+               .slewrise_mask = 0x3,                   \
+               .slewfall_offset = 30,                  \
+               .slewfall_mask = 0x3,                   \
+       }
+
+const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
+       DEFAULT_DRIVE_PINGROUP(AO1,             0x868),
+       DEFAULT_DRIVE_PINGROUP(AO2,             0x86c),
+       DEFAULT_DRIVE_PINGROUP(AT1,             0x870),
+       DEFAULT_DRIVE_PINGROUP(AT2,             0x874),
+       DEFAULT_DRIVE_PINGROUP(AT3,             0x878),
+       DEFAULT_DRIVE_PINGROUP(AT4,             0x87c),
+       DEFAULT_DRIVE_PINGROUP(AT5,             0x880),
+       DEFAULT_DRIVE_PINGROUP(CDEV1,           0x884),
+       DEFAULT_DRIVE_PINGROUP(CDEV2,           0x888),
+       DEFAULT_DRIVE_PINGROUP(CSUS,            0x88c),
+       DEFAULT_DRIVE_PINGROUP(DAP1,            0x890),
+       DEFAULT_DRIVE_PINGROUP(DAP2,            0x894),
+       DEFAULT_DRIVE_PINGROUP(DAP3,            0x898),
+       DEFAULT_DRIVE_PINGROUP(DAP4,            0x89c),
+       DEFAULT_DRIVE_PINGROUP(DBG,             0x8a0),
+       DEFAULT_DRIVE_PINGROUP(SDIO3,           0x8b0),
+       DEFAULT_DRIVE_PINGROUP(SPI,             0x8b4),
+       DEFAULT_DRIVE_PINGROUP(UAA,             0x8b8),
+       DEFAULT_DRIVE_PINGROUP(UAB,             0x8bc),
+       DEFAULT_DRIVE_PINGROUP(UART2,           0x8c0),
+       DEFAULT_DRIVE_PINGROUP(UART3,           0x8c4),
+       DEFAULT_DRIVE_PINGROUP(SDIO1,           0x8ec),
+       DEFAULT_DRIVE_PINGROUP(CRT,             0x8f8),
+       DEFAULT_DRIVE_PINGROUP(DDC,             0x8fc),
+       DEFAULT_DRIVE_PINGROUP(GMA,             0x900),
+       DEFAULT_DRIVE_PINGROUP(GME,             0x910),
+       DEFAULT_DRIVE_PINGROUP(GMF,             0x914),
+       DEFAULT_DRIVE_PINGROUP(GMG,             0x918),
+       DEFAULT_DRIVE_PINGROUP(GMH,             0x91c),
+       DEFAULT_DRIVE_PINGROUP(OWR,             0x920),
+       DEFAULT_DRIVE_PINGROUP(UAD,             0x924),
+       DEFAULT_DRIVE_PINGROUP(GPV,             0x928),
+       DEFAULT_DRIVE_PINGROUP(DEV3,            0x92c),
+       DEFAULT_DRIVE_PINGROUP(CEC,             0x938),
+       DEFAULT_DRIVE_PINGROUP(AT6,             0x994),
+       DEFAULT_DRIVE_PINGROUP(DAP5,            0x998),
+       DEFAULT_DRIVE_PINGROUP(VBUS,            0x99C),
+};
+
+#define PINGROUP(pg_name, gpio_nr, vdd, f0, f1, f2, f3, fs, iod, reg)  \
+       [TEGRA_PINGROUP_ ## pg_name] = {                        \
+               .name = #pg_name,                               \
+               .vddio = TEGRA_VDDIO_ ## vdd,                   \
+               .funcs = {                                      \
+                       TEGRA_MUX_ ## f0,                       \
+                       TEGRA_MUX_ ## f1,                       \
+                       TEGRA_MUX_ ## f2,                       \
+                       TEGRA_MUX_ ## f3,                       \
+               },                                              \
+               .gpionr = TEGRA_GPIO_ ## gpio_nr,               \
+               .func_safe = TEGRA_MUX_ ## fs,                  \
+               .tri_bank = 1,                                  \
+               .tri_reg = ((reg) - MUXCTL_REG_A),              \
+               .tri_bit = 4,                                   \
+               .mux_bank = 1,                                  \
+               .mux_reg = ((reg) - MUXCTL_REG_A),              \
+               .mux_bit = 0,                                   \
+               .pupd_bank = 1,                                 \
+               .pupd_reg = ((reg) - MUXCTL_REG_A),             \
+               .pupd_bit = 2,                                  \
+               .io_default = TEGRA_PIN_ ## iod,                \
+               .od_bit = 6,                                    \
+               .lock_bit = 7,                                  \
+               .ioreset_bit = 8,                               \
+       }
+
+/* !!!FIXME!!! FILL IN fSafe COLUMN IN TABLE ....... */
+#define PINGROUPS      \
+       /*       NAME             GPIO          VDD         f0          f1          f2          f3          fSafe       io      reg */\
+       PINGROUP(ULPI_DATA0,      PO1,          BB,         SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3000),\
+       PINGROUP(ULPI_DATA1,      PO2,          BB,         SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3004),\
+       PINGROUP(ULPI_DATA2,      PO3,          BB,         SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3008),\
+       PINGROUP(ULPI_DATA3,      PO4,          BB,         SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x300c),\
+       PINGROUP(ULPI_DATA4,      PO5,          BB,         SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3010),\
+       PINGROUP(ULPI_DATA5,      PO6,          BB,         SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3014),\
+       PINGROUP(ULPI_DATA6,      PO7,          BB,         SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3018),\
+       PINGROUP(ULPI_DATA7,      PO0,          BB,         SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x301c),\
+       PINGROUP(ULPI_CLK,        PY0,          BB,         SPI1,       SPI5,       UARTD,      ULPI,       RSVD,       INPUT,  0x3020),\
+       PINGROUP(ULPI_DIR,        PY1,          BB,         SPI1,       SPI5,       UARTD,      ULPI,       RSVD,       INPUT,  0x3024),\
+       PINGROUP(ULPI_NXT,        PY2,          BB,         SPI1,       SPI5,       UARTD,      ULPI,       RSVD,       INPUT,  0x3028),\
+       PINGROUP(ULPI_STP,        PY3,          BB,         SPI1,       SPI5,       UARTD,      ULPI,       RSVD,       INPUT,  0x302c),\
+       PINGROUP(DAP3_FS,         PP0,          BB,         I2S2,       SPI5,       DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3030),\
+       PINGROUP(DAP3_DIN,        PP1,          BB,         I2S2,       SPI5,       DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3034),\
+       PINGROUP(DAP3_DOUT,       PP2,          BB,         I2S2,       SPI5,       DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3038),\
+       PINGROUP(DAP3_SCLK,       PP3,          BB,         I2S2,       SPI5,       DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x303c),\
+       PINGROUP(GPIO_PV0,        PV0,          BB,         RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3040),\
+       PINGROUP(GPIO_PV1,        PV1,          BB,         RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3044),\
+       PINGROUP(SDMMC1_CLK,      PZ0,          SDMMC1,     SDMMC1,     CLK12,      RSVD1,      RSVD2,      RSVD,       INPUT,  0x3048),\
+       PINGROUP(SDMMC1_CMD,      PZ1,          SDMMC1,     SDMMC1,     SPDIF,      SPI4,       UARTA,      RSVD,       INPUT,  0x304c),\
+       PINGROUP(SDMMC1_DAT3,     PY4,          SDMMC1,     SDMMC1,     SPDIF,      SPI4,       UARTA,      RSVD,       INPUT,  0x3050),\
+       PINGROUP(SDMMC1_DAT2,     PY5,          SDMMC1,     SDMMC1,     PWM0,       SPI4,       UARTA,      RSVD,       INPUT,  0x3054),\
+       PINGROUP(SDMMC1_DAT1,     PY6,          SDMMC1,     SDMMC1,     PWM1,       SPI4,       UARTA,      RSVD,       INPUT,  0x3058),\
+       PINGROUP(SDMMC1_DAT0,     PY7,          SDMMC1,     SDMMC1,     RSVD1,      RSVD2,      UARTA,      RSVD,       INPUT,  0x305c),\
+       PINGROUP(CLK2_OUT,        PW5,          SDMMC1,     EXTPERIPH2, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3068),\
+       PINGROUP(CLK2_REQ,        PCC5,         SDMMC1,     DAP,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x306c),\
+       PINGROUP(HDMI_INT,        PN7,          LCD,        RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3110),\
+       PINGROUP(DDC_SCL,         PV4,          LCD,        I2C4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3114),\
+       PINGROUP(DDC_SDA,         PV5,          LCD,        I2C4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3118),\
+       PINGROUP(UART2_RXD,       PC3,          UART,       IRDA,       SPDIF,      UARTA,      SPI4,       RSVD,       INPUT,  0x3164),\
+       PINGROUP(UART2_TXD,       PC2,          UART,       IRDA,       SPDIF,      UARTA,      SPI4,       RSVD,       INPUT,  0x3168),\
+       PINGROUP(UART2_RTS_N,     PJ6,          UART,       UARTA,      UARTB,      RSVD,       SPI4,       RSVD,       INPUT,  0x316c),\
+       PINGROUP(UART2_CTS_N,     PJ5,          UART,       UARTA,      UARTB,      RSVD,       SPI4,       RSVD,       INPUT,  0x3170),\
+       PINGROUP(UART3_TXD,       PW6,          UART,       UARTC,      RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3174),\
+       PINGROUP(UART3_RXD,       PW7,          UART,       UARTC,      RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3178),\
+       PINGROUP(UART3_CTS_N,     PA1,          UART,       UARTC,      SDMMC1,     RSVD1,      RSVD2,      RSVD,       INPUT,  0x317c),\
+       PINGROUP(UART3_RTS_N,     PC0,          UART,       UARTC,      PWM0,       RSVD1,      RSVD2,      RSVD,       INPUT,  0x3180),\
+       PINGROUP(GPIO_PU0,        PU0,          UART,       OWR,        UARTA,      RSVD1,      RSVD2,      RSVD,       INPUT,  0x3184),\
+       PINGROUP(GPIO_PU1,        PU1,          UART,       RSVD1,      UARTA,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3188),\
+       PINGROUP(GPIO_PU2,        PU2,          UART,       RSVD1,      UARTA,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x318c),\
+       PINGROUP(GPIO_PU3,        PU3,          UART,       PWM0,       UARTA,      RSVD1,      RSVD2,      RSVD,       INPUT,  0x3190),\
+       PINGROUP(GPIO_PU4,        PU4,          UART,       PWM1,       UARTA,      RSVD1,      RSVD2,      RSVD,       INPUT,  0x3194),\
+       PINGROUP(GPIO_PU5,        PU5,          UART,       PWM2,       UARTA,      RSVD1,      RSVD2,      RSVD,       INPUT,  0x3198),\
+       PINGROUP(GPIO_PU6,        PU6,          UART,       PWM3,       UARTA,      USB,        RSVD2,      RSVD,       INPUT,  0x319c),\
+       PINGROUP(GEN1_I2C_SDA,    PC5,          UART,       I2C1,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31a0),\
+       PINGROUP(GEN1_I2C_SCL,    PC4,          UART,       I2C1,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31a4),\
+       PINGROUP(DAP4_FS,         PP4,          UART,       I2S3,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31a8),\
+       PINGROUP(DAP4_DIN,        PP5,          UART,       I2S3,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31ac),\
+       PINGROUP(DAP4_DOUT,       PP6,          UART,       I2S3,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31b0),\
+       PINGROUP(DAP4_SCLK,       PP7,          UART,       I2S3,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31b4),\
+       PINGROUP(CLK3_OUT,        PEE0,         UART,       EXTPERIPH3, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31b8),\
+       PINGROUP(CLK3_REQ,        PEE1,         UART,       DEV3,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31bc),\
+       PINGROUP(GMI_WP_N,        PC7,          GMI,        RSVD1,      NAND,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x31c0),\
+       PINGROUP(GMI_IORDY,       PI5,          GMI,        SDMMC2,     NAND,       GMI,        TRACE,      RSVD,       INPUT,  0x31c4),\
+       PINGROUP(GMI_WAIT,        PI7,          GMI,        RSVD1,      NAND,       GMI,        TRACE,      RSVD,       INPUT,  0x31c8),\
+       PINGROUP(GMI_ADV_N,       PK0,          GMI,        SDMMC2,     NAND,       GMI,        TRACE,      RSVD,       INPUT,  0x31cc),\
+       PINGROUP(GMI_CLK,         PK1,          GMI,        SDMMC2,     NAND,       GMI,        TRACE,      RSVD,       INPUT,  0x31d0),\
+       PINGROUP(GMI_CS0_N,       PJ0,          GMI,        RSVD1,      NAND,       GMI,        RSVD,       RSVD,       INPUT,  0x31d4),\
+       PINGROUP(GMI_CS1_N,       PJ2,          GMI,        RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31d8),\
+       PINGROUP(GMI_CS2_N,       PK3,          GMI,        SDMMC2,     NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31dc),\
+       PINGROUP(GMI_CS3_N,       PK4,          GMI,        SDMMC2,     NAND,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x31e0),\
+       PINGROUP(GMI_CS4_N,       PK2,          GMI,        USB,        NAND,       GMI,        TRACE,      RSVD,       INPUT,  0x31e4),\
+       PINGROUP(GMI_CS6_N,       PI3,          GMI,        NAND,       NAND_ALT,   GMI,        SATA,       RSVD,       INPUT,  0x31e8),\
+       PINGROUP(GMI_CS7_N,       PI6,          GMI,        NAND,       NAND_ALT,   GMI,        RSVD,       RSVD,       INPUT,  0x31ec),\
+       PINGROUP(GMI_AD0,         PG0,          GMI,        RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f0),\
+       PINGROUP(GMI_AD1,         PG1,          GMI,        RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f4),\
+       PINGROUP(GMI_AD2,         PG2,          GMI,        RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f8),\
+       PINGROUP(GMI_AD3,         PG3,          GMI,        RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31fc),\
+       PINGROUP(GMI_AD4,         PG4,          GMI,        RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3200),\
+       PINGROUP(GMI_AD5,         PG5,          GMI,        RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3204),\
+       PINGROUP(GMI_AD6,         PG6,          GMI,        RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3208),\
+       PINGROUP(GMI_AD7,         PG7,          GMI,        RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x320c),\
+       PINGROUP(GMI_AD8,         PH0,          GMI,        PWM0,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3210),\
+       PINGROUP(GMI_AD9,         PH1,          GMI,        PWM1,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3214),\
+       PINGROUP(GMI_AD10,        PH2,          GMI,        PWM2,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3218),\
+       PINGROUP(GMI_AD11,        PH3,          GMI,        PWM3,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x321c),\
+       PINGROUP(GMI_AD12,        PH4,          GMI,        SDMMC2,     NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3220),\
+       PINGROUP(GMI_AD13,        PH5,          GMI,        SDMMC2,     NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3224),\
+       PINGROUP(GMI_AD14,        PH6,          GMI,        SDMMC2,     NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3228),\
+       PINGROUP(GMI_AD15,        PH7,          GMI,        SDMMC2,     NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x322c),\
+       PINGROUP(GMI_A16,         PJ7,          GMI,        UARTD,      SPI4,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x3230),\
+       PINGROUP(GMI_A17,         PB0,          GMI,        UARTD,      SPI4,       GMI,        TRACE,      RSVD,       INPUT,  0x3234),\
+       PINGROUP(GMI_A18,         PB1,          GMI,        UARTD,      SPI4,       GMI,        TRACE,      RSVD,       INPUT,  0x3238),\
+       PINGROUP(GMI_A19,         PK7,          GMI,        UARTD,      SPI4,       GMI,        TRACE,      RSVD,       INPUT,  0x323c),\
+       PINGROUP(GMI_WR_N,        PI0,          GMI,        RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3240),\
+       PINGROUP(GMI_OE_N,        PI1,          GMI,        RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3244),\
+       PINGROUP(GMI_DQS_P,       PJ3,          GMI,        SDMMC2,     NAND,       GMI,        TRACE,      RSVD,       INPUT,  0x3248),\
+       PINGROUP(GMI_RST_N,       PI4,          GMI,        NAND,       NAND_ALT,   GMI,        SDMMC2,     RSVD,       INPUT,  0x324c),\
+       PINGROUP(GEN2_I2C_SCL,    PT5,          GMI,        I2C2,       RSVD1,      GMI,        RSVD3,      RSVD,       INPUT,  0x3250),\
+       PINGROUP(GEN2_I2C_SDA,    PT6,          GMI,        I2C2,       RSVD1,      GMI,        RSVD3,      RSVD,       INPUT,  0x3254),\
+       PINGROUP(SDMMC4_CLK,      PCC4,         SDMMC4,     SDMMC4,     RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x3258),\
+       PINGROUP(SDMMC4_CMD,      PT7,          SDMMC4,     SDMMC4,     RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x325c),\
+       PINGROUP(SDMMC4_DAT0,     PAA0,         SDMMC4,     SDMMC4,     SPI3,       GMI,        RSVD2,      RSVD,       INPUT,  0x3260),\
+       PINGROUP(SDMMC4_DAT1,     PAA1,         SDMMC4,     SDMMC4,     SPI3,       GMI,        RSVD2,      RSVD,       INPUT,  0x3264),\
+       PINGROUP(SDMMC4_DAT2,     PAA2,         SDMMC4,     SDMMC4,     SPI3,       GMI,        RSVD2,      RSVD,       INPUT,  0x3268),\
+       PINGROUP(SDMMC4_DAT3,     PAA3,         SDMMC4,     SDMMC4,     SPI3,       GMI,        RSVD2,      RSVD,       INPUT,  0x326c),\
+       PINGROUP(SDMMC4_DAT4,     PAA4,         SDMMC4,     SDMMC4,     RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x3270),\
+       PINGROUP(SDMMC4_DAT5,     PAA5,         SDMMC4,     SDMMC4,     RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x3274),\
+       PINGROUP(SDMMC4_DAT6,     PAA6,         SDMMC4,     SDMMC4,     RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x3278),\
+       PINGROUP(SDMMC4_DAT7,     PAA7,         SDMMC4,     SDMMC4,     RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x327c),\
+       PINGROUP(SDMMC4_RST_N,    INVALID,      SDMMC4,     RSVD1,      RSVD2,      RSVD3,      SDMMC4,     RSVD,       INPUT,  0x3280),\
+       PINGROUP(CAM_MCLK,        PCC0,         CAM,        VI,         INVALID,    VI_ALT2,    RSVD,       RSVD,       INPUT,  0x3284),\
+       PINGROUP(GPIO_PCC1,       PCC1,         CAM,        I2S4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3288),\
+       PINGROUP(GPIO_PBB0,       PBB0,         CAM,        I2S4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x328c),\
+       PINGROUP(CAM_I2C_SCL,     PBB1,         CAM,        INVALID,    I2C3,       RSVD2,      RSVD3,      RSVD,       INPUT,  0x3290),\
+       PINGROUP(CAM_I2C_SDA,     PBB2,         CAM,        INVALID,    I2C3,       RSVD2,      RSVD3,      RSVD,       INPUT,  0x3294),\
+       PINGROUP(GPIO_PBB3,       PBB3,         CAM,        VGP3,       DISPLAYA,   DISPLAYB,   RSVD2,      RSVD,       INPUT,  0x3298),\
+       PINGROUP(GPIO_PBB4,       PBB4,         CAM,        VGP4,       DISPLAYA,   DISPLAYB,   RSVD2,      RSVD,       INPUT,  0x329c),\
+       PINGROUP(GPIO_PBB5,       PBB5,         CAM,        VGP5,       DISPLAYA,   DISPLAYB,   RSVD,       RSVD,       INPUT,  0x32a0),\
+       PINGROUP(GPIO_PBB6,       PBB6,         CAM,        VGP6,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x32a4),\
+       PINGROUP(GPIO_PBB7,       PBB7,         CAM,        I2S4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32a8),\
+       PINGROUP(GPIO_PCC2,       PCC2,         CAM,        I2S4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32ac),\
+       PINGROUP(JTAG_RTCK,       PU7,          SYS,        RTCK,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b0),\
+       PINGROUP(PWR_I2C_SCL,     PZ6,          SYS,        I2CPWR,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b4),\
+       PINGROUP(PWR_I2C_SDA,     PZ7,          SYS,        I2CPWR,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b8),\
+       PINGROUP(KB_ROW0,         PR0,          SYS,        KBC,        RSVD2,      DTV,        RSVD3,      RSVD,       INPUT,  0x32bc),\
+       PINGROUP(KB_ROW1,         PR1,          SYS,        KBC,        RSVD2,      DTV,        RSVD3,      RSVD,       INPUT,  0x32c0),\
+       PINGROUP(KB_ROW2,         PR2,          SYS,        KBC,        RSVD2,      DTV,        RSVD3,      RSVD,       INPUT,  0x32c4),\
+       PINGROUP(KB_ROW3,         PR3,          SYS,        KBC,        DISPLAYA,   DTV,        DISPLAYB,   RSVD,       INPUT,  0x32c8),\
+       PINGROUP(KB_ROW4,         PR4,          SYS,        KBC,        DISPLAYA,   SPI2,       DISPLAYB,   RSVD,       INPUT,  0x32cc),\
+       PINGROUP(KB_ROW5,         PR5,          SYS,        KBC,        DISPLAYA,   SPI2,       DISPLAYB,   RSVD,       INPUT,  0x32d0),\
+       PINGROUP(KB_ROW6,         PR6,          SYS,        KBC,        DISPLAYA,   RSVD,       DISPLAYB,   RSVD,       INPUT,  0x32d4),\
+       PINGROUP(KB_ROW7,         PR7,          SYS,        KBC,        RSVD,       RSVD2,      UARTA,      RSVD,       INPUT,  0x32d8),\
+       PINGROUP(KB_ROW8,         PS0,          SYS,        KBC,        RSVD,       RSVD2,      UARTA,      RSVD,       INPUT,  0x32dc),\
+       PINGROUP(KB_ROW9,         PS1,          SYS,        KBC,        RSVD,       RSVD2,      UARTA,      RSVD,       INPUT,  0x32e0),\
+       PINGROUP(KB_ROW10,        PS2,          SYS,        KBC,        RSVD,       RSVD2,      UARTA,      RSVD,       INPUT,  0x32e4),\
+       PINGROUP(KB_COL0,         PQ0,          SYS,        KBC,        USB,        SPI2,       EMC_DLL,    RSVD,       INPUT,  0x32fc),\
+       PINGROUP(KB_COL1,         PQ1,          SYS,        KBC,        RSVD2,      SPI2,       EMC_DLL,    RSVD,       INPUT,  0x3300),\
+       PINGROUP(KB_COL2,         PQ2,          SYS,        KBC,        RSVD2,      SPI2,       RSVD,       RSVD,       INPUT,  0x3304),\
+       PINGROUP(KB_COL3,         PQ3,          SYS,        KBC,        RSVD2,      PWM2,       RSVD,       RSVD,       INPUT,  0x3308),\
+       PINGROUP(KB_COL4,         PQ4,          SYS,        KBC,        OWR,        SDMMC3,     UARTA,      RSVD,       INPUT,  0x330c),\
+       PINGROUP(KB_COL5,         PQ5,          SYS,        KBC,        RSVD1,      SDMMC1,     RSVD2,      RSVD,       INPUT,  0x3310),\
+       PINGROUP(KB_COL6,         PQ6,          SYS,        KBC,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3314),\
+       PINGROUP(KB_COL7,         PQ7,          SYS,        KBC,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3318),\
+       PINGROUP(CLK_32K_OUT,     PA0,          SYS,        BLINK,      RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x331c),\
+       PINGROUP(SYS_CLK_REQ,     PZ5,          SYS,        SYSCLK,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3320),\
+       PINGROUP(CORE_PWR_REQ,    INVALID,      SYS,        RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3324),\
+       PINGROUP(CPU_PWR_REQ,     INVALID,      SYS,        RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3328),\
+       PINGROUP(PWR_INT_N,       INVALID,      SYS,        RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x332c),\
+       PINGROUP(CLK_32K_IN,      INVALID,      SYS,        RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3330),\
+       PINGROUP(OWR,             INVALID,      SYS,        RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3334),\
+       PINGROUP(DAP1_FS,         PN0,          AUDIO,      I2S0,       HDA,        GMI,        RSVD,       RSVD,       INPUT,  0x3338),\
+       PINGROUP(DAP1_DIN,        PN1,          AUDIO,      I2S0,       HDA,        GMI,        RSVD,       RSVD,       INPUT,  0x333c),\
+       PINGROUP(DAP1_DOUT,       PN2,          AUDIO,      I2S0,       HDA,        GMI,        RSVD,       RSVD,       INPUT,  0x3340),\
+       PINGROUP(DAP1_SCLK,       PN3,          AUDIO,      I2S0,       HDA,        GMI,        RSVD,       RSVD,       INPUT,  0x3344),\
+       PINGROUP(CLK1_REQ,        PEE2,         AUDIO,      DAP,        HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x3348),\
+       PINGROUP(CLK1_OUT,        PW4,          AUDIO,      EXTPERIPH1, DAP2,       RSVD2,      RSVD3,      RSVD,       INPUT,  0x334c),\
+       PINGROUP(SPDIF_IN,        PK6,          AUDIO,      SPDIF,      RSVD1,      I2C1,       RSVD2,      RSVD,       INPUT,  0x3350),\
+       PINGROUP(SPDIF_OUT,       PK5,          AUDIO,      SPDIF,      RSVD1,      I2C1,       RSVD2,      RSVD,       INPUT,  0x3354),\
+       PINGROUP(DAP2_FS,         PA2,          AUDIO,      I2S1,       HDA,        RSVD1,      RSVD2,      RSVD,       INPUT,  0x3358),\
+       PINGROUP(DAP2_DIN,        PA4,          AUDIO,      I2S1,       HDA,        RSVD1,      RSVD2,      RSVD,       INPUT,  0x335c),\
+       PINGROUP(DAP2_DOUT,       PA5,          AUDIO,      I2S1,       HDA,        RSVD1,      RSVD2,      RSVD,       INPUT,  0x3360),\
+       PINGROUP(DAP2_SCLK,       PA3,          AUDIO,      I2S1,       HDA,        RSVD1,      RSVD2,      RSVD,       INPUT,  0x3364),\
+       PINGROUP(SPI2_MOSI,       PX0,          AUDIO,      SPI6,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3368),\
+       PINGROUP(SPI2_MISO,       PX1,          AUDIO,      SPI6,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x336c),\
+       PINGROUP(SPI2_CS0_N,      PX3,          AUDIO,      SPI6,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3370),\
+       PINGROUP(SPI2_SCK,        PX2,          AUDIO,      SPI6,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3374),\
+       PINGROUP(SPI1_MOSI,       PX4,          AUDIO,      SPI6,       RSVD1,      RSVD2,      DAP2,       RSVD,       INPUT,  0x3378),\
+       PINGROUP(SPI1_SCK,        PX5,          AUDIO,      SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x337c),\
+       PINGROUP(SPI1_CS0_N,      PX6,          AUDIO,      SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x3380),\
+       PINGROUP(SPI1_MISO,       PX7,          AUDIO,      RSVD1,      SPI1,       SPI2,       RSVD2,      RSVD,       INPUT,  0x3384),\
+       PINGROUP(SDMMC3_CLK,      PA6,          SDMMC3,     SDMMC3,     RSVD1,      RSVD2,      SPI3,       RSVD,       INPUT,  0x3390),\
+       PINGROUP(SDMMC3_CMD,      PA7,          SDMMC3,     SDMMC3,     PWM3,       UARTA,      RSVD,       RSVD,       INPUT,  0x3394),\
+       PINGROUP(SDMMC3_DAT0,     PB7,          SDMMC3,     SDMMC3,     PWM3,       RSVD3,      SPI3,       RSVD,       INPUT,  0x3398),\
+       PINGROUP(SDMMC3_DAT1,     PB6,          SDMMC3,     SDMMC3,     RSVD1,      UARTA,      SPI3,       RSVD,       INPUT,  0x339c),\
+       PINGROUP(SDMMC3_DAT2,     PB5,          SDMMC3,     SDMMC3,     PWM2,       RSVD,       SPI3,       RSVD,       INPUT,  0x33a0),\
+       PINGROUP(SDMMC3_DAT3,     PB4,          SDMMC3,     SDMMC3,     PWM1,       RSVD,       SPI3,       RSVD,       INPUT,  0x33a4),\
+       PINGROUP(HDMI_CEC,        PEE3,         SYS,        CEC,        SDMMC3,     RSVD2,      RSVD3,      RSVD,       INPUT,  0x33e0),\
+       PINGROUP(SDMMC1_WP_N,     PV3,          SDMMC1,     SDMMC1,     CLK12,      RSVD2,      UARTA,      RSVD,       INPUT,  0x33e4),\
+       PINGROUP(SDMMC3_CD_N,     PV2,          SDMMC3,     CLK12,      RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x33e8),\
+       PINGROUP(SPI1_CS1_N,      PW2,          AUDIO,      RSVD1,      SPI1,       SPI2,       I2C1,       RSVD,       INPUT,  0x33ec),\
+       PINGROUP(SPI1_CS2_N,      PW3,          AUDIO,      RSVD1,      SPI1,       SPI2,       I2C1,       RSVD,       INPUT,  0x33f0),\
+       PINGROUP(USB_VBUS_EN0,    PN4,          SYS,        RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x33f4),\
+       PINGROUP(USB_VBUS_EN1,    PM5,          SYS,        RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x33f8),\
+
+const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
+       PINGROUPS
+};
+
+#undef PINGROUP
+
+#define PINGROUP(pg_name, gpio_nr, vdd, f0, f1, f2, f3, fs, iod, reg)  \
+       [TEGRA_GPIO_##gpio_nr] =  TEGRA_PINGROUP_ ##pg_name\
+
+const int gpio_to_pingroup[TEGRA_MAX_GPIO] = {
+       PINGROUPS
+
+};
+
+#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
+       {                                                       \
+               .pingroup = TEGRA_DRIVE_PINGROUP_##_name,       \
+               .hsm = TEGRA_HSM_##_hsm,                        \
+               .schmitt = TEGRA_SCHMITT_##_schmitt,            \
+               .drive = TEGRA_DRIVE_##_drive,                  \
+               .pull_down = TEGRA_PULL_##_pulldn_drive,        \
+               .pull_up = TEGRA_PULL_##_pullup_drive,          \
+               .slew_rising = TEGRA_SLEW_##_pulldn_slew,       \
+               .slew_falling = TEGRA_SLEW_##_pullup_slew,      \
+       }
+
+static __initdata struct tegra_drive_pingroup_config t12x_def_drive_pinmux[] = {
+       SET_DRIVE(DAP2, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+};
+
+#ifdef CONFIG_PM_SLEEP
+
+static u32 pinmux_reg[TEGRA_MAX_PINGROUP + ARRAY_SIZE(tegra_soc_drive_pingroups)];
+
+static int tegra12x_pinmux_suspend(void)
+{
+       unsigned int i;
+       u32 *ctx = pinmux_reg;
+
+       for (i = 0; i < TEGRA_MAX_PINGROUP; i++)
+               *ctx++ = pg_readl(tegra_soc_pingroups[i].mux_bank,
+                               tegra_soc_pingroups[i].mux_reg);
+
+       for (i = 0; i < ARRAY_SIZE(tegra_soc_drive_pingroups); i++)
+               *ctx++ = pg_readl(tegra_soc_drive_pingroups[i].reg_bank,
+                               tegra_soc_drive_pingroups[i].reg);
+
+       return 0;
+}
+
+#define PMC_IO_DPD_REQ         0x1B8
+#define PMC_IO_DPD2_REQ                0x1C0
+
+static void tegra12x_pinmux_resume(void)
+{
+       void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+       unsigned int i;
+       u32 *ctx = pinmux_reg;
+       u32 *tmp = pinmux_reg;
+       u32 reg_value;
+
+       for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
+               reg_value = *tmp++;
+               reg_value |= BIT(4); /* tristate */
+               pg_writel(reg_value, tegra_soc_pingroups[i].mux_bank,
+                       tegra_soc_pingroups[i].mux_reg);
+       }
+
+       writel(0x400fffff, pmc_base + PMC_IO_DPD_REQ);
+       writel(0x40001fff, pmc_base + PMC_IO_DPD2_REQ);
+
+       for (i = 0; i < TEGRA_MAX_PINGROUP; i++)
+               pg_writel(*ctx++, tegra_soc_pingroups[i].mux_bank,
+                       tegra_soc_pingroups[i].mux_reg);
+
+       for (i = 0; i < ARRAY_SIZE(tegra_soc_drive_pingroups); i++)
+               pg_writel(*ctx++, tegra_soc_drive_pingroups[i].reg_bank,
+                       tegra_soc_drive_pingroups[i].reg);
+}
+
+static struct syscore_ops tegra_pinmux_syscore_ops = {
+       .suspend = tegra12x_pinmux_suspend,
+       .resume = tegra12x_pinmux_resume,
+};
+#endif
+
+void __devinit tegra12x_pinmux_init(const struct tegra_pingroup_desc **pg,
+               int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
+               int *pgdrive_max, const int **gpiomap, int *gpiomap_max)
+{
+       *pg = tegra_soc_pingroups;
+       *pg_max = TEGRA_MAX_PINGROUP;
+       *pgdrive = tegra_soc_drive_pingroups;
+       *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
+       *gpiomap = gpio_to_pingroup;
+       *gpiomap_max = TEGRA_MAX_GPIO;
+
+#ifdef CONFIG_PM_SLEEP
+       register_syscore_ops(&tegra_pinmux_syscore_ops);
+#endif
+}
+
+void tegra12x_default_pinmux(void)
+{
+       tegra_drive_pinmux_config_table(t12x_def_drive_pinmux,
+                                       ARRAY_SIZE(t12x_def_drive_pinmux));
+}
index 5fc148f..73c69bf 100644 (file)
@@ -984,6 +984,9 @@ static struct of_device_id tegra_pinmux_of_match[] = {
 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
        { .compatible = "nvidia,tegra11x-pinmux-ctl", tegra11x_pinmux_init },
 #endif
+#ifdef CONFIG_ARCH_TEGRA_12x_SOC
+       { .compatible = "nvidia,tegra11x-pinmux", tegra12x_pinmux_init },
+#endif
 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
        { .compatible = "nvidia,tegra14x-pinmux", tegra14x_pinmux_init },
 #endif
@@ -1094,6 +1097,10 @@ static struct platform_device_id tegra_pinmux_id[] = {
        { .name = "tegra11x-pinmux-ctl",
          .driver_data = (kernel_ulong_t)tegra11x_pinmux_init, },
 #endif
+#ifdef CONFIG_ARCH_TEGRA_12x_SOC
+       { .name = "tegra12x-pinmux",
+         .driver_data = (kernel_ulong_t)tegra12x_pinmux_init, },
+#endif
 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
        { .name = "tegra14x-pinmux",
          .driver_data = (kernel_ulong_t)tegra14x_pinmux_init, },