ARM: tegra: New macro name for LP2 timer config
Bo Yan [Tue, 24 Jul 2012 17:03:39 +0000 (10:03 -0700)]
The config macro TEGRA_LP2_ARM_TWD was defined when only Cortex-A9
was used in Tegra SoC, but the feature enabled by this configuration
option is not just for Cortex-A9. In fact, any CPU with private timer
can make use of this feature. Therefore, change macro name to a more
generic one "TEGRA_LP2_CPU_TIMER" so it can be used with new CPU
architecture (CortexA15)

Change-Id: I6903dba056c554c72bb8d1416df90145a4043295
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/118099
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

Rebase-Id: R0da9d17d0281e91f5908099579b8eaaf4b01a024

arch/arm/mach-tegra/Kconfig
arch/arm/mach-tegra/cpuidle-t3.c
arch/arm/mach-tegra/pm.h
chromeos/config/armel/config.flavour.chromeos-tegra3

index 4b5a6c0..60c8ac9 100644 (file)
@@ -64,7 +64,7 @@ config ARCH_TEGRA_3x_SOC
        select PINCTRL_TEGRA30
        select PL310_ERRATA_769419 if CACHE_L2X0
        select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
-       select TEGRA_LP2_ARM_TWD if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS
+       select TEGRA_LP2_CPU_TIMER if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS
        select USB_ARCH_HAS_EHCI if USB_SUPPORT
        select USB_ULPI if USB_PHY
        select USB_ULPI_VIEWPORT if USB_PHY
@@ -326,7 +326,7 @@ config TEGRA_WDT_RECOVERY
          Enables watchdog recovery mechanism to protect against
          suspend/resume hangs.
 
-config TEGRA_LP2_ARM_TWD
+config TEGRA_LP2_CPU_TIMER
        bool
 
 config TEGRA_RAIL_OFF_MULTIPLE_CPUS
index a451b93..05e4b4a 100644 (file)
@@ -365,7 +365,7 @@ static bool tegra3_idle_enter_lp2_cpu_n(struct cpuidle_device *dev,
        struct tegra_twd_context twd_context;
        bool sleep_completed = false;
        struct tick_sched *ts = tick_get_tick_sched(dev->cpu);
-#ifdef CONFIG_TEGRA_LP2_ARM_TWD
+#ifdef CONFIG_TEGRA_LP2_CPU_TIMER
        void __iomem *twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
 #endif
 
@@ -376,7 +376,7 @@ static bool tegra3_idle_enter_lp2_cpu_n(struct cpuidle_device *dev,
                    (twd_context.twd_ctrl & TWD_TIMER_CONTROL_IT_ENABLE)) {
                        request = div_u64((u64)twd_context.twd_cnt * 1000000,
                                          twd_rate);
-#ifdef CONFIG_TEGRA_LP2_ARM_TWD
+#ifdef CONFIG_TEGRA_LP2_CPU_TIMER
                        if (request >= state->target_residency) {
                                twd_context.twd_cnt -= state->exit_latency *
                                        (twd_rate / 1000000);
@@ -397,7 +397,7 @@ static bool tegra3_idle_enter_lp2_cpu_n(struct cpuidle_device *dev,
                return false;
        }
 
-#ifndef CONFIG_TEGRA_LP2_ARM_TWD
+#ifndef CONFIG_TEGRA_LP2_CPU_TIMER
        sleep_time = request - state->exit_latency;
        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
        tegra_twd_suspend(&twd_context);
@@ -425,7 +425,7 @@ static bool tegra3_idle_enter_lp2_cpu_n(struct cpuidle_device *dev,
 
        tegra_cpu_wake_by_time[dev->cpu] = LLONG_MAX;
 
-#ifdef CONFIG_TEGRA_LP2_ARM_TWD
+#ifdef CONFIG_TEGRA_LP2_CPU_TIMER
        if (!tegra_twd_get_state(&twd_context))
                sleep_completed = (twd_context.twd_cnt == 0);
 #else
index 84a4000..d729d5d 100644 (file)
@@ -186,7 +186,7 @@ static inline unsigned long tegra_lp2_timer_remain(void)
 
 static inline int tegra_is_lp2_timer_ready(unsigned int cpu)
 {
-#if defined(CONFIG_TEGRA_LP2_ARM_TWD) || defined(CONFIG_ARCH_TEGRA_2x_SOC)
+#if defined(CONFIG_TEGRA_LP2_CPU_TIMER) || defined(CONFIG_ARCH_TEGRA_2x_SOC)
        return 1;
 #else
        return tegra3_is_lp2_timer_ready(cpu);
index 1b6f875..25dffee 100644 (file)
@@ -105,7 +105,7 @@ CONFIG_TEGRA_EDP_LIMITS=y
 CONFIG_TEGRA_EMC_TO_DDR_CLOCK=1
 CONFIG_TEGRA_IOVMM_SMMU=y
 # CONFIG_TEGRA_IOVMM_SMMU_SYSFS is not set
-CONFIG_TEGRA_LP2_ARM_TWD=y
+CONFIG_TEGRA_LP2_CPU_TIMER=y
 # CONFIG_TEGRA_MC_EARLY_ACK is not set
 CONFIG_TEGRA_PCI=y
 CONFIG_TEGRA_PLLM_RESTRICTED=y