spi: tegra: fixed polling mode tranfer timeout
snchen [Fri, 14 Oct 2016 09:44:57 +0000 (17:44 +0800)]
The change "set INTR_MASK only once" cause polling mode failed.

Interrupt mask has to be cleared in case of polling mode during setup.
Check against transfer direction is invalid during setup and will fail.
Removed direction check.

bug 1818284

Signed-off-by: snchen <snchen@nvidia.com>
Change-Id: I8f5c0f5685e6f0e311deadc4a32c0aade40dd572
Reviewed-on: http://git-master/r/1241690
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

drivers/spi/spi-tegra114.c

index e529827..015e943 100644 (file)
@@ -1242,15 +1242,12 @@ static int tegra_spi_setup(struct spi_device *spi)
        }
 
        if (tspi->chip_data->intr_mask_reg) {
-               if ((tspi->cur_direction & DATA_DIR_TX) ||
-                   (tspi->cur_direction & DATA_DIR_RX)) {
-                       intr_mask = tegra_spi_readl(tspi, SPI_INTR_MASK);
-                       if (!tspi->polling_mode)
-                               intr_mask &= ~(SPI_INTR_ALL_MASK);
-                       else
-                               intr_mask |= SPI_INTR_ALL_MASK;
-                       tegra_spi_writel(tspi, intr_mask, SPI_INTR_MASK);
-               }
+               intr_mask = tegra_spi_readl(tspi, SPI_INTR_MASK);
+               if (!tspi->polling_mode)
+                       intr_mask &= ~(SPI_INTR_ALL_MASK);
+               else
+                       intr_mask |= SPI_INTR_ALL_MASK;
+               tegra_spi_writel(tspi, intr_mask, SPI_INTR_MASK);
        }
        spin_lock_irqsave(&tspi->lock, flags);
        val = tspi->def_command1_reg;