tegra: dc: Round up target HDMI rate
Alex Frid [Sat, 19 Dec 2015 22:49:47 +0000 (14:49 -0800)]
Since Tegra Clock Framework rounds down when module clock divider is
determined, rounded up target rate for sor clock switch to compensate.

Bug 200162245

Change-Id: Ic6fde0ebf32143609a399a9f6ed2b6805d9f7029
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/926981
Reviewed-by: Aly Hirani <ahirani@nvidia.com>
Tested-by: Aly Hirani <ahirani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>

drivers/video/tegra/dc/hdmi2.0.c

index 1229717..5bbf866 100644 (file)
@@ -1909,8 +1909,8 @@ static void tegra_hdmi_config_clk(struct tegra_hdmi *hdmi, u32 clk_type)
                        clk_get_rate(clk_get_parent(sor->src_switch_clk));
 
                /* Set sor divider */
-               if (rate != parent_rate / div) {
-                       rate = parent_rate / div;
+               if (rate != DIV_ROUND_UP(parent_rate, div)) {
+                       rate = DIV_ROUND_UP(parent_rate, div);
                        clk_set_rate(sor->src_switch_clk, rate);
                }