video: tegra: dc: Add pixel width setting for even/odd split
Ken Chang [Tue, 21 Apr 2015 09:48:29 +0000 (17:48 +0800)]
Add support of configuring pixel width for symmetric even/odd
ganged mode. The value can be configured by dt property
'nvidia,dsi-even-odd-pixel-width'.
If the panel's dsi-ganged-type is
'TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD' and does not have this
dt property, the pixel width is set to 1 by default.

Bug 1609219

Change-Id: I96205754875ea9f5c2e2a5c7f8e8034ef74240e2
Signed-off-by: Ken Chang <kenc@nvidia.com>
Reviewed-on: http://git-master/r/733560
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

Documentation/devicetree/bindings/video/nvidia,tegra210-dsi.txt
arch/arm/mach-tegra/include/mach/dc.h
drivers/video/tegra/dc/dsi.c
drivers/video/tegra/dc/fake_panel.c
drivers/video/tegra/dc/of_dc.c

index bf9b0f4..1c71724 100644 (file)
@@ -71,6 +71,7 @@ NVIDIA TEGRA210 Display Serial Interface
  - nvidia,dsi-te-gpio: specifies a GPIO used for dsi panel TE signal.
  - nvidia,nvidia,dsi-ganged-type: specifies dsi ganged type. 1 for TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT,
    2 for TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD, 3 for TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP
+ - nvidia,dsi-even-odd-pixel-width: pixel width for symmetric even/odd split, max value is 0x1FFF.
  - nvidia,dsi-phy-hsdexit: dsi phy timing, t_hsdexit_ns.
  - nvidia,dsi-phy-hstrail: dsi phy timing, t_hstrail_ns.
  - nvidia,dsi-phy-datzero: dsi phy timing, t_datzero_ns.
index a0f4909..c9ac2aa 100644 (file)
@@ -332,6 +332,7 @@ struct tegra_dsi_out {
        u16             dsi_panel_rst_gpio;
        u16             dsi_panel_bl_en_gpio;
        u16             dsi_panel_bl_pwm_gpio;
+       u16             even_odd_split_width;
        u8              controller_vs;
 
        bool            panel_has_frame_buffer; /* required*/
index 4ad8aa0..fe9a1a3 100644 (file)
@@ -2948,11 +2948,12 @@ static void tegra_dsi_ganged(struct tegra_dc *dc,
                        DSI_GANGED_MODE_START, dsi_instances[0]);
                /* DSI 1 */
                tegra_dsi_controller_writel(dsi,
-                       DSI_GANGED_MODE_START_POINTER(1),
+                       DSI_GANGED_MODE_START_POINTER(
+                               dsi->info.even_odd_split_width),
                        DSI_GANGED_MODE_START, dsi_instances[1]);
 
-               low_width = 0x1;
-               high_width = 0x1;
+               low_width = dsi->info.even_odd_split_width;
+               high_width = dsi->info.even_odd_split_width;
                val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
                        DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
        }
index be9d5de..a0188c4 100644 (file)
@@ -229,6 +229,7 @@ static int tegra_dc_reset_fakedsi_panel(struct tegra_dc *dc, long dc_outtype)
        struct tegra_dc_out *dc_out = dc->out;
        if (dc_outtype == TEGRA_DC_OUT_FAKE_DSI_GANGED) {
                dc_out->dsi->ganged_type = TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD;
+               dc_out->dsi->even_odd_split_width = 1;
                dc_out->dsi->dsi_instance = 0;
                dc_out->dsi->n_data_lanes = 8;
        } else if (dc_outtype == TEGRA_DC_OUT_FAKE_DSIB) {
index 609a07e..6e18409 100644 (file)
@@ -1219,6 +1219,16 @@ static struct device_node *parse_dsi_settings(struct platform_device *ndev,
                "nvidia,dsi-ganged-type", &temp)) {
                dsi->ganged_type = (u8)temp;
                OF_DC_LOG("dsi ganged_type %d\n", dsi->ganged_type);
+               /* Set pixel width to 1 by default for even-odd split */
+               if (dsi->ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD)
+                       dsi->even_odd_split_width = 1;
+       }
+
+       if (!of_property_read_u32(np_dsi_panel,
+               "nvidia,dsi-even-odd-pixel-width", &temp)) {
+               dsi->even_odd_split_width = temp;
+               OF_DC_LOG("dsi pixel width for even/odd split %d\n",
+                               dsi->even_odd_split_width);
        }
 
        if (!of_property_read_u32(np_dsi_panel,