ARM: tegra: Use tegra_read_chipid()
Dan Willemsen [Wed, 4 Sep 2013 07:55:52 +0000 (00:55 -0700)]
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Change-Id: Idd0fe0289c1b047d2418289151006f0cbec67948

arch/arm/mach-tegra/tegra11_clocks.c
arch/arm/mach-tegra/tegra12_clocks.c
arch/arm/mach-tegra/tegra14_clocks.c
drivers/hwmon/tegra-tsensor.c

index 0c358d2..3d1567b 100644 (file)
@@ -30,6 +30,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/platform_device.h>
 #include <linux/clk/tegra.h>
+#include <linux/tegra-soc.h>
 
 #include <asm/clkdev.h>
 
@@ -568,7 +569,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
 static void __iomem *reg_xusb_padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
 
-#define MISC_GP_HIDREV                         0x804
 #define MISC_GP_TRANSACTOR_SCRATCH_0           0x864
 #define MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE   (0x1 << 1)
 #define MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE  (0x1 << 2)
@@ -590,8 +590,6 @@ static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
        __raw_writel(value, reg_pmc_base + (reg))
 #define pmc_readl(reg) \
        __raw_readl(reg_pmc_base + (reg))
-#define chipid_readl() \
-       __raw_readl(misc_gp_base + MISC_GP_HIDREV)
 #define xusb_padctl_writel(value, reg) \
        __raw_writel(value, reg_xusb_padctl_base + (reg))
 #define xusb_padctl_readl(reg) \
@@ -4020,7 +4018,7 @@ static void tegra11_periph_clk_disable(struct clk *c)
                 * flush the write operation in apb bus. This will avoid the
                 * peripheral access after disabling clock*/
                if (c->flags & PERIPH_ON_APB)
-                       val = chipid_readl();
+                       val = tegra_read_chipid();
 
                clk_writel_delay(
                        PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
@@ -4044,7 +4042,7 @@ static void tegra11_periph_clk_reset(struct clk *c, bool assert)
                         * will avoid the peripheral access after disabling
                         * clock */
                        if (c->flags & PERIPH_ON_APB)
-                               val = chipid_readl();
+                               val = tegra_read_chipid();
 
                        clk_writel(PERIPH_CLK_TO_BIT(c),
                                   PERIPH_CLK_TO_RST_SET_REG(c));
index 9802a6f..2b21b06 100644 (file)
@@ -29,6 +29,7 @@
 #include <linux/cpufreq.h>
 #include <linux/syscore_ops.h>
 #include <linux/platform_device.h>
+#include <linux/tegra-soc.h>
 
 #include <asm/clkdev.h>
 
@@ -633,7 +634,6 @@ static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
 
-#define MISC_GP_HIDREV                         0x804
 #define MISC_GP_TRANSACTOR_SCRATCH_0           0x864
 #define MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE   (0x1 << 1)
 #define MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE  (0x1 << 2)
@@ -655,8 +655,6 @@ static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
        __raw_writel(value,(void *)((u32)reg_pmc_base + (reg)))
 #define pmc_readl(reg) \
        __raw_readl((void *)((u32)reg_pmc_base + (reg)))
-#define chipid_readl() \
-       __raw_readl((void *)((u32)misc_gp_base + MISC_GP_HIDREV))
 
 #define clk_writel_delay(value, reg)                                   \
        do {                                                            \
@@ -4273,7 +4271,7 @@ static void tegra12_periph_clk_disable(struct clk *c)
                 * flush the write operation in apb bus. This will avoid the
                 * peripheral access after disabling clock*/
                if (c->flags & PERIPH_ON_APB)
-                       val = chipid_readl();
+                       val = tegra_read_chipid();
 
                clk_writel_delay(
                        PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
@@ -4297,7 +4295,7 @@ static void tegra12_periph_clk_reset(struct clk *c, bool assert)
                         * will avoid the peripheral access after disabling
                         * clock */
                        if (c->flags & PERIPH_ON_APB)
-                               val = chipid_readl();
+                               val = tegra_read_chipid();
 
                        clk_writel(PERIPH_CLK_TO_BIT(c),
                                   PERIPH_CLK_TO_RST_SET_REG(c));
index 081a977..ebbc15b 100644 (file)
@@ -29,6 +29,7 @@
 #include <linux/cpufreq.h>
 #include <linux/syscore_ops.h>
 #include <linux/platform_device.h>
+#include <linux/tegra-soc.h>
 
 #include <asm/clkdev.h>
 
@@ -453,7 +454,6 @@ static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
 
-#define MISC_GP_HIDREV                         0x804
 #define MISC_GP_TRANSACTOR_SCRATCH_0           0x864
 #define MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE   (0x1 << 1)
 #define MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE  (0x1 << 2)
@@ -475,8 +475,6 @@ static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
        __raw_writel(value, reg_pmc_base + (reg))
 #define pmc_readl(reg) \
        __raw_readl(reg_pmc_base + (reg))
-#define chipid_readl() \
-       __raw_readl(misc_gp_base + MISC_GP_HIDREV)
 
 #define clk_writel_delay(value, reg)                                   \
        do {                                                            \
@@ -3630,7 +3628,7 @@ static void tegra14_periph_clk_disable(struct clk *c)
                 * flush the write operation in apb bus. This will avoid the
                 * peripheral access after disabling clock*/
                if (c->flags & PERIPH_ON_APB)
-                       val = chipid_readl();
+                       val = tegra_read_chipid();
 
                clk_writel_delay(
                        PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
@@ -3654,7 +3652,7 @@ static void tegra14_periph_clk_reset(struct clk *c, bool assert)
                         * will avoid the peripheral access after disabling
                         * clock */
                        if (c->flags & PERIPH_ON_APB)
-                               val = chipid_readl();
+                               val = tegra_read_chipid();
 
                        clk_writel(PERIPH_CLK_TO_BIT(c),
                                   PERIPH_CLK_TO_RST_SET_REG(c));
index 0a1bcaf..0e0d265 100644 (file)
@@ -94,7 +94,6 @@
 #define SENSOR_CTRL_RST_SHIFT                  1
 #define RST_SRC_MASK                           0x7
 #define RST_SRC_SENSOR                         2
-#define TEGRA_REV_REG_OFFSET                   0x804
 #define CCLK_G_BURST_POLICY_REG_REL_OFFSET     0x368
 #define TSENSOR_SLOWDOWN_BIT                   23