ARM: tegra11: clock: Disable secondary dividers
Alex Frid [Sat, 23 Mar 2013 06:45:02 +0000 (23:45 -0700)]
During clock initialization disabled secondary dividers of disabled
PLLs (just in case if such divider is left enabled by boot-loader).

Change-Id: I69d510213b82c8860f040a786386489ac4dcf720
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/212384
(cherry picked from commit df9c6859ecc98fe4ad3720b82cb3628ec016508d)
Reviewed-on: http://git-master/r/212381
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c

index b0732f8..29ee44c 100644 (file)
@@ -3728,8 +3728,11 @@ static int tegra11_pll_div_clk_set_rate(struct clk *c, unsigned long rate);
 static void tegra11_pll_div_clk_init(struct clk *c)
 {
        if (c->flags & DIV_U71) {
-               u32 divu71;
-               u32 val = clk_readl(c->reg);
+               u32 val, divu71;
+               if (c->parent->state == OFF)
+                       c->ops->disable(c);
+
+               val = clk_readl(c->reg);
                val >>= c->reg_shift;
                c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
                if (!(val & PLL_OUT_RESET_DISABLE))