ARM: tegra: enable split mem config at runtime
Chetan Kumar N G [Thu, 20 Jun 2013 17:32:21 +0000 (10:32 -0700)]
This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: I5dac33e6a3c8d2609fb57580658f05a2612e46df
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/252560
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/board-bonaire.c
arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/include/mach/hardware.h
arch/arm/mach-tegra/iomap.h

index 87bbc16..2ae8986 100644 (file)
@@ -641,11 +641,9 @@ static void __init tegra_bonaire_reserve(void)
 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
        tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M);
 #else
-#if defined(CONFIG_TEGRA_SIMULATION_SPLIT_MEM)
-       if (tegra_split_mem_active())
+       if (tegra_cpu_is_asim() && tegra_split_mem_active())
                tegra_reserve(0, 0, 0);
        else
-#endif
                tegra_reserve(SZ_128M, SZ_16M + SZ_2M, SZ_16M);
 #endif
 }
index a682e84..ab008fc 100644 (file)
@@ -168,9 +168,7 @@ static int pwr_i2c_clk = 400;
 static u8 power_config;
 static u8 display_config;
 
-#ifdef CONFIG_TEGRA_SIMULATION_SPLIT_MEM
 static int tegra_split_mem_set;
-#endif
 
 /*
  * Storage for debug-macro.S's state.
@@ -1883,81 +1881,83 @@ void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
                        tegra_fb_size = fb_size;
        }
 
-#ifdef CONFIG_TEGRA_SIMULATION_SPLIT_MEM
-       if (tegra_split_mem_active()) {
-               tegra_fb_start = TEGRA_ASIM_QT_FB_START;
-               tegra_fb_size = TEGRA_ASIM_QT_FB_SIZE;
-
-               if (tegra_vpr_size == 0) {
-                       tegra_carveout_start =
-                               TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
-                       tegra_carveout_size =
-                               TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_SIZE;
-               } else if (
-                       (tegra_vpr_start <
-                               TEGRA_ASIM_QT_FB_START +
-                               TEGRA_ASIM_QT_FB_SIZE) ||
-                       (tegra_vpr_start + tegra_vpr_size - 1 >
-                               TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
-                               TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE - 1)) {
-                       /*
-                        * On ASIM/ASIM + QT with
-                        * CONFIG_TEGRA_SIMULATION_SPLIT_MEM enabled, the VPR
-                        * region needs to be within the front door memory
-                        * region. Moreover, the VPR region can't exist where
-                        * the framebuffer resides.
-                        */
-                       BUG();
-               } else if (
-                       (tegra_vpr_start -
-                       (TEGRA_ASIM_QT_FB_START +
-                       TEGRA_ASIM_QT_FB_SIZE) <
-                               TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE) &&
-                       (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
-                       TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
-                       (tegra_vpr_start + tegra_vpr_size) <
-                               TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE)) {
-                       /*
-                        * The tegra ASIM/QT carveout has a min size:-
-                        * TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE. All free regions in
-                        * front door mem are smaller than the min carveout
-                        * size. Therefore, we can't fit the carveout in front
-                        * door mem.
-                        */
-                       BUG();
-               } else if (
-                       (tegra_vpr_start -
-                       (TEGRA_ASIM_QT_FB_START + TEGRA_ASIM_QT_FB_SIZE)) >=
-                       (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
-                       TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
-                       (tegra_vpr_start + tegra_vpr_size))) {
-                       /*
-                        * Place the tegra ASIM/QT carveout between the
-                        * framebuffer and VPR.
-                        */
-                       tegra_carveout_start =
-                               TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
-                       tegra_carveout_size = tegra_vpr_start -
-                                               (TEGRA_ASIM_QT_FB_START +
-                                               TEGRA_ASIM_QT_FB_SIZE);
-               } else {
-                       /*
-                        * Place the tegra ASIM/QT carveout after VPR.
-                        */
-                       tegra_carveout_start = tegra_vpr_start + tegra_vpr_size;
-                       tegra_carveout_size =
+       if (tegra_cpu_is_asim()) {
+               if (tegra_split_mem_active()) {
+                       tegra_fb_start = TEGRA_ASIM_QT_FB_START;
+                       tegra_fb_size = TEGRA_ASIM_QT_FB_SIZE;
+
+                       if (tegra_vpr_size == 0) {
+                               tegra_carveout_start =
+                                  TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
+                               tegra_carveout_size =
+                                  TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_SIZE;
+                       } else if (
+                                   (tegra_vpr_start <
+                                    TEGRA_ASIM_QT_FB_START +
+                                    TEGRA_ASIM_QT_FB_SIZE) ||
+                                    (tegra_vpr_start + tegra_vpr_size - 1 >
+                                    TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
+                                    TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE - 1)) {
+                               /*
+                                * On ASIM/ASIM + QT with
+                                * CONFIG_TEGRA_SIMULATION_SPLIT_MEM enabled,
+                                * the VPR region needs to be within the front
+                                * door memory region. Moreover, the VPR region
+                                * can't exist where the framebuffer resides.
+                                */
+                               BUG();
+                       } else if (
+                                       (tegra_vpr_start -
+                                        (TEGRA_ASIM_QT_FB_START +
+                                         TEGRA_ASIM_QT_FB_SIZE) <
+                                        TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE) &&
+                                       (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
+                                        TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
+                                        (tegra_vpr_start + tegra_vpr_size) <
+                                        TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE)) {
+                               /*
+                                * The tegra ASIM/QT carveout has a min size:-
+                                * TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE. All free
+                                * regions in front door mem are smaller than
+                                * the min carveout size. Therefore, we can't
+                                * fit the carveout in front door mem.
+                                */
+                               BUG();
+                       } else if (
+                                       (tegra_vpr_start -
+                                        (TEGRA_ASIM_QT_FB_START +
+                                         TEGRA_ASIM_QT_FB_SIZE)) >=
+                                       (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
+                                        TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
+                                        (tegra_vpr_start + tegra_vpr_size))) {
+                               /*
+                                * Place the tegra ASIM/QT carveout between the
+                                * framebuffer and VPR.
+                                */
+                               tegra_carveout_start =
+                                 TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
+                               tegra_carveout_size = tegra_vpr_start -
+                                       (TEGRA_ASIM_QT_FB_START +
+                                        TEGRA_ASIM_QT_FB_SIZE);
+                       } else {
+                               /*
+                                * Place the tegra ASIM/QT carveout after VPR.
+                                */
+                               tegra_carveout_start = tegra_vpr_start +
+                                                        tegra_vpr_size;
+                               tegra_carveout_size =
                                        TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
                                        TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
                                        (tegra_vpr_start + tegra_vpr_size);
+                       }
+               } else if (tegra_vpr_size != 0) {
+                       /*
+                        * VPR cannot work on ASIM/ASIM + QT if split mem is not
+                        * enabled.
+                        */
+                       BUG();
                }
-       } else if (tegra_vpr_size != 0) {
-               /*
-                * VPR cannot work on ASIM/ASIM + QT if split mem is not
-                * enabled.
-                */
-               BUG();
        }
-#endif
 
        if (tegra_fb_size)
                tegra_grhost_aperture = tegra_fb_start;
@@ -2359,8 +2359,6 @@ static int __init enet_smsc911x_init(void)
 rootfs_initcall(enet_smsc911x_init);
 #endif
 
-#ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
-#ifdef CONFIG_TEGRA_SIMULATION_SPLIT_MEM
 int tegra_split_mem_active(void)
 {
        return tegra_split_mem_set;
@@ -2372,5 +2370,3 @@ static int __init set_tegra_split_mem(char *options)
        return 0;
 }
 early_param("tegra_split_mem", set_tegra_split_mem);
-#endif
-#endif
index 78bdc1e..be2c2da 100644 (file)
@@ -61,9 +61,7 @@ extern enum tegra_revision tegra_revision;
 enum tegra_chipid tegra_get_chipid(void);
 unsigned int tegra_get_minor_rev(void);
 
-#ifdef CONFIG_TEGRA_SIMULATION_SPLIT_MEM
 int tegra_split_mem_active(void);
-#endif
 
 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
 void tegra_get_netlist_revision(u32 *netlist, u32* patchid);
index 74e80a5..a4ab354 100644 (file)
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2011-2013, NVIDIA Corporation.
+ * Copyright (C) 2011-2013, NVIDIA Corporation. All rights reserved.
  *
  * Author:
  *     Colin Cross <ccross@google.com>
@@ -749,7 +749,6 @@ defined(CONFIG_ARCH_TEGRA_12x_SOC))
 #define TEGRA_SIM_ETH_SIZE              SZ_64K
 #endif
 
-#ifdef CONFIG_TEGRA_SIMULATION_SPLIT_MEM
 #define TEGRA_ASIM_QT_FRONT_DOOR_MEM_START     0x81000000
 #define TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE      (SZ_256M - SZ_16M)
 #define TEGRA_ASIM_QT_FB_START         TEGRA_ASIM_QT_FRONT_DOOR_MEM_START
@@ -759,7 +758,6 @@ defined(CONFIG_ARCH_TEGRA_12x_SOC))
 #define TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_SIZE \
                (TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE - TEGRA_ASIM_QT_FB_SIZE)
 #define TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE                SZ_128M
-#endif
 
 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)  || defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
     defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)