ARM: tegra: ardbeg/loki: Fix calibration offsets
Pavan Kunapuli [Tue, 15 Oct 2013 13:35:57 +0000 (18:35 +0530)]
Based on the latest characterization results, calibration offsets should
be set for all modes. Removing the platform data that would selectively
set calibration offsets for some modes.

Bug 1347531

Change-Id: I40e92c6b2f11a7030e0b0cc6fac03ad12767ada7
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/299520
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

arch/arm/mach-tegra/board-ardbeg-sdhci.c
arch/arm/mach-tegra/board-loki-sdhci.c

index 57d299c..c7c6314 100644 (file)
@@ -170,7 +170,6 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
                MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50,
        .calib_3v3_offsets = 0x7676,
        .calib_1v8_offsets = 0x7676,
-       .calib_1v8_offsets_uhs_modes = MMC_1V8_CALIB_OFFSET_DDR50,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
@@ -185,7 +184,6 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
                MMC_UHS_MASK_SDR50,
        .calib_3v3_offsets = 0x7676,
        .calib_1v8_offsets = 0x7676,
-       .calib_1v8_offsets_uhs_modes = MMC_1V8_CALIB_OFFSET_DDR50,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
@@ -204,8 +202,6 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
        .max_clk_limit = 102000000,
        .calib_3v3_offsets = 0x0202,
        .calib_1v8_offsets = 0x0202,
-       .calib_1v8_offsets_uhs_modes = MMC_1V8_CALIB_OFFSET_DDR50 |
-               MMC_1V8_CALIB_OFFSET_HS200,
 };
 
 static struct platform_device tegra_sdhci_device0 = {
index 7de81a8..d93d786 100644 (file)
@@ -152,7 +152,6 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
                MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50,
        .calib_3v3_offsets = 0x7676,
        .calib_1v8_offsets = 0x7676,
-       .calib_1v8_offsets_uhs_modes = MMC_1V8_CALIB_OFFSET_DDR50,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
@@ -167,7 +166,6 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
                MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50,
        .calib_3v3_offsets = 0x7676,
        .calib_1v8_offsets = 0x7676,
-       .calib_1v8_offsets_uhs_modes = MMC_1V8_CALIB_OFFSET_DDR50,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
@@ -187,9 +185,6 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
        .max_clk_limit = 102000000,
        .calib_3v3_offsets = 0x0202,
        .calib_1v8_offsets = 0x0202,
-       .calib_1v8_offsets_uhs_modes = MMC_1V8_CALIB_OFFSET_DDR50 |
-               MMC_1V8_CALIB_OFFSET_HS200,
-
 };
 
 static struct platform_device tegra_sdhci_device0 = {