arm: tegra: Set G-CPU L2 cache latency to 0x442/552.
Krishna Reddy [Thu, 1 Dec 2011 23:32:36 +0000 (15:32 -0800)]
also restore the L2 cache latency values after exit from LP2.
Bug 909628

Change-Id: Ia113d3511255f77ba5f5bfbfafebe43ba247818f
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/67767
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R83fa076e3f91fbca3da82ee180a8b24dc60ec7a0

arch/arm/mach-tegra/board.h
arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/pm.c

index 4931121..0b58f51 100644 (file)
@@ -43,7 +43,7 @@ void __init tegra_dt_init_irq(void);
 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
        unsigned long fb2_size);
 int __init tegra_pcie_init(bool init_port0, bool init_port1);
-void tegra_init_cache();
+void tegra_init_cache(bool init);
 void __init tegra_release_bootloader_fb(void);
 void __init tegra_protected_aperture_init(unsigned long aperture);
 void tegra_move_framebuffer(unsigned long to, unsigned long from,
index c627c9c..aebaa1e 100644 (file)
@@ -139,7 +139,7 @@ static int debug_uart_port_id;
 static enum audio_codec_type audio_codec_name;
 static int max_cpu_current;
 
-void tegra_init_cache(u32 tag_latency, u32 data_latency)
+void tegra_init_cache(bool init)
 {
 #ifdef CONFIG_CACHE_L2X0
        void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
@@ -155,8 +155,8 @@ void tegra_init_cache(u32 tag_latency, u32 data_latency)
                tag_latency = 0x221;
                data_latency = 0x221;
        } else {
-               tag_latency = 0x441;
-               data_latency = 0x551;
+               tag_latency = 0x442;
+               data_latency = 0x552;
        }
 #else
        tag_latency = 0x770;
@@ -173,11 +173,13 @@ void tegra_init_cache(u32 tag_latency, u32 data_latency)
 #endif 
 #endif
 
-       cache_type = readl(p + L2X0_CACHE_TYPE);
-       aux_ctrl = (cache_type & 0x700) << (17-8);
-       aux_ctrl |= 0x7C400001;
+       if (init) {
+               cache_type = readl(p + L2X0_CACHE_TYPE);
+               aux_ctrl = (cache_type & 0x700) << (17-8);
+               aux_ctrl |= 0x7C400001;
 
-       l2x0_init(p, aux_ctrl, 0x8200c3fe);
+               l2x0_init(p, aux_ctrl, 0x8200c3fe);
+       }
 #endif
 }
 
@@ -258,7 +260,7 @@ void __init tegra20_init_early(void)
 #endif
        tegra_apb_io_init();
        tegra_init_fuse();
-       tegra_init_cache();
+       tegra_init_cache(true);
        tegra_powergate_init();
        tegra20_hotplug_init();
        tegra_init_power();
@@ -276,7 +278,7 @@ void __init tegra30_init_early(void)
 #endif
        tegra_apb_io_init();
        tegra_init_fuse();
-       tegra_init_cache();
+       tegra_init_cache(true);
        tegra_pmc_init();
        tegra_powergate_init();
        tegra30_hotplug_init();
index 24d5932..75b16cb 100644 (file)
@@ -570,6 +570,7 @@ unsigned int tegra_idle_lp2_last(unsigned int sleep_time, unsigned int flags)
        tegra_sleep_cpu(PHYS_OFFSET - PAGE_OFFSET);
 
 #ifdef CONFIG_CACHE_L2X0
+       tegra_init_cache(false);
        l2x0_enable();
 #endif
        tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_switch);
@@ -812,7 +813,7 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags)
        else
                tegra_sleep_core(PHYS_OFFSET - PAGE_OFFSET);
 
-       tegra_init_cache();
+       tegra_init_cache(true);
 
        if (mode == TEGRA_SUSPEND_LP0) {
                tegra_cpu_reset_handler_restore();