platform: tegra: Define DDR Tap/trim varibles
Naveen Kumar Arepalli [Thu, 16 Oct 2014 09:20:11 +0000 (14:20 +0530)]
Bug 1563244

Change-Id: Ic4a43df8d11f87b3f62c652109abf540874224c4
Reviewed-on: http://git-master/r/#/c/557255/
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
(cherry picked from commit fd23e040930d735191a4fcc85ba692496aeb8b56)
Reviewed-on: http://git-master/r/737315
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jeetesh Burman <jburman@nvidia.com>
Tested-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

include/linux/platform_data/mmc-sdhci-tegra.h

index fb67cb0..de534ff 100644 (file)
@@ -52,7 +52,10 @@ struct tegra_sdhci_platform_data {
        unsigned int max_clk_limit;
        unsigned int ddr_clk_limit;
        unsigned int tap_delay;
+       bool is_ddr_tap_delay;
+       unsigned int ddr_tap_delay;
        unsigned int trim_delay;
+       bool is_ddr_trim_delay;
        unsigned int ddr_trim_delay;
        unsigned int uhs_mask;
        struct mmc_platform_data mmc_data;