Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
David S. Miller [Fri, 8 May 2009 09:48:30 +0000 (02:48 -0700)]
Conflicts:
include/net/tcp.h

443 files changed:
Documentation/isdn/00-INDEX
Documentation/networking/ip-sysctl.txt
Documentation/networking/mac80211-injection.txt
Documentation/rfkill.txt
MAINTAINERS
arch/arm/mach-pxa/tosa-bt.c
arch/powerpc/platforms/82xx/ep8248e.c
arch/powerpc/platforms/pasemi/gpio_mdio.c
drivers/net/3c509.c
drivers/net/8139too.c
drivers/net/8390.c
drivers/net/8390p.c
drivers/net/Kconfig
drivers/net/Makefile
drivers/net/atl1c/atl1c_main.c
drivers/net/atl1e/atl1e_main.c
drivers/net/atlx/atl1.c
drivers/net/benet/be_main.c
drivers/net/bmac.c
drivers/net/bnx2x.h
drivers/net/bnx2x_fw_file_hdr.h [new file with mode: 0644]
drivers/net/bnx2x_init.h
drivers/net/bnx2x_init_ops.h [new file with mode: 0644]
drivers/net/bnx2x_init_values.h [deleted file]
drivers/net/bnx2x_main.c
drivers/net/bonding/bond_main.c
drivers/net/chelsio/common.h
drivers/net/chelsio/cphy.h
drivers/net/chelsio/cxgb2.c
drivers/net/chelsio/mv88x201x.c
drivers/net/chelsio/my3126.c
drivers/net/chelsio/sge.c
drivers/net/chelsio/subr.c
drivers/net/cpmac.c
drivers/net/cxgb3/adapter.h
drivers/net/cxgb3/ael1002.c
drivers/net/cxgb3/common.h
drivers/net/cxgb3/cxgb3_main.c
drivers/net/cxgb3/sge.c
drivers/net/cxgb3/t3_hw.c
drivers/net/cxgb3/vsc8211.c
drivers/net/depca.c
drivers/net/dm9000.c
drivers/net/e1000/e1000_main.c
drivers/net/e1000e/netdev.c
drivers/net/ehea/ehea_main.c
drivers/net/fec.c
drivers/net/fec.h
drivers/net/fec_mpc52xx.c
drivers/net/fec_mpc52xx_phy.c
drivers/net/forcedeth.c
drivers/net/fs_enet/fs_enet-main.c
drivers/net/fs_enet/fs_enet.h
drivers/net/fs_enet/mac-fec.c
drivers/net/fs_enet/mii-bitbang.c
drivers/net/fs_enet/mii-fec.c
drivers/net/fsl_pq_mdio.c
drivers/net/gianfar.c
drivers/net/gianfar.h
drivers/net/hp100.c
drivers/net/hplance.c
drivers/net/ibmveth.c
drivers/net/igb/e1000_82575.h
drivers/net/igb/e1000_defines.h
drivers/net/igb/e1000_mbx.c
drivers/net/igb/igb.h
drivers/net/igb/igb_ethtool.c
drivers/net/igb/igb_main.c
drivers/net/igbvf/ethtool.c
drivers/net/igbvf/igbvf.h
drivers/net/igbvf/netdev.c
drivers/net/irda/au1k_ir.c
drivers/net/irda/pxaficp_ir.c
drivers/net/irda/sa1100_ir.c
drivers/net/iseries_veth.c
drivers/net/ixgb/ixgb_hw.c
drivers/net/ixgb/ixgb_hw.h
drivers/net/ixgb/ixgb_main.c
drivers/net/ixgb/ixgb_osdep.h
drivers/net/ixgbe/ixgbe.h
drivers/net/ixgbe/ixgbe_82598.c
drivers/net/ixgbe/ixgbe_82599.c
drivers/net/ixgbe/ixgbe_common.c
drivers/net/ixgbe/ixgbe_dcb_nl.c
drivers/net/ixgbe/ixgbe_ethtool.c
drivers/net/ixgbe/ixgbe_main.c
drivers/net/ixgbe/ixgbe_phy.c
drivers/net/ixgbe/ixgbe_phy.h
drivers/net/ixgbe/ixgbe_type.h
drivers/net/ixp2000/ixpdev.c
drivers/net/jazzsonic.c
drivers/net/korina.c
drivers/net/lasi_82596.c
drivers/net/lib82596.c
drivers/net/ll_temac.h [new file with mode: 0644]
drivers/net/ll_temac_main.c [new file with mode: 0644]
drivers/net/ll_temac_mdio.c [new file with mode: 0644]
drivers/net/loopback.c
drivers/net/macb.c
drivers/net/mace.c
drivers/net/macmace.c
drivers/net/macvlan.c
drivers/net/mdio.c [new file with mode: 0644]
drivers/net/meth.c
drivers/net/mii.c
drivers/net/mipsnet.c
drivers/net/mv643xx_eth.c
drivers/net/mvme147.c
drivers/net/myri10ge/myri10ge.c
drivers/net/ne2k-pci.c
drivers/net/ne3210.c
drivers/net/netx-eth.c
drivers/net/netxen/netxen_nic.h
drivers/net/netxen/netxen_nic_ctx.c
drivers/net/netxen/netxen_nic_ethtool.c
drivers/net/netxen/netxen_nic_hdr.h
drivers/net/netxen/netxen_nic_hw.c
drivers/net/netxen/netxen_nic_hw.h
drivers/net/netxen/netxen_nic_init.c
drivers/net/netxen/netxen_nic_main.c
drivers/net/netxen/netxen_nic_niu.c
drivers/net/netxen/netxen_nic_phan_reg.h
drivers/net/pasemi_mac.c
drivers/net/pasemi_mac.h
drivers/net/pci-skeleton.c
drivers/net/pcmcia/3c574_cs.c
drivers/net/pcmcia/3c589_cs.c
drivers/net/pcnet32.c
drivers/net/phy/mdio_bus.c
drivers/net/phy/phy_device.c
drivers/net/pppol2tp.c
drivers/net/r6040.c
drivers/net/r8169.c
drivers/net/rionet.c
drivers/net/s2io-regs.h
drivers/net/s2io.c
drivers/net/sb1250-mac.c
drivers/net/sfc/Kconfig
drivers/net/sfc/boards.c
drivers/net/sfc/efx.c
drivers/net/sfc/ethtool.c
drivers/net/sfc/falcon.c
drivers/net/sfc/falcon_hwdefs.h
drivers/net/sfc/falcon_xmac.c
drivers/net/sfc/mdio_10g.c
drivers/net/sfc/mdio_10g.h
drivers/net/sfc/net_driver.h
drivers/net/sfc/rx.c
drivers/net/sfc/selftest.c
drivers/net/sfc/selftest.h
drivers/net/sfc/sfe4001.c
drivers/net/sfc/tenxpress.c
drivers/net/sfc/xenpack.h
drivers/net/sfc/xfp_phy.c
drivers/net/sgiseeq.c
drivers/net/smc-mca.c
drivers/net/smc911x.c
drivers/net/smsc911x.c
drivers/net/sun3lance.c
drivers/net/tg3.c
drivers/net/tg3.h
drivers/net/tulip/de4x5.c
drivers/net/tulip/winbond-840.c
drivers/net/tun.c
drivers/net/ucc_geth.c
drivers/net/ucc_geth.h
drivers/net/usb/Kconfig
drivers/net/usb/Makefile
drivers/net/usb/cdc_ether.c
drivers/net/usb/hso.c
drivers/net/usb/int51x1.c [new file with mode: 0644]
drivers/net/usb/kaweth.c
drivers/net/usb/usbnet.c
drivers/net/virtio_net.c
drivers/net/vxge/vxge-traffic.c
drivers/net/wan/pc300_drv.c
drivers/net/wireless/Kconfig
drivers/net/wireless/Makefile
drivers/net/wireless/at76c50x-usb.c
drivers/net/wireless/ath/Kconfig [new file with mode: 0644]
drivers/net/wireless/ath/Makefile [new file with mode: 0644]
drivers/net/wireless/ath/ar9170/Kconfig [moved from drivers/net/wireless/ar9170/Kconfig with 96% similarity]
drivers/net/wireless/ath/ar9170/Makefile [moved from drivers/net/wireless/ar9170/Makefile with 100% similarity]
drivers/net/wireless/ath/ar9170/ar9170.h [moved from drivers/net/wireless/ar9170/ar9170.h with 90% similarity]
drivers/net/wireless/ath/ar9170/cmd.c [moved from drivers/net/wireless/ar9170/cmd.c with 100% similarity]
drivers/net/wireless/ath/ar9170/cmd.h [moved from drivers/net/wireless/ar9170/cmd.h with 100% similarity]
drivers/net/wireless/ath/ar9170/eeprom.h [moved from drivers/net/wireless/ar9170/eeprom.h with 100% similarity]
drivers/net/wireless/ath/ar9170/hw.h [moved from drivers/net/wireless/ar9170/hw.h with 97% similarity]
drivers/net/wireless/ath/ar9170/led.c [moved from drivers/net/wireless/ar9170/led.c with 100% similarity]
drivers/net/wireless/ath/ar9170/mac.c [moved from drivers/net/wireless/ar9170/mac.c with 100% similarity]
drivers/net/wireless/ath/ar9170/main.c [moved from drivers/net/wireless/ar9170/main.c with 77% similarity]
drivers/net/wireless/ath/ar9170/phy.c [moved from drivers/net/wireless/ar9170/phy.c with 100% similarity]
drivers/net/wireless/ath/ar9170/usb.c [moved from drivers/net/wireless/ar9170/usb.c with 100% similarity]
drivers/net/wireless/ath/ar9170/usb.h [moved from drivers/net/wireless/ar9170/usb.h with 98% similarity]
drivers/net/wireless/ath/ath5k/Kconfig [moved from drivers/net/wireless/ath5k/Kconfig with 98% similarity]
drivers/net/wireless/ath/ath5k/Makefile [moved from drivers/net/wireless/ath5k/Makefile with 100% similarity]
drivers/net/wireless/ath/ath5k/ath5k.h [moved from drivers/net/wireless/ath5k/ath5k.h with 99% similarity]
drivers/net/wireless/ath/ath5k/attach.c [moved from drivers/net/wireless/ath5k/attach.c with 100% similarity]
drivers/net/wireless/ath/ath5k/base.c [moved from drivers/net/wireless/ath5k/base.c with 98% similarity]
drivers/net/wireless/ath/ath5k/base.h [moved from drivers/net/wireless/ath5k/base.h with 99% similarity]
drivers/net/wireless/ath/ath5k/caps.c [moved from drivers/net/wireless/ath5k/caps.c with 100% similarity]
drivers/net/wireless/ath/ath5k/debug.c [moved from drivers/net/wireless/ath5k/debug.c with 100% similarity]
drivers/net/wireless/ath/ath5k/debug.h [moved from drivers/net/wireless/ath5k/debug.h with 100% similarity]
drivers/net/wireless/ath/ath5k/desc.c [moved from drivers/net/wireless/ath5k/desc.c with 100% similarity]
drivers/net/wireless/ath/ath5k/desc.h [moved from drivers/net/wireless/ath5k/desc.h with 100% similarity]
drivers/net/wireless/ath/ath5k/dma.c [moved from drivers/net/wireless/ath5k/dma.c with 99% similarity]
drivers/net/wireless/ath/ath5k/eeprom.c [moved from drivers/net/wireless/ath5k/eeprom.c with 100% similarity]
drivers/net/wireless/ath/ath5k/eeprom.h [moved from drivers/net/wireless/ath5k/eeprom.h with 100% similarity]
drivers/net/wireless/ath/ath5k/gpio.c [moved from drivers/net/wireless/ath5k/gpio.c with 100% similarity]
drivers/net/wireless/ath/ath5k/initvals.c [moved from drivers/net/wireless/ath5k/initvals.c with 99% similarity]
drivers/net/wireless/ath/ath5k/led.c [moved from drivers/net/wireless/ath5k/led.c with 97% similarity]
drivers/net/wireless/ath/ath5k/pcu.c [moved from drivers/net/wireless/ath5k/pcu.c with 100% similarity]
drivers/net/wireless/ath/ath5k/phy.c [moved from drivers/net/wireless/ath5k/phy.c with 99% similarity]
drivers/net/wireless/ath/ath5k/qcu.c [moved from drivers/net/wireless/ath5k/qcu.c with 100% similarity]
drivers/net/wireless/ath/ath5k/reg.h [moved from drivers/net/wireless/ath5k/reg.h with 100% similarity]
drivers/net/wireless/ath/ath5k/reset.c [moved from drivers/net/wireless/ath5k/reset.c with 99% similarity]
drivers/net/wireless/ath/ath5k/rfbuffer.h [moved from drivers/net/wireless/ath5k/rfbuffer.h with 100% similarity]
drivers/net/wireless/ath/ath5k/rfgain.h [moved from drivers/net/wireless/ath5k/rfgain.h with 100% similarity]
drivers/net/wireless/ath/ath9k/Kconfig [moved from drivers/net/wireless/ath9k/Kconfig with 97% similarity]
drivers/net/wireless/ath/ath9k/Makefile [moved from drivers/net/wireless/ath9k/Makefile with 96% similarity]
drivers/net/wireless/ath/ath9k/ahb.c [moved from drivers/net/wireless/ath9k/ahb.c with 100% similarity]
drivers/net/wireless/ath/ath9k/ani.c [moved from drivers/net/wireless/ath9k/ani.c with 99% similarity]
drivers/net/wireless/ath/ath9k/ani.h [moved from drivers/net/wireless/ath9k/ani.h with 100% similarity]
drivers/net/wireless/ath/ath9k/ath9k.h [moved from drivers/net/wireless/ath9k/ath9k.h with 94% similarity]
drivers/net/wireless/ath/ath9k/beacon.c [moved from drivers/net/wireless/ath9k/beacon.c with 98% similarity]
drivers/net/wireless/ath/ath9k/calib.c [moved from drivers/net/wireless/ath9k/calib.c with 90% similarity]
drivers/net/wireless/ath/ath9k/calib.h [moved from drivers/net/wireless/ath9k/calib.h with 81% similarity]
drivers/net/wireless/ath/ath9k/debug.c [moved from drivers/net/wireless/ath9k/debug.c with 99% similarity]
drivers/net/wireless/ath/ath9k/debug.h [moved from drivers/net/wireless/ath9k/debug.h with 89% similarity]
drivers/net/wireless/ath/ath9k/eeprom.c [moved from drivers/net/wireless/ath9k/eeprom.c with 99% similarity]
drivers/net/wireless/ath/ath9k/eeprom.h [moved from drivers/net/wireless/ath9k/eeprom.h with 99% similarity]
drivers/net/wireless/ath/ath9k/hw.c [moved from drivers/net/wireless/ath9k/hw.c with 96% similarity]
drivers/net/wireless/ath/ath9k/hw.h [moved from drivers/net/wireless/ath9k/hw.h with 87% similarity]
drivers/net/wireless/ath/ath9k/initvals.h [moved from drivers/net/wireless/ath9k/initvals.h with 100% similarity]
drivers/net/wireless/ath/ath9k/mac.c [moved from drivers/net/wireless/ath9k/mac.c with 93% similarity]
drivers/net/wireless/ath/ath9k/mac.h [moved from drivers/net/wireless/ath9k/mac.h with 100% similarity]
drivers/net/wireless/ath/ath9k/main.c [moved from drivers/net/wireless/ath9k/main.c with 91% similarity]
drivers/net/wireless/ath/ath9k/pci.c [moved from drivers/net/wireless/ath9k/pci.c with 100% similarity]
drivers/net/wireless/ath/ath9k/phy.c [moved from drivers/net/wireless/ath9k/phy.c with 99% similarity]
drivers/net/wireless/ath/ath9k/phy.h [moved from drivers/net/wireless/ath9k/phy.h with 99% similarity]
drivers/net/wireless/ath/ath9k/rc.c [moved from drivers/net/wireless/ath9k/rc.c with 98% similarity]
drivers/net/wireless/ath/ath9k/rc.h [moved from drivers/net/wireless/ath9k/rc.h with 98% similarity]
drivers/net/wireless/ath/ath9k/recv.c [moved from drivers/net/wireless/ath9k/recv.c with 93% similarity]
drivers/net/wireless/ath/ath9k/reg.h [moved from drivers/net/wireless/ath9k/reg.h with 100% similarity]
drivers/net/wireless/ath/ath9k/virtual.c [moved from drivers/net/wireless/ath9k/virtual.c with 100% similarity]
drivers/net/wireless/ath/ath9k/xmit.c [moved from drivers/net/wireless/ath9k/xmit.c with 98% similarity]
drivers/net/wireless/ath/main.c [new file with mode: 0644]
drivers/net/wireless/ath/regd.c [moved from drivers/net/wireless/ath9k/regd.c with 65% similarity]
drivers/net/wireless/ath/regd.h [moved from drivers/net/wireless/ath9k/regd.h with 85% similarity]
drivers/net/wireless/ath/regd_common.h [moved from drivers/net/wireless/ath9k/regd_common.h with 100% similarity]
drivers/net/wireless/b43/Kconfig
drivers/net/wireless/b43/b43.h
drivers/net/wireless/b43/main.c
drivers/net/wireless/b43/rfkill.c
drivers/net/wireless/b43legacy/Kconfig
drivers/net/wireless/b43legacy/b43legacy.h
drivers/net/wireless/b43legacy/main.c
drivers/net/wireless/b43legacy/rfkill.c
drivers/net/wireless/b43legacy/xmit.c
drivers/net/wireless/b43legacy/xmit.h
drivers/net/wireless/hostap/hostap_plx.c
drivers/net/wireless/ipw2x00/ipw2200.c
drivers/net/wireless/ipw2x00/libipw_module.c
drivers/net/wireless/iwlwifi/iwl-3945-rs.c
drivers/net/wireless/iwlwifi/iwl-3945.c
drivers/net/wireless/iwlwifi/iwl-3945.h
drivers/net/wireless/iwlwifi/iwl-4965.c
drivers/net/wireless/iwlwifi/iwl-5000.c
drivers/net/wireless/iwlwifi/iwl-6000.c
drivers/net/wireless/iwlwifi/iwl-agn-rs.c
drivers/net/wireless/iwlwifi/iwl-agn-rs.h
drivers/net/wireless/iwlwifi/iwl-agn.c
drivers/net/wireless/iwlwifi/iwl-commands.h
drivers/net/wireless/iwlwifi/iwl-core.c
drivers/net/wireless/iwlwifi/iwl-core.h
drivers/net/wireless/iwlwifi/iwl-debug.h
drivers/net/wireless/iwlwifi/iwl-debugfs.c
drivers/net/wireless/iwlwifi/iwl-dev.h
drivers/net/wireless/iwlwifi/iwl-rfkill.c
drivers/net/wireless/iwlwifi/iwl-rx.c
drivers/net/wireless/iwlwifi/iwl-scan.c
drivers/net/wireless/iwlwifi/iwl-sta.c
drivers/net/wireless/iwlwifi/iwl-tx.c
drivers/net/wireless/iwlwifi/iwl3945-base.c
drivers/net/wireless/libertas/cmd.c
drivers/net/wireless/libertas/defs.h
drivers/net/wireless/libertas/dev.h
drivers/net/wireless/libertas/host.h
drivers/net/wireless/libertas/hostcmd.h
drivers/net/wireless/libertas/if_cs.c
drivers/net/wireless/libertas/if_sdio.c
drivers/net/wireless/libertas/if_sdio.h
drivers/net/wireless/libertas/if_spi.c
drivers/net/wireless/libertas/if_usb.c
drivers/net/wireless/libertas/main.c
drivers/net/wireless/libertas/rx.c
drivers/net/wireless/libertas/tx.c
drivers/net/wireless/libertas/types.h
drivers/net/wireless/libertas_tf/if_usb.c
drivers/net/wireless/p54/p54.h
drivers/net/wireless/p54/p54common.c
drivers/net/wireless/p54/p54spi.c
drivers/net/wireless/rndis_wlan.c
drivers/net/wireless/rt2x00/rt2400pci.c
drivers/net/wireless/rt2x00/rt2500pci.c
drivers/net/wireless/rt2x00/rt2x00.h
drivers/net/wireless/rt2x00/rt2x00link.c
drivers/net/wireless/rt2x00/rt2x00pci.c
drivers/net/wireless/rt2x00/rt61pci.c
drivers/net/wireless/rt2x00/rt61pci.h
drivers/net/wireless/rtl818x/Makefile
drivers/net/wireless/rtl818x/rtl8187.h
drivers/net/wireless/rtl818x/rtl8187_dev.c
drivers/net/wireless/rtl818x/rtl8187_leds.c [new file with mode: 0644]
drivers/net/wireless/rtl818x/rtl8187_leds.h [new file with mode: 0644]
drivers/of/Kconfig
drivers/of/Makefile
drivers/of/base.c
drivers/of/of_mdio.c [new file with mode: 0644]
drivers/pci/quirks.c
drivers/platform/x86/acer-wmi.c
drivers/platform/x86/hp-wmi.c
drivers/platform/x86/sony-laptop.c
drivers/platform/x86/toshiba_acpi.c
drivers/serial/serial_cs.c
drivers/usb/atm/cxacru.c
firmware/Makefile
firmware/WHENCE
firmware/bnx2x-e1-4.8.53.0.fw.ihex [new file with mode: 0644]
firmware/bnx2x-e1h-4.8.53.0.fw.ihex [new file with mode: 0644]
firmware/cis/3CCFEM556.cis.ihex [new file with mode: 0644]
firmware/cis/3CXEM556.cis.ihex [new file with mode: 0644]
include/linux/etherdevice.h
include/linux/ethtool.h
include/linux/fs_enet_pd.h
include/linux/ieee80211.h
include/linux/if_tun.h
include/linux/if_vlan.h
include/linux/mdio.h [new file with mode: 0644]
include/linux/mii.h
include/linux/mmc/sdio_ids.h
include/linux/netdevice.h
include/linux/nl80211.h
include/linux/of.h
include/linux/of_mdio.h [new file with mode: 0644]
include/linux/pci_ids.h
include/linux/phy.h
include/linux/rfkill.h
include/linux/skbuff.h
include/linux/smsc911x.h
include/linux/snmp.h
include/linux/socket.h
include/linux/tcp.h
include/linux/usb/usbnet.h
include/net/cfg80211.h
include/net/ip.h
include/net/ip_fib.h
include/net/ipv6.h
include/net/iucv/af_iucv.h
include/net/mac80211.h
include/net/regulatory.h [new file with mode: 0644]
include/net/snmp.h
include/net/tcp.h
include/net/wireless.h [deleted file]
net/8021q/vlan_core.c
net/8021q/vlan_dev.c
net/core/datagram.c
net/core/dev.c
net/core/drop_monitor.c
net/core/iovec.c
net/core/net_namespace.c
net/ipv4/af_inet.c
net/ipv4/inet_diag.c
net/ipv4/inet_timewait_sock.c
net/ipv4/ip_input.c
net/ipv4/ip_output.c
net/ipv4/proc.c
net/ipv4/syncookies.c
net/ipv4/tcp_input.c
net/ipv4/tcp_ipv4.c
net/ipv4/tcp_output.c
net/ipv6/ip6_input.c
net/ipv6/ip6_output.c
net/ipv6/mcast.c
net/ipv6/ndisc.c
net/ipv6/proc.c
net/ipv6/raw.c
net/ipv6/syncookies.c
net/ipv6/tcp_ipv6.c
net/iucv/af_iucv.c
net/iucv/iucv.c
net/mac80211/Kconfig
net/mac80211/cfg.c
net/mac80211/debugfs.c
net/mac80211/event.c
net/mac80211/ht.c
net/mac80211/ibss.c
net/mac80211/ieee80211_i.h
net/mac80211/iface.c
net/mac80211/main.c
net/mac80211/mlme.c
net/mac80211/pm.c
net/mac80211/rx.c
net/mac80211/scan.c
net/mac80211/spectmgmt.c
net/mac80211/sta_info.c
net/mac80211/sta_info.h
net/mac80211/tx.c
net/mac80211/util.c
net/mac80211/wext.c
net/mac80211/wpa.c
net/rds/af_rds.c
net/rds/connection.c
net/rds/ib.c
net/rds/ib.h
net/rds/ib_recv.c
net/rds/ib_ring.c
net/rds/ib_send.c
net/rds/info.c
net/rds/iw.c
net/rds/iw.h
net/rds/iw_recv.c
net/rds/iw_ring.c
net/rds/iw_send.c
net/rds/rdma.c
net/rds/rdma_transport.c
net/rds/rds.h
net/rds/send.c
net/rfkill/rfkill-input.c
net/rfkill/rfkill.c
net/sctp/output.c
net/wimax/op-rfkill.c
net/wireless/Makefile
net/wireless/core.c
net/wireless/core.h
net/wireless/ibss.c [new file with mode: 0644]
net/wireless/mlme.c
net/wireless/nl80211.c
net/wireless/nl80211.h
net/wireless/reg.c
net/wireless/scan.c
net/wireless/util.c
net/wireless/wext-compat.c

index 5a2d699..f6010a5 100644 (file)
@@ -22,16 +22,11 @@ README.gigaset
        - info on the drivers for Siemens Gigaset ISDN adapters.
 README.icn
        - info on the ICN-ISDN-card and its driver.
+>>>>>>> 93af7aca44f0e82e67bda10a0fb73d383edcc8bd:Documentation/isdn/00-INDEX
 README.HiSax
        - info on the HiSax driver which replaces the old teles.
-README.hfc-pci
-       - info on hfc-pci based cards.
-README.pcbit
-       - info on the PCBIT-D ISDN adapter and driver.
-README.syncppp
-       - info on running Sync PPP over ISDN.
-syncPPP.FAQ
-       - frequently asked questions about running PPP over ISDN.
+README.audio
+       - info for running audio over ISDN.
 README.avmb1
        - info on driver for AVM-B1 ISDN card.
 README.act2000
@@ -42,10 +37,28 @@ README.concap
        - info on "CONCAP" encapsulation protocol interface used for X.25.
 README.diversion
        - info on module for isdn diversion services.
+README.fax
+       - info for using Fax over ISDN.
+README.gigaset
+       - info on the drivers for Siemens Gigaset ISDN adapters
+README.hfc-pci
+       - info on hfc-pci based cards.
+README.hysdn
+        - info on driver for Hypercope active HYSDN cards
+README.icn
+       - info on the ICN-ISDN-card and its driver.
+README.mISDN
+       - info on the Modular ISDN subsystem (mISDN)
+README.pcbit
+       - info on the PCBIT-D ISDN adapter and driver.
 README.sc
        - info on driver for Spellcaster cards.
+README.syncppp
+       - info on running Sync PPP over ISDN.
 README.x25
        - info for running X.25 over ISDN.
+syncPPP.FAQ
+       - frequently asked questions about running PPP over ISDN.
 README.hysdn
        - info on driver for Hypercope active HYSDN cards
 README.mISDN
index ec5de02..7f98aa3 100644 (file)
@@ -168,7 +168,16 @@ tcp_dsack - BOOLEAN
        Allows TCP to send "duplicate" SACKs.
 
 tcp_ecn - BOOLEAN
-       Enable Explicit Congestion Notification in TCP.
+       Enable Explicit Congestion Notification (ECN) in TCP. ECN is only
+       used when both ends of the TCP flow support it. It is useful to
+       avoid losses due to congestion (when the bottleneck router supports
+       ECN).
+       Possible values are:
+               0 disable ECN
+               1 ECN enabled
+               2 Only server-side ECN enabled. If the other end does
+                 not support ECN, behavior is like with ECN disabled.
+       Default: 2
 
 tcp_fack - BOOLEAN
        Enable FACK congestion avoidance and fast retransmission.
index 84906ef..b30e81a 100644 (file)
@@ -12,38 +12,22 @@ following format:
 The radiotap format is discussed in
 ./Documentation/networking/radiotap-headers.txt.
 
-Despite 13 radiotap argument types are currently defined, most only make sense
+Despite many radiotap parameters being currently defined, most only make sense
 to appear on received packets.  The following information is parsed from the
 radiotap headers and used to control injection:
 
- * IEEE80211_RADIOTAP_RATE
-
-   rate in 500kbps units, automatic if invalid or not present
-
-
- * IEEE80211_RADIOTAP_ANTENNA
-
-   antenna to use, automatic if not present
-
-
- * IEEE80211_RADIOTAP_DBM_TX_POWER
-
-   transmit power in dBm, automatic if not present
-
-
  * IEEE80211_RADIOTAP_FLAGS
 
    IEEE80211_RADIOTAP_F_FCS: FCS will be removed and recalculated
    IEEE80211_RADIOTAP_F_WEP: frame will be encrypted if key available
    IEEE80211_RADIOTAP_F_FRAG: frame will be fragmented if longer than the
-                             current fragmentation threshold. Note that
-                             this flag is only reliable when software
-                             fragmentation is enabled)
+                             current fragmentation threshold.
+
 
 The injection code can also skip all other currently defined radiotap fields
 facilitating replay of captured radiotap headers directly.
 
-Here is an example valid radiotap header defining these three parameters
+Here is an example valid radiotap header defining some parameters
 
        0x00, 0x00, // <-- radiotap version
        0x0b, 0x00, // <- radiotap header length
@@ -72,8 +56,8 @@ interface), along the following lines:
 ...
        r = pcap_inject(ppcap, u8aSendBuffer, nLength);
 
-You can also find sources for a complete inject test applet here:
+You can also find a link to a complete inject application here:
 
-http://penumbra.warmcat.com/_twk/tiki-index.php?page=packetspammer
+http://wireless.kernel.org/en/users/Documentation/packetspammer
 
 Andy Green <andy@warmcat.com>
index 4d3ee31..40c3a3f 100644 (file)
@@ -521,16 +521,12 @@ status of the system.
 Input devices may issue events that are related to rfkill.  These are the
 various KEY_* events and SW_* events supported by rfkill-input.c.
 
-******IMPORTANT******
-When rfkill-input is ACTIVE, userspace is NOT TO CHANGE THE STATE OF AN RFKILL
-SWITCH IN RESPONSE TO AN INPUT EVENT also handled by rfkill-input, unless it
-has set to true the user_claim attribute for that particular switch.  This rule
-is *absolute*; do NOT violate it.
-******IMPORTANT******
-
-Userspace must not assume it is the only source of control for rfkill switches.
-Their state CAN and WILL change due to firmware actions, direct user actions,
-and the rfkill-input EPO override for *_RFKILL_ALL.
+Userspace may not change the state of an rfkill switch in response to an
+input event, it should refrain from changing states entirely.
+
+Userspace cannot assume it is the only source of control for rfkill switches.
+Their state can change due to firmware actions, direct user actions, and the
+rfkill-input EPO override for *_RFKILL_ALL.
 
 When rfkill-input is not active, userspace must initiate a rfkill status
 change by writing to the "state" attribute in order for anything to happen.
index 36ea627..3dfe1a7 100644 (file)
@@ -888,6 +888,12 @@ P: Luis R. Rodriguez
 M:     lrodriguez@atheros.com
 P:     Jouni Malinen
 M:     jmalinen@atheros.com
+P:     Sujith Manoharan
+M:     Sujith.Manoharan@atheros.com
+P:     Vasanthakumar Thiagarajan
+M:     vasanth@atheros.com
+P:     Senthil Balasubramanian
+M:     senthilkumar@atheros.com
 L:     linux-wireless@vger.kernel.org
 L:     ath9k-devel@lists.ath9k.org
 S:     Supported
@@ -4421,8 +4427,8 @@ S:        Maintained
 F:     drivers/ata/sata_promise.*
 
 PS3 NETWORK SUPPORT
-P:     Masakazu Mokuno
-M:     mokuno@sm.sony.co.jp
+P:     Geoff Levand
+M:     geoffrey.levand@am.sony.com
 L:     netdev@vger.kernel.org
 L:     cbe-oss-dev@ozlabs.org
 S:     Supported
@@ -4607,7 +4613,7 @@ F:        drivers/net/r6040.c
 RDS - RELIABLE DATAGRAM SOCKETS
 P:     Andy Grover
 M:     andy.grover@oracle.com
-L:     rds-devel@oss.oracle.com
+L:     rds-devel@oss.oracle.com (moderated for non-subscribers)
 S:     Supported
 F:     net/rds/
 
index fb0294b..bde42aa 100644 (file)
@@ -38,9 +38,9 @@ static void tosa_bt_off(struct tosa_bt_data *data)
 static int tosa_bt_toggle_radio(void *data, enum rfkill_state state)
 {
        pr_info("BT_RADIO going: %s\n",
-                       state == RFKILL_STATE_ON ? "on" : "off");
+                       state == RFKILL_STATE_UNBLOCKED ? "on" : "off");
 
-       if (state == RFKILL_STATE_ON) {
+       if (state == RFKILL_STATE_UNBLOCKED) {
                pr_info("TOSA_BT: going ON\n");
                tosa_bt_on(data);
        } else {
index 0eb6d7f..51fcae4 100644 (file)
@@ -14,6 +14,7 @@
 #include <linux/interrupt.h>
 #include <linux/fsl_devices.h>
 #include <linux/mdio-bitbang.h>
+#include <linux/of_mdio.h>
 #include <linux/of_platform.h>
 
 #include <asm/io.h>
@@ -115,7 +116,7 @@ static int __devinit ep8248e_mdio_probe(struct of_device *ofdev,
        struct mii_bus *bus;
        struct resource res;
        struct device_node *node;
-       int ret, i;
+       int ret;
 
        node = of_get_parent(ofdev->node);
        of_node_put(node);
@@ -130,17 +131,13 @@ static int __devinit ep8248e_mdio_probe(struct of_device *ofdev,
        if (!bus)
                return -ENOMEM;
 
-       bus->phy_mask = 0;
        bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
 
-       for (i = 0; i < PHY_MAX_ADDR; i++)
-               bus->irq[i] = -1;
-
        bus->name = "ep8248e-mdio-bitbang";
        bus->parent = &ofdev->dev;
        snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
 
-       return mdiobus_register(bus);
+       return of_mdiobus_register(bus, ofdev->node);
 }
 
 static int ep8248e_mdio_remove(struct of_device *ofdev)
index 75cc165..3bf5467 100644 (file)
@@ -29,7 +29,7 @@
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
 #include <linux/phy.h>
-#include <linux/platform_device.h>
+#include <linux/of_mdio.h>
 #include <linux/of_platform.h>
 
 #define DELAY 1
@@ -39,6 +39,7 @@ static void __iomem *gpio_regs;
 struct gpio_priv {
        int mdc_pin;
        int mdio_pin;
+       int mdio_irqs[PHY_MAX_ADDR];
 };
 
 #define MDC_PIN(bus)   (((struct gpio_priv *)bus->priv)->mdc_pin)
@@ -218,12 +219,11 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev,
                                     const struct of_device_id *match)
 {
        struct device *dev = &ofdev->dev;
-       struct device_node *phy_dn, *np = ofdev->node;
+       struct device_node *np = ofdev->node;
        struct mii_bus *new_bus;
        struct gpio_priv *priv;
        const unsigned int *prop;
        int err;
-       int i;
 
        err = -ENOMEM;
        priv = kzalloc(sizeof(struct gpio_priv), GFP_KERNEL);
@@ -244,27 +244,7 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev,
        snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", *prop);
        new_bus->priv = priv;
 
-       new_bus->phy_mask = 0;
-
-       new_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
-
-       if (!new_bus->irq)
-               goto out_free_bus;
-
-       for (i = 0; i < PHY_MAX_ADDR; i++)
-               new_bus->irq[i] = NO_IRQ;
-
-       for (phy_dn = of_get_next_child(np, NULL);
-            phy_dn != NULL;
-            phy_dn = of_get_next_child(np, phy_dn)) {
-               const unsigned int *ip, *regp;
-
-               ip = of_get_property(phy_dn, "interrupts", NULL);
-               regp = of_get_property(phy_dn, "reg", NULL);
-               if (!ip || !regp || *regp >= PHY_MAX_ADDR)
-                       continue;
-               new_bus->irq[*regp] = irq_create_mapping(NULL, *ip);
-       }
+       new_bus->irq = priv->mdio_irqs;
 
        prop = of_get_property(np, "mdc-pin", NULL);
        priv->mdc_pin = *prop;
@@ -275,7 +255,7 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev,
        new_bus->parent = dev;
        dev_set_drvdata(dev, new_bus);
 
-       err = mdiobus_register(new_bus);
+       err = of_mdiobus_register(new_bus, np);
 
        if (err != 0) {
                printk(KERN_ERR "%s: Cannot register as MDIO bus, err %d\n",
@@ -286,8 +266,6 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev,
        return 0;
 
 out_free_irq:
-       kfree(new_bus->irq);
-out_free_bus:
        kfree(new_bus);
 out_free_priv:
        kfree(priv);
index fbb3719..393e4e7 100644 (file)
@@ -653,11 +653,11 @@ static int __init el3_mca_probe(struct device *device)
        netdev_boot_setup_check(dev);
 
        el3_dev_fill(dev, phys_addr, ioaddr, irq, if_port, EL3_MCA);
-       device->driver_data = dev;
+       dev_set_drvdata(device, dev);
        err = el3_common_init(dev);
 
        if (err) {
-               device->driver_data = NULL;
+               dev_set_drvdata(device, NULL);
                free_netdev(dev);
                return -ENOMEM;
        }
@@ -721,12 +721,12 @@ static int __init el3_eisa_probe (struct device *device)
 
 /* This remove works for all device types.
  *
- * The net dev must be stored in the driver_data field */
+ * The net dev must be stored in the driver data field */
 static int __devexit el3_device_remove (struct device *device)
 {
        struct net_device *dev;
 
-       dev  = device->driver_data;
+       dev = dev_get_drvdata(device);
 
        el3_common_remove (dev);
        return 0;
@@ -1451,7 +1451,7 @@ el3_suspend(struct device *pdev, pm_message_t state)
        struct el3_private *lp;
        int ioaddr;
 
-       dev = pdev->driver_data;
+       dev = dev_get_drvdata(pdev);
        lp = netdev_priv(dev);
        ioaddr = dev->base_addr;
 
@@ -1475,7 +1475,7 @@ el3_resume(struct device *pdev)
        struct el3_private *lp;
        int ioaddr;
 
-       dev = pdev->driver_data;
+       dev = dev_get_drvdata(pdev);
        lp = netdev_priv(dev);
        ioaddr = dev->base_addr;
 
index 1fc4543..d901775 100644 (file)
@@ -2292,11 +2292,11 @@ static int rtl8139_close (struct net_device *dev)
    other threads or interrupts aren't messing with the 8139.  */
 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 {
-       struct rtl8139_private *np = netdev_priv(dev);
-       void __iomem *ioaddr = np->mmio_addr;
+       struct rtl8139_private *tp = netdev_priv(dev);
+       void __iomem *ioaddr = tp->mmio_addr;
 
-       spin_lock_irq(&np->lock);
-       if (rtl_chip_info[np->chipset].flags & HasLWake) {
+       spin_lock_irq(&tp->lock);
+       if (rtl_chip_info[tp->chipset].flags & HasLWake) {
                u8 cfg3 = RTL_R8 (Config3);
                u8 cfg5 = RTL_R8 (Config5);
 
@@ -2317,7 +2317,7 @@ static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
                if (cfg5 & Cfg5_BWF)
                        wol->wolopts |= WAKE_BCAST;
        }
-       spin_unlock_irq(&np->lock);
+       spin_unlock_irq(&tp->lock);
 }
 
 
@@ -2326,19 +2326,19 @@ static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
    aren't messing with the 8139.  */
 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 {
-       struct rtl8139_private *np = netdev_priv(dev);
-       void __iomem *ioaddr = np->mmio_addr;
+       struct rtl8139_private *tp = netdev_priv(dev);
+       void __iomem *ioaddr = tp->mmio_addr;
        u32 support;
        u8 cfg3, cfg5;
 
-       support = ((rtl_chip_info[np->chipset].flags & HasLWake)
+       support = ((rtl_chip_info[tp->chipset].flags & HasLWake)
                   ? (WAKE_PHY | WAKE_MAGIC
                      | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
                   : 0);
        if (wol->wolopts & ~support)
                return -EINVAL;
 
-       spin_lock_irq(&np->lock);
+       spin_lock_irq(&tp->lock);
        cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
        if (wol->wolopts & WAKE_PHY)
                cfg3 |= Cfg3_LinkUp;
@@ -2359,87 +2359,87 @@ static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
        if (wol->wolopts & WAKE_BCAST)
                cfg5 |= Cfg5_BWF;
        RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
-       spin_unlock_irq(&np->lock);
+       spin_unlock_irq(&tp->lock);
 
        return 0;
 }
 
 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
 {
-       struct rtl8139_private *np = netdev_priv(dev);
+       struct rtl8139_private *tp = netdev_priv(dev);
        strcpy(info->driver, DRV_NAME);
        strcpy(info->version, DRV_VERSION);
-       strcpy(info->bus_info, pci_name(np->pci_dev));
-       info->regdump_len = np->regs_len;
+       strcpy(info->bus_info, pci_name(tp->pci_dev));
+       info->regdump_len = tp->regs_len;
 }
 
 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
-       struct rtl8139_private *np = netdev_priv(dev);
-       spin_lock_irq(&np->lock);
-       mii_ethtool_gset(&np->mii, cmd);
-       spin_unlock_irq(&np->lock);
+       struct rtl8139_private *tp = netdev_priv(dev);
+       spin_lock_irq(&tp->lock);
+       mii_ethtool_gset(&tp->mii, cmd);
+       spin_unlock_irq(&tp->lock);
        return 0;
 }
 
 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
-       struct rtl8139_private *np = netdev_priv(dev);
+       struct rtl8139_private *tp = netdev_priv(dev);
        int rc;
-       spin_lock_irq(&np->lock);
-       rc = mii_ethtool_sset(&np->mii, cmd);
-       spin_unlock_irq(&np->lock);
+       spin_lock_irq(&tp->lock);
+       rc = mii_ethtool_sset(&tp->mii, cmd);
+       spin_unlock_irq(&tp->lock);
        return rc;
 }
 
 static int rtl8139_nway_reset(struct net_device *dev)
 {
-       struct rtl8139_private *np = netdev_priv(dev);
-       return mii_nway_restart(&np->mii);
+       struct rtl8139_private *tp = netdev_priv(dev);
+       return mii_nway_restart(&tp->mii);
 }
 
 static u32 rtl8139_get_link(struct net_device *dev)
 {
-       struct rtl8139_private *np = netdev_priv(dev);
-       return mii_link_ok(&np->mii);
+       struct rtl8139_private *tp = netdev_priv(dev);
+       return mii_link_ok(&tp->mii);
 }
 
 static u32 rtl8139_get_msglevel(struct net_device *dev)
 {
-       struct rtl8139_private *np = netdev_priv(dev);
-       return np->msg_enable;
+       struct rtl8139_private *tp = netdev_priv(dev);
+       return tp->msg_enable;
 }
 
 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
 {
-       struct rtl8139_private *np = netdev_priv(dev);
-       np->msg_enable = datum;
+       struct rtl8139_private *tp = netdev_priv(dev);
+       tp->msg_enable = datum;
 }
 
 static int rtl8139_get_regs_len(struct net_device *dev)
 {
-       struct rtl8139_private *np;
+       struct rtl8139_private *tp;
        /* TODO: we are too slack to do reg dumping for pio, for now */
        if (use_io)
                return 0;
-       np = netdev_priv(dev);
-       return np->regs_len;
+       tp = netdev_priv(dev);
+       return tp->regs_len;
 }
 
 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
 {
-       struct rtl8139_private *np;
+       struct rtl8139_private *tp;
 
        /* TODO: we are too slack to do reg dumping for pio, for now */
        if (use_io)
                return;
-       np = netdev_priv(dev);
+       tp = netdev_priv(dev);
 
        regs->version = RTL_REGS_VER;
 
-       spin_lock_irq(&np->lock);
-       memcpy_fromio(regbuf, np->mmio_addr, regs->len);
-       spin_unlock_irq(&np->lock);
+       spin_lock_irq(&tp->lock);
+       memcpy_fromio(regbuf, tp->mmio_addr, regs->len);
+       spin_unlock_irq(&tp->lock);
 }
 
 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
@@ -2454,12 +2454,12 @@ static int rtl8139_get_sset_count(struct net_device *dev, int sset)
 
 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
 {
-       struct rtl8139_private *np = netdev_priv(dev);
+       struct rtl8139_private *tp = netdev_priv(dev);
 
-       data[0] = np->xstats.early_rx;
-       data[1] = np->xstats.tx_buf_mapped;
-       data[2] = np->xstats.tx_timeouts;
-       data[3] = np->xstats.rx_lost_in_ring;
+       data[0] = tp->xstats.early_rx;
+       data[1] = tp->xstats.tx_buf_mapped;
+       data[2] = tp->xstats.tx_timeouts;
+       data[3] = tp->xstats.rx_lost_in_ring;
 }
 
 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
@@ -2486,15 +2486,15 @@ static const struct ethtool_ops rtl8139_ethtool_ops = {
 
 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 {
-       struct rtl8139_private *np = netdev_priv(dev);
+       struct rtl8139_private *tp = netdev_priv(dev);
        int rc;
 
        if (!netif_running(dev))
                return -EINVAL;
 
-       spin_lock_irq(&np->lock);
-       rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
-       spin_unlock_irq(&np->lock);
+       spin_lock_irq(&tp->lock);
+       rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL);
+       spin_unlock_irq(&tp->lock);
 
        return rc;
 }
index ec3e22e..21153de 100644 (file)
@@ -74,14 +74,8 @@ EXPORT_SYMBOL(ei_netdev_ops);
 struct net_device *__alloc_ei_netdev(int size)
 {
        struct net_device *dev = ____alloc_ei_netdev(size);
-#ifdef CONFIG_COMPAT_NET_DEV_OPS
-       if (dev) {
-               dev->hard_start_xmit = ei_start_xmit;
-               dev->get_stats  = ei_get_stats;
-               dev->set_multicast_list = ei_set_multicast_list;
-               dev->tx_timeout = ei_tx_timeout;
-       }
-#endif
+       if (dev)
+               dev->netdev_ops = &ei_netdev_ops;
        return dev;
 }
 EXPORT_SYMBOL(__alloc_ei_netdev);
index da863c9..d225c29 100644 (file)
@@ -79,14 +79,8 @@ EXPORT_SYMBOL(eip_netdev_ops);
 struct net_device *__alloc_eip_netdev(int size)
 {
        struct net_device *dev = ____alloc_ei_netdev(size);
-#ifdef CONFIG_COMPAT_NET_DEV_OPS
-       if (dev) {
-               dev->hard_start_xmit = eip_start_xmit;
-               dev->get_stats  = eip_get_stats;
-               dev->set_multicast_list = eip_set_multicast_list;
-               dev->tx_timeout = eip_tx_timeout;
-       }
-#endif
+       if (dev)
+               dev->netdev_ops = &eip_netdev_ops;
        return dev;
 }
 EXPORT_SYMBOL(__alloc_eip_netdev);
@@ -97,16 +91,15 @@ void NS8390p_init(struct net_device *dev, int startp)
 }
 EXPORT_SYMBOL(NS8390p_init);
 
-#if defined(MODULE)
-
-int init_module(void)
+static int __init NS8390p_init_module(void)
 {
        return 0;
 }
 
-void cleanup_module(void)
+static void __exit NS8390p_cleanup_module(void)
 {
 }
 
-#endif /* MODULE */
+module_init(NS8390p_init_module);
+module_exit(NS8390p_cleanup_module);
 MODULE_LICENSE("GPL");
index 214a92d..b8727d5 100644 (file)
@@ -2362,6 +2362,14 @@ config MV643XX_ETH
          Some boards that use the Discovery chipset are the Momenco
          Ocelot C and Jaguar ATX and Pegasos II.
 
+config XILINX_LL_TEMAC
+       tristate "Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver"
+       select PHYLIB
+       depends on PPC_DCR_NATIVE
+       help
+         This driver supports the Xilinx 10/100/1000 LocalLink TEMAC
+         core used in Xilinx Spartan and Virtex FPGAs
+
 config QLA3XXX
        tristate "QLogic QLA3XXX Network Driver Support"
        depends on PCI
@@ -2435,10 +2443,14 @@ menuconfig NETDEV_10000
 
 if NETDEV_10000
 
+config MDIO
+       tristate
+
 config CHELSIO_T1
         tristate "Chelsio 10Gb Ethernet support"
         depends on PCI
        select CRC32
+       select MDIO
         help
           This driver supports Chelsio gigabit and 10-gigabit
           Ethernet cards. More information about adapter features and
@@ -2471,6 +2483,7 @@ config CHELSIO_T3
        tristate "Chelsio Communications T3 10Gb Ethernet support"
        depends on CHELSIO_T3_DEPENDS
        select FW_LOADER
+       select MDIO
        help
          This driver supports Chelsio T3-based gigabit and 10Gb Ethernet
          adapters.
@@ -2506,6 +2519,7 @@ config ENIC
 config IXGBE
        tristate "Intel(R) 10GbE PCI Express adapters support"
        depends on PCI && INET
+       select MDIO
        ---help---
          This driver supports Intel(R) 10GbE PCI Express family of
          adapters.  For more information on how to identify your adapter, go
@@ -2668,6 +2682,7 @@ config TEHUTI
 config BNX2X
        tristate "Broadcom NetXtremeII 10Gb support"
        depends on PCI
+       select FW_LOADER
        select ZLIB_INFLATE
        select LIBCRC32C
        help
index 1fc4602..dcd5f15 100644 (file)
@@ -95,6 +95,7 @@ obj-$(CONFIG_SH_ETH) += sh_eth.o
 #
 
 obj-$(CONFIG_MII) += mii.o
+obj-$(CONFIG_MDIO) += mdio.o
 obj-$(CONFIG_PHYLIB) += phy/
 
 obj-$(CONFIG_SUNDANCE) += sundance.o
@@ -134,6 +135,8 @@ obj-$(CONFIG_AX88796) += ax88796.o
 
 obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o
 obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o
+ll_temac-objs := ll_temac_main.o ll_temac_mdio.o
+obj-$(CONFIG_XILINX_LL_TEMAC) += ll_temac.o
 obj-$(CONFIG_QLA3XXX) += qla3xxx.o
 obj-$(CONFIG_QLGE) += qlge/
 
index deb7b53..8b17278 100644 (file)
@@ -220,11 +220,11 @@ static void atl1c_check_link_status(struct atl1c_adapter *adapter)
                /* link down */
                if (netif_carrier_ok(netdev)) {
                        hw->hibernate = true;
-                       atl1c_set_aspm(hw, false);
                        if (atl1c_stop_mac(hw) != 0)
                                if (netif_msg_hw(adapter))
                                        dev_warn(&pdev->dev,
                                                "stop mac failed\n");
+                       atl1c_set_aspm(hw, false);
                }
                netif_carrier_off(netdev);
        } else {
@@ -240,10 +240,10 @@ static void atl1c_check_link_status(struct atl1c_adapter *adapter)
                    adapter->link_duplex != duplex) {
                        adapter->link_speed  = speed;
                        adapter->link_duplex = duplex;
+                       atl1c_set_aspm(hw, true);
                        atl1c_enable_tx_ctrl(hw);
                        atl1c_enable_rx_ctrl(hw);
                        atl1c_setup_mac_ctrl(adapter);
-                       atl1c_set_aspm(hw, true);
                        if (netif_msg_link(adapter))
                                dev_info(&pdev->dev,
                                        "%s: %s NIC Link is Up<%d Mbps %s>\n",
@@ -1242,9 +1242,7 @@ static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup)
 
        AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
 
-       pm_ctrl_data &= PM_CTRL_SERDES_PD_EX_L1;
-       pm_ctrl_data |= ~PM_CTRL_SERDES_BUDS_RX_L1_EN;
-       pm_ctrl_data |= ~PM_CTRL_SERDES_L1_EN;
+       pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
        pm_ctrl_data &=  ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
                        PM_CTRL_L1_ENTRY_TIMER_SHIFT);
 
@@ -1254,19 +1252,11 @@ static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup)
                pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
                pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
 
-               if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT) {
-                       pm_ctrl_data |= AT_ASPM_L1_TIMER <<
-                               PM_CTRL_L1_ENTRY_TIMER_SHIFT;
-                       pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
-               } else
-                       pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
-
-               if (hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT)
-                       pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN;
-               else
-                       pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
-
+               pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
+               pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
        } else {
+               pm_ctrl_data &= ~PM_CTRL_SERDES_BUDS_RX_L1_EN;
+               pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
                pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
                pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
 
index fb57b75..adac061 100644 (file)
@@ -1794,8 +1794,7 @@ static void atl1e_tx_map(struct atl1e_adapter *adapter,
                        memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
 
                        tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
-                       if (tx_buffer->skb)
-                               BUG();
+                       BUG_ON(tx_buffer->skb);
 
                        tx_buffer->skb = NULL;
                        tx_buffer->length =
index 0ab2254..13f0bdc 100644 (file)
@@ -2207,8 +2207,7 @@ static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
        nr_frags = skb_shinfo(skb)->nr_frags;
        next_to_use = atomic_read(&tpd_ring->next_to_use);
        buffer_info = &tpd_ring->buffer_info[next_to_use];
-       if (unlikely(buffer_info->skb))
-               BUG();
+       BUG_ON(buffer_info->skb);
        /* put skb in last TPD */
        buffer_info->skb = NULL;
 
@@ -2274,8 +2273,8 @@ static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
                        ATL1_MAX_TX_BUF_LEN;
                for (i = 0; i < nseg; i++) {
                        buffer_info = &tpd_ring->buffer_info[next_to_use];
-                       if (unlikely(buffer_info->skb))
-                               BUG();
+                       BUG_ON(buffer_info->skb);
+
                        buffer_info->skb = NULL;
                        buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ?
                                ATL1_MAX_TX_BUF_LEN : buf_len;
index 9b75aa6..8994b03 100644 (file)
@@ -637,6 +637,22 @@ static void be_rx_stats_update(struct be_adapter *adapter,
        stats->be_rx_bytes += pktsize;
 }
 
+static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
+{
+       u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
+
+       l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
+       ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
+       ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
+       if (ip_version) {
+               tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
+               udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
+       }
+       ipv6_chk = (ip_version && (tcpf || udpf));
+
+       return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
+}
+
 static struct be_rx_page_info *
 get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
 {
@@ -752,9 +768,7 @@ static void be_rx_compl_process(struct be_adapter *adapter,
 {
        struct sk_buff *skb;
        u32 vtp, vid;
-       int l4_cksm;
 
-       l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
        vtp = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
 
        skb = netdev_alloc_skb(adapter->netdev, BE_HDR_LEN + NET_IP_ALIGN);
@@ -769,10 +783,10 @@ static void be_rx_compl_process(struct be_adapter *adapter,
 
        skb_fill_rx_data(adapter, skb, rxcp);
 
-       if (l4_cksm && adapter->rx_csum)
-               skb->ip_summed = CHECKSUM_UNNECESSARY;
-       else
+       if (do_pkt_csum(rxcp, adapter->rx_csum))
                skb->ip_summed = CHECKSUM_NONE;
+       else
+               skb->ip_summed = CHECKSUM_UNNECESSARY;
 
        skb->truesize = skb->len + sizeof(struct sk_buff);
        skb->protocol = eth_type_trans(skb, adapter->netdev);
@@ -1626,10 +1640,12 @@ static void be_netdev_init(struct net_device *netdev)
 
        netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
                NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_IP_CSUM |
-               NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
+               NETIF_F_IPV6_CSUM;
 
        netdev->flags |= IFF_MULTICAST;
 
+       adapter->rx_csum = true;
+
        BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
 
        SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
index 44d015f..9578a3d 100644 (file)
@@ -1247,6 +1247,16 @@ static const struct ethtool_ops bmac_ethtool_ops = {
        .get_link               = ethtool_op_get_link,
 };
 
+static const struct net_device_ops bmac_netdev_ops = {
+       .ndo_open               = bmac_open,
+       .ndo_stop               = bmac_close,
+       .ndo_start_xmit         = bmac_output,
+       .ndo_set_multicast_list = bmac_set_multicast,
+       .ndo_set_mac_address    = bmac_set_address,
+       .ndo_change_mtu         = eth_change_mtu,
+       .ndo_validate_addr      = eth_validate_addr,
+};
+
 static int __devinit bmac_probe(struct macio_dev *mdev, const struct of_device_id *match)
 {
        int j, rev, ret;
@@ -1308,12 +1318,8 @@ static int __devinit bmac_probe(struct macio_dev *mdev, const struct of_device_i
        bmac_enable_and_reset_chip(dev);
        bmwrite(dev, INTDISABLE, DisableAll);
 
-       dev->open = bmac_open;
-       dev->stop = bmac_close;
+       dev->netdev_ops = &bmac_netdev_ops;
        dev->ethtool_ops = &bmac_ethtool_ops;
-       dev->hard_start_xmit = bmac_output;
-       dev->set_multicast_list = bmac_set_multicast;
-       dev->set_mac_address = bmac_set_address;
 
        bmac_get_station_address(dev, addr);
        if (bmac_verify_checksum(dev) != 0)
index a329bee..8678457 100644 (file)
@@ -965,6 +965,21 @@ struct bnx2x {
        int                     gunzip_outlen;
 #define FW_BUF_SIZE                    0x8000
 
+       struct raw_op          *init_ops;
+       /* Init blocks offsets inside init_ops */
+       u16                    *init_ops_offsets;
+       /* Data blob - has 32 bit granularity */
+       u32                    *init_data;
+       /* Zipped PRAM blobs - raw data */
+       const u8               *tsem_int_table_data;
+       const u8               *tsem_pram_data;
+       const u8               *usem_int_table_data;
+       const u8               *usem_pram_data;
+       const u8               *xsem_int_table_data;
+       const u8               *xsem_pram_data;
+       const u8               *csem_int_table_data;
+       const u8               *csem_pram_data;
+        const struct firmware  *firmware;
 };
 
 
diff --git a/drivers/net/bnx2x_fw_file_hdr.h b/drivers/net/bnx2x_fw_file_hdr.h
new file mode 100644 (file)
index 0000000..3f5ee5d
--- /dev/null
@@ -0,0 +1,37 @@
+/* bnx2x_fw_file_hdr.h: FW binary file header structure.
+ *
+ * Copyright (c) 2007-2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Maintained by: Eilon Greenstein <eilong@broadcom.com>
+ * Written by: Vladislav Zolotarov <vladz@broadcom.com>
+ * Based on the original idea of John Wright <john.wright@hp.com>.
+ */
+
+#ifndef BNX2X_INIT_FILE_HDR_H
+#define BNX2X_INIT_FILE_HDR_H
+
+struct bnx2x_fw_file_section {
+       __be32 len;
+       __be32 offset;
+};
+
+struct bnx2x_fw_file_hdr {
+       struct bnx2x_fw_file_section init_ops;
+       struct bnx2x_fw_file_section init_ops_offsets;
+       struct bnx2x_fw_file_section init_data;
+       struct bnx2x_fw_file_section tsem_int_table_data;
+       struct bnx2x_fw_file_section tsem_pram_data;
+       struct bnx2x_fw_file_section usem_int_table_data;
+       struct bnx2x_fw_file_section usem_pram_data;
+       struct bnx2x_fw_file_section csem_int_table_data;
+       struct bnx2x_fw_file_section csem_pram_data;
+       struct bnx2x_fw_file_section xsem_int_table_data;
+       struct bnx2x_fw_file_section xsem_pram_data;
+       struct bnx2x_fw_file_section fw_version;
+};
+
+#endif /* BNX2X_INIT_FILE_HDR_H */
index 39ba293..3ba4d88 100644 (file)
@@ -1,4 +1,5 @@
 /* bnx2x_init.h: Broadcom Everest network driver.
+ *               Structures and macroes needed during the initialization.
  *
  * Copyright (c) 2007-2009 Broadcom Corporation
  *
@@ -8,6 +9,7 @@
  *
  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  * Written by: Eliezer Tamir
+ * Modified by: Vladislav Zolotarov <vladz@broadcom.com>
  */
 
 #ifndef BNX2X_INIT_H
 #define OP_WR_64               0x8 /* write 64 bit pattern */
 #define OP_WB                  0x9 /* copy a string using DMAE */
 
-/* Operation specific for E1 */
-#define OP_RD_E1               0xa /* read single register */
-#define OP_WR_E1               0xb /* write single register */
-#define OP_IW_E1               0xc /* write single register using mailbox */
-#define OP_SW_E1               0xd /* copy a string to the device */
-#define OP_SI_E1               0xe /* copy a string using mailbox */
-#define OP_ZR_E1               0xf /* clear memory */
-#define OP_ZP_E1               0x10 /* unzip then copy with DMAE */
-#define OP_WR_64_E1            0x11 /* write 64 bit pattern on E1 */
-#define OP_WB_E1               0x12 /* copy a string using DMAE */
-
-/* Operation specific for E1H */
-#define OP_RD_E1H              0x13 /* read single register */
-#define OP_WR_E1H              0x14 /* write single register */
-#define OP_IW_E1H              0x15 /* write single register using mailbox */
-#define OP_SW_E1H              0x16 /* copy a string to the device */
-#define OP_SI_E1H              0x17 /* copy a string using mailbox */
-#define OP_ZR_E1H              0x18 /* clear memory */
-#define OP_ZP_E1H              0x19 /* unzip then copy with DMAE */
-#define OP_WR_64_E1H           0x1a /* write 64 bit pattern on E1H */
-#define OP_WB_E1H              0x1b /* copy a string using DMAE */
-
 /* FPGA and EMUL specific operations */
-#define OP_WR_EMUL_E1H         0x1c /* write single register on E1H Emul */
-#define OP_WR_EMUL             0x1d /* write single register on Emulation */
-#define OP_WR_FPGA             0x1e /* write single register on FPGA */
-#define OP_WR_ASIC             0x1f /* write single register on ASIC */
+#define OP_WR_EMUL             0xa /* write single register on Emulation */
+#define OP_WR_FPGA             0xb /* write single register on FPGA */
+#define OP_WR_ASIC             0xc /* write single register on ASIC */
+
+/* Init stages */
+#define COMMON_STAGE            0
+#define PORT0_STAGE            1
+#define PORT1_STAGE            2
+/* Never reorder FUNCx stages !!! */
+#define FUNC0_STAGE            3
+#define FUNC1_STAGE            4
+#define FUNC2_STAGE            5
+#define FUNC3_STAGE            6
+#define FUNC4_STAGE            7
+#define FUNC5_STAGE            8
+#define FUNC6_STAGE            9
+#define FUNC7_STAGE            10
+#define STAGE_IDX_MAX          11
+
+#define STAGE_START            0
+#define STAGE_END              1
+
+
+/* Indices of blocks */
+#define PRS_BLOCK               0
+#define SRCH_BLOCK              1
+#define TSDM_BLOCK              2
+#define TCM_BLOCK               3
+#define BRB1_BLOCK              4
+#define TSEM_BLOCK              5
+#define PXPCS_BLOCK             6
+#define EMAC0_BLOCK             7
+#define EMAC1_BLOCK             8
+#define DBU_BLOCK               9
+#define MISC_BLOCK              10
+#define DBG_BLOCK               11
+#define NIG_BLOCK               12
+#define MCP_BLOCK               13
+#define UPB_BLOCK               14
+#define CSDM_BLOCK              15
+#define USDM_BLOCK              16
+#define CCM_BLOCK               17
+#define UCM_BLOCK               18
+#define USEM_BLOCK              19
+#define CSEM_BLOCK              20
+#define XPB_BLOCK               21
+#define DQ_BLOCK                22
+#define TIMERS_BLOCK            23
+#define XSDM_BLOCK              24
+#define QM_BLOCK                25
+#define PBF_BLOCK               26
+#define XCM_BLOCK               27
+#define XSEM_BLOCK              28
+#define CDU_BLOCK               29
+#define DMAE_BLOCK              30
+#define PXP_BLOCK               31
+#define CFC_BLOCK               32
+#define HC_BLOCK                33
+#define PXP2_BLOCK              34
+#define MISC_AEU_BLOCK          35
+
+/* Returns the index of start or end of a specific block stage in ops array*/
+#define BLOCK_OPS_IDX(block, stage, end) \
+       (2*(((block)*STAGE_IDX_MAX) + (stage)) + (end))
 
 
 struct raw_op {
@@ -118,292 +158,6 @@ union init_op {
        struct raw_op           raw;
 };
 
-#include "bnx2x_init_values.h"
-
-static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
-static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len);
-
-static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
-                             u32 len)
-{
-       int i;
-
-       for (i = 0; i < len; i++) {
-               REG_WR(bp, addr + i*4, data[i]);
-               if (!(i % 10000)) {
-                       touch_softlockup_watchdog();
-                       cpu_relax();
-               }
-       }
-}
-
-static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
-                             u16 len)
-{
-       int i;
-
-       for (i = 0; i < len; i++) {
-               REG_WR_IND(bp, addr + i*4, data[i]);
-               if (!(i % 10000)) {
-                       touch_softlockup_watchdog();
-                       cpu_relax();
-               }
-       }
-}
-
-static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
-{
-       int offset = 0;
-
-       if (bp->dmae_ready) {
-               while (len > DMAE_LEN32_WR_MAX) {
-                       bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
-                                        addr + offset, DMAE_LEN32_WR_MAX);
-                       offset += DMAE_LEN32_WR_MAX * 4;
-                       len -= DMAE_LEN32_WR_MAX;
-               }
-               bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
-                                addr + offset, len);
-       } else
-               bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
-}
-
-static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
-{
-       u32 buf_len = (((len * 4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len * 4));
-       u32 buf_len32 = buf_len / 4;
-       int i;
-
-       memset(bp->gunzip_buf, fill, buf_len);
-
-       for (i = 0; i < len; i += buf_len32) {
-               u32 cur_len = min(buf_len32, len - i);
-
-               bnx2x_write_big_buf(bp, addr + i * 4, cur_len);
-       }
-}
-
-static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
-                            u32 len64)
-{
-       u32 buf_len32 = FW_BUF_SIZE / 4;
-       u32 len = len64 * 2;
-       u64 data64 = 0;
-       int i;
-
-       /* 64 bit value is in a blob: first low DWORD, then high DWORD */
-       data64 = HILO_U64((*(data + 1)), (*data));
-       len64 = min((u32)(FW_BUF_SIZE/8), len64);
-       for (i = 0; i < len64; i++) {
-               u64 *pdata = ((u64 *)(bp->gunzip_buf)) + i;
-
-               *pdata = data64;
-       }
-
-       for (i = 0; i < len; i += buf_len32) {
-               u32 cur_len = min(buf_len32, len - i);
-
-               bnx2x_write_big_buf(bp, addr + i * 4, cur_len);
-       }
-}
-
-/*********************************************************
-   There are different blobs for each PRAM section.
-   In addition, each blob write operation is divided into a few operations
-   in order to decrease the amount of phys. contiguous buffer needed.
-   Thus, when we select a blob the address may be with some offset
-   from the beginning of PRAM section.
-   The same holds for the INT_TABLE sections.
-**********************************************************/
-#define IF_IS_INT_TABLE_ADDR(base, addr) \
-                       if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
-
-#define IF_IS_PRAM_ADDR(base, addr) \
-                       if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
-
-static const u32 *bnx2x_sel_blob(u32 addr, const u32 *data, int is_e1)
-{
-       IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
-               data = is_e1 ? tsem_int_table_data_e1 :
-                              tsem_int_table_data_e1h;
-       else
-               IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
-                       data = is_e1 ? csem_int_table_data_e1 :
-                                      csem_int_table_data_e1h;
-       else
-               IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
-                       data = is_e1 ? usem_int_table_data_e1 :
-                                      usem_int_table_data_e1h;
-       else
-               IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
-                       data = is_e1 ? xsem_int_table_data_e1 :
-                                      xsem_int_table_data_e1h;
-       else
-               IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
-                       data = is_e1 ? tsem_pram_data_e1 : tsem_pram_data_e1h;
-       else
-               IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
-                       data = is_e1 ? csem_pram_data_e1 : csem_pram_data_e1h;
-       else
-               IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
-                       data = is_e1 ? usem_pram_data_e1 : usem_pram_data_e1h;
-       else
-               IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
-                       data = is_e1 ? xsem_pram_data_e1 : xsem_pram_data_e1h;
-
-       return data;
-}
-
-static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
-                            u32 len, int gunzip, int is_e1, u32 blob_off)
-{
-       int offset = 0;
-
-       data = bnx2x_sel_blob(addr, data, is_e1) + blob_off;
-
-       if (gunzip) {
-               int rc;
-#ifdef __BIG_ENDIAN
-               int i, size;
-               u32 *temp;
-
-               temp = kmalloc(len, GFP_KERNEL);
-               size = (len / 4) + ((len % 4) ? 1 : 0);
-               for (i = 0; i < size; i++)
-                       temp[i] = swab32(data[i]);
-               data = temp;
-#endif
-               rc = bnx2x_gunzip(bp, (u8 *)data, len);
-               if (rc) {
-                       BNX2X_ERR("gunzip failed ! rc %d\n", rc);
-#ifdef __BIG_ENDIAN
-                       kfree(temp);
-#endif
-                       return;
-               }
-               len = bp->gunzip_outlen;
-#ifdef __BIG_ENDIAN
-               kfree(temp);
-               for (i = 0; i < len; i++)
-                       ((u32 *)bp->gunzip_buf)[i] =
-                                       swab32(((u32 *)bp->gunzip_buf)[i]);
-#endif
-       } else {
-               if ((len * 4) > FW_BUF_SIZE) {
-                       BNX2X_ERR("LARGE DMAE OPERATION ! "
-                                 "addr 0x%x  len 0x%x\n", addr, len*4);
-                       return;
-               }
-               memcpy(bp->gunzip_buf, data, len * 4);
-       }
-
-       if (bp->dmae_ready) {
-               while (len > DMAE_LEN32_WR_MAX) {
-                       bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
-                                        addr + offset, DMAE_LEN32_WR_MAX);
-                       offset += DMAE_LEN32_WR_MAX * 4;
-                       len -= DMAE_LEN32_WR_MAX;
-               }
-               bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
-                                addr + offset, len);
-       } else
-               bnx2x_init_ind_wr(bp, addr, bp->gunzip_buf, len);
-}
-
-static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
-{
-       int is_e1       = CHIP_IS_E1(bp);
-       int is_e1h      = CHIP_IS_E1H(bp);
-       int is_emul_e1h = (CHIP_REV_IS_EMUL(bp) && is_e1h);
-       int hw_wr, i;
-       union init_op *op;
-       u32 op_type, addr, len;
-       const u32 *data, *data_base;
-
-       if (CHIP_REV_IS_FPGA(bp))
-               hw_wr = OP_WR_FPGA;
-       else if (CHIP_REV_IS_EMUL(bp))
-               hw_wr = OP_WR_EMUL;
-       else
-               hw_wr = OP_WR_ASIC;
-
-       if (is_e1)
-               data_base = init_data_e1;
-       else /* CHIP_IS_E1H(bp) */
-               data_base = init_data_e1h;
-
-       for (i = op_start; i < op_end; i++) {
-
-               op = (union init_op *)&(init_ops[i]);
-
-               op_type = op->str_wr.op;
-               addr = op->str_wr.offset;
-               len = op->str_wr.data_len;
-               data = data_base + op->str_wr.data_off;
-
-               /* careful! it must be in order */
-               if (unlikely(op_type > OP_WB)) {
-
-                       /* If E1 only */
-                       if (op_type <= OP_WB_E1) {
-                               if (is_e1)
-                                       op_type -= (OP_RD_E1 - OP_RD);
-
-                       /* If E1H only */
-                       } else if (op_type <= OP_WB_E1H) {
-                               if (is_e1h)
-                                       op_type -= (OP_RD_E1H - OP_RD);
-                       }
-
-                       /* HW/EMUL specific */
-                       if (op_type == hw_wr)
-                               op_type = OP_WR;
-
-                       /* EMUL on E1H is special */
-                       if ((op_type == OP_WR_EMUL_E1H) && is_emul_e1h)
-                               op_type = OP_WR;
-               }
-
-               switch (op_type) {
-               case OP_RD:
-                       REG_RD(bp, addr);
-                       break;
-               case OP_WR:
-                       REG_WR(bp, addr, op->write.val);
-                       break;
-               case OP_SW:
-                       bnx2x_init_str_wr(bp, addr, data, len);
-                       break;
-               case OP_WB:
-                       bnx2x_init_wr_wb(bp, addr, data, len, 0, is_e1, 0);
-                       break;
-               case OP_SI:
-                       bnx2x_init_ind_wr(bp, addr, data, len);
-                       break;
-               case OP_ZR:
-                       bnx2x_init_fill(bp, addr, 0, op->zero.len);
-                       break;
-               case OP_ZP:
-                       bnx2x_init_wr_wb(bp, addr, data, len, 1, is_e1,
-                                        op->str_wr.data_off);
-                       break;
-               case OP_WR_64:
-                       bnx2x_init_wr_64(bp, addr, data, len);
-                       break;
-               default:
-                       /* happens whenever an op is of a diff HW */
-#if 0
-                       DP(NETIF_MSG_HW, "skipping init operation  "
-                          "index %d[%d:%d]: type %d  addr 0x%x  "
-                          "len %d(0x%x)\n",
-                          i, op_start, op_end, op_type, addr, len, len);
-#endif
-                       break;
-               }
-       }
-}
-
-
 /****************************************************************************
 * PXP
 ****************************************************************************/
@@ -567,111 +321,6 @@ static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
                PXP2_REG_RQ_BW_WR_UBOUND30}
 };
 
-static void bnx2x_init_pxp(struct bnx2x *bp)
-{
-       u16 devctl;
-       int r_order, w_order;
-       u32 val, i;
-
-       pci_read_config_word(bp->pdev,
-                            bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
-       DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
-       w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
-       if (bp->mrrs == -1)
-               r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
-       else {
-               DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
-               r_order = bp->mrrs;
-       }
-
-       if (r_order > MAX_RD_ORD) {
-               DP(NETIF_MSG_HW, "read order of %d  order adjusted to %d\n",
-                  r_order, MAX_RD_ORD);
-               r_order = MAX_RD_ORD;
-       }
-       if (w_order > MAX_WR_ORD) {
-               DP(NETIF_MSG_HW, "write order of %d  order adjusted to %d\n",
-                  w_order, MAX_WR_ORD);
-               w_order = MAX_WR_ORD;
-       }
-       if (CHIP_REV_IS_FPGA(bp)) {
-               DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
-               w_order = 0;
-       }
-       DP(NETIF_MSG_HW, "read order %d  write order %d\n", r_order, w_order);
-
-       for (i = 0; i < NUM_RD_Q-1; i++) {
-               REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l);
-               REG_WR(bp, read_arb_addr[i].add,
-                      read_arb_data[i][r_order].add);
-               REG_WR(bp, read_arb_addr[i].ubound,
-                      read_arb_data[i][r_order].ubound);
-       }
-
-       for (i = 0; i < NUM_WR_Q-1; i++) {
-               if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
-                   (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
-
-                       REG_WR(bp, write_arb_addr[i].l,
-                              write_arb_data[i][w_order].l);
-
-                       REG_WR(bp, write_arb_addr[i].add,
-                              write_arb_data[i][w_order].add);
-
-                       REG_WR(bp, write_arb_addr[i].ubound,
-                              write_arb_data[i][w_order].ubound);
-               } else {
-
-                       val = REG_RD(bp, write_arb_addr[i].l);
-                       REG_WR(bp, write_arb_addr[i].l,
-                              val | (write_arb_data[i][w_order].l << 10));
-
-                       val = REG_RD(bp, write_arb_addr[i].add);
-                       REG_WR(bp, write_arb_addr[i].add,
-                              val | (write_arb_data[i][w_order].add << 10));
-
-                       val = REG_RD(bp, write_arb_addr[i].ubound);
-                       REG_WR(bp, write_arb_addr[i].ubound,
-                              val | (write_arb_data[i][w_order].ubound << 7));
-               }
-       }
-
-       val =  write_arb_data[NUM_WR_Q-1][w_order].add;
-       val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
-       val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
-       REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val);
-
-       val =  read_arb_data[NUM_RD_Q-1][r_order].add;
-       val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
-       val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
-       REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val);
-
-       REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order);
-       REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order);
-       REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order);
-       REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order);
-
-       if (r_order == MAX_RD_ORD)
-               REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
-
-       REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
-
-       if (CHIP_IS_E1H(bp)) {
-               val = ((w_order == 0) ? 2 : 3);
-               REG_WR(bp, PXP2_REG_WR_HC_MPS, val);
-               REG_WR(bp, PXP2_REG_WR_USDM_MPS, val);
-               REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val);
-               REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val);
-               REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val);
-               REG_WR(bp, PXP2_REG_WR_QM_MPS, val);
-               REG_WR(bp, PXP2_REG_WR_TM_MPS, val);
-               REG_WR(bp, PXP2_REG_WR_SRC_MPS, val);
-               REG_WR(bp, PXP2_REG_WR_DBG_MPS, val);
-               REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */
-               REG_WR(bp, PXP2_REG_WR_CDU_MPS, val);
-       }
-}
-
 
 /****************************************************************************
 * CDU
@@ -695,128 +344,12 @@ static void bnx2x_init_pxp(struct bnx2x *bp)
        (0x80 | ((_type) & 0xf << 3) | (CDU_CRC8(_cid, _region, _type) & 0x7))
 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val)       ((_val) & ~0x80)
 
-/*****************************************************************************
- * Description:
- *         Calculates crc 8 on a word value: polynomial 0-1-2-8
- *         Code was translated from Verilog.
- ****************************************************************************/
-static u8 calc_crc8(u32 data, u8 crc)
-{
-       u8 D[32];
-       u8 NewCRC[8];
-       u8 C[8];
-       u8 crc_res;
-       u8 i;
-
-       /* split the data into 31 bits */
-       for (i = 0; i < 32; i++) {
-               D[i] = data & 1;
-               data = data >> 1;
-       }
-
-       /* split the crc into 8 bits */
-       for (i = 0; i < 8; i++) {
-               C[i] = crc & 1;
-               crc = crc >> 1;
-       }
-
-       NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
-               D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
-               C[6] ^ C[7];
-       NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
-               D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
-               D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6];
-       NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
-               D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
-               C[0] ^ C[1] ^ C[4] ^ C[5];
-       NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
-               D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
-               C[1] ^ C[2] ^ C[5] ^ C[6];
-       NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
-               D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
-               C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
-       NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
-               D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
-               C[3] ^ C[4] ^ C[7];
-       NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
-               D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
-               C[5];
-       NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
-               D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
-               C[6];
-
-       crc_res = 0;
-       for (i = 0; i < 8; i++)
-               crc_res |= (NewCRC[i] << i);
-
-       return crc_res;
-}
 
 /* registers addresses are not in order
    so these arrays help simplify the code */
-static const int cm_start[E1H_FUNC_MAX][9] = {
-       {MISC_FUNC0_START, TCM_FUNC0_START, UCM_FUNC0_START, CCM_FUNC0_START,
-        XCM_FUNC0_START, TSEM_FUNC0_START, USEM_FUNC0_START, CSEM_FUNC0_START,
-        XSEM_FUNC0_START},
-       {MISC_FUNC1_START, TCM_FUNC1_START, UCM_FUNC1_START, CCM_FUNC1_START,
-        XCM_FUNC1_START, TSEM_FUNC1_START, USEM_FUNC1_START, CSEM_FUNC1_START,
-        XSEM_FUNC1_START},
-       {MISC_FUNC2_START, TCM_FUNC2_START, UCM_FUNC2_START, CCM_FUNC2_START,
-        XCM_FUNC2_START, TSEM_FUNC2_START, USEM_FUNC2_START, CSEM_FUNC2_START,
-        XSEM_FUNC2_START},
-       {MISC_FUNC3_START, TCM_FUNC3_START, UCM_FUNC3_START, CCM_FUNC3_START,
-        XCM_FUNC3_START, TSEM_FUNC3_START, USEM_FUNC3_START, CSEM_FUNC3_START,
-        XSEM_FUNC3_START},
-       {MISC_FUNC4_START, TCM_FUNC4_START, UCM_FUNC4_START, CCM_FUNC4_START,
-        XCM_FUNC4_START, TSEM_FUNC4_START, USEM_FUNC4_START, CSEM_FUNC4_START,
-        XSEM_FUNC4_START},
-       {MISC_FUNC5_START, TCM_FUNC5_START, UCM_FUNC5_START, CCM_FUNC5_START,
-        XCM_FUNC5_START, TSEM_FUNC5_START, USEM_FUNC5_START, CSEM_FUNC5_START,
-        XSEM_FUNC5_START},
-       {MISC_FUNC6_START, TCM_FUNC6_START, UCM_FUNC6_START, CCM_FUNC6_START,
-        XCM_FUNC6_START, TSEM_FUNC6_START, USEM_FUNC6_START, CSEM_FUNC6_START,
-        XSEM_FUNC6_START},
-       {MISC_FUNC7_START, TCM_FUNC7_START, UCM_FUNC7_START, CCM_FUNC7_START,
-        XCM_FUNC7_START, TSEM_FUNC7_START, USEM_FUNC7_START, CSEM_FUNC7_START,
-        XSEM_FUNC7_START}
-};
-
-static const int cm_end[E1H_FUNC_MAX][9] = {
-       {MISC_FUNC0_END, TCM_FUNC0_END, UCM_FUNC0_END, CCM_FUNC0_END,
-        XCM_FUNC0_END, TSEM_FUNC0_END, USEM_FUNC0_END, CSEM_FUNC0_END,
-        XSEM_FUNC0_END},
-       {MISC_FUNC1_END, TCM_FUNC1_END, UCM_FUNC1_END, CCM_FUNC1_END,
-        XCM_FUNC1_END, TSEM_FUNC1_END, USEM_FUNC1_END, CSEM_FUNC1_END,
-        XSEM_FUNC1_END},
-       {MISC_FUNC2_END, TCM_FUNC2_END, UCM_FUNC2_END, CCM_FUNC2_END,
-        XCM_FUNC2_END, TSEM_FUNC2_END, USEM_FUNC2_END, CSEM_FUNC2_END,
-        XSEM_FUNC2_END},
-       {MISC_FUNC3_END, TCM_FUNC3_END, UCM_FUNC3_END, CCM_FUNC3_END,
-        XCM_FUNC3_END, TSEM_FUNC3_END, USEM_FUNC3_END, CSEM_FUNC3_END,
-        XSEM_FUNC3_END},
-       {MISC_FUNC4_END, TCM_FUNC4_END, UCM_FUNC4_END, CCM_FUNC4_END,
-        XCM_FUNC4_END, TSEM_FUNC4_END, USEM_FUNC4_END, CSEM_FUNC4_END,
-        XSEM_FUNC4_END},
-       {MISC_FUNC5_END, TCM_FUNC5_END, UCM_FUNC5_END, CCM_FUNC5_END,
-        XCM_FUNC5_END, TSEM_FUNC5_END, USEM_FUNC5_END, CSEM_FUNC5_END,
-        XSEM_FUNC5_END},
-       {MISC_FUNC6_END, TCM_FUNC6_END, UCM_FUNC6_END, CCM_FUNC6_END,
-        XCM_FUNC6_END, TSEM_FUNC6_END, USEM_FUNC6_END, CSEM_FUNC6_END,
-        XSEM_FUNC6_END},
-       {MISC_FUNC7_END, TCM_FUNC7_END, UCM_FUNC7_END, CCM_FUNC7_END,
-        XCM_FUNC7_END, TSEM_FUNC7_END, USEM_FUNC7_END, CSEM_FUNC7_END,
-        XSEM_FUNC7_END},
-};
-
-static const int hc_limits[E1H_FUNC_MAX][2] = {
-       {HC_FUNC0_START, HC_FUNC0_END},
-       {HC_FUNC1_START, HC_FUNC1_END},
-       {HC_FUNC2_START, HC_FUNC2_END},
-       {HC_FUNC3_START, HC_FUNC3_END},
-       {HC_FUNC4_START, HC_FUNC4_END},
-       {HC_FUNC5_START, HC_FUNC5_END},
-       {HC_FUNC6_START, HC_FUNC6_END},
-       {HC_FUNC7_START, HC_FUNC7_END}
+static const int cm_blocks[9] = {
+       MISC_BLOCK, TCM_BLOCK,  UCM_BLOCK,  CCM_BLOCK, XCM_BLOCK,
+       TSEM_BLOCK, USEM_BLOCK, CSEM_BLOCK, XSEM_BLOCK
 };
 
 #endif /* BNX2X_INIT_H */
diff --git a/drivers/net/bnx2x_init_ops.h b/drivers/net/bnx2x_init_ops.h
new file mode 100644 (file)
index 0000000..32552b9
--- /dev/null
@@ -0,0 +1,442 @@
+/* bnx2x_init_ops.h: Broadcom Everest network driver.
+ *               Static functions needed during the initialization.
+ *               This file is "included" in bnx2x_main.c.
+ *
+ * Copyright (c) 2007-2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Maintained by: Eilon Greenstein <eilong@broadcom.com>
+ * Written by: Vladislav Zolotarov <vladz@broadcom.com>
+ */
+#ifndef BNX2X_INIT_OPS_H
+#define BNX2X_INIT_OPS_H
+
+static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
+static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len);
+
+static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
+                             u32 len)
+{
+       int i;
+
+       for (i = 0; i < len; i++) {
+               REG_WR(bp, addr + i*4, data[i]);
+               if (!(i % 10000)) {
+                       touch_softlockup_watchdog();
+                       cpu_relax();
+               }
+       }
+}
+
+static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
+                             u16 len)
+{
+       int i;
+
+       for (i = 0; i < len; i++) {
+               REG_WR_IND(bp, addr + i*4, data[i]);
+               if (!(i % 10000)) {
+                       touch_softlockup_watchdog();
+                       cpu_relax();
+               }
+       }
+}
+
+static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
+{
+       int offset = 0;
+
+       if (bp->dmae_ready) {
+               while (len > DMAE_LEN32_WR_MAX) {
+                       bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
+                                        addr + offset, DMAE_LEN32_WR_MAX);
+                       offset += DMAE_LEN32_WR_MAX * 4;
+                       len -= DMAE_LEN32_WR_MAX;
+               }
+               bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
+                                addr + offset, len);
+       } else
+               bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
+}
+
+static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
+{
+       u32 buf_len = (((len * 4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len * 4));
+       u32 buf_len32 = buf_len / 4;
+       int i;
+
+       memset(bp->gunzip_buf, fill, buf_len);
+
+       for (i = 0; i < len; i += buf_len32) {
+               u32 cur_len = min(buf_len32, len - i);
+
+               bnx2x_write_big_buf(bp, addr + i * 4, cur_len);
+       }
+}
+
+static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
+                            u32 len64)
+{
+       u32 buf_len32 = FW_BUF_SIZE / 4;
+       u32 len = len64 * 2;
+       u64 data64 = 0;
+       int i;
+
+       /* 64 bit value is in a blob: first low DWORD, then high DWORD */
+       data64 = HILO_U64((*(data + 1)), (*data));
+       len64 = min((u32)(FW_BUF_SIZE/8), len64);
+       for (i = 0; i < len64; i++) {
+               u64 *pdata = ((u64 *)(bp->gunzip_buf)) + i;
+
+               *pdata = data64;
+       }
+
+       for (i = 0; i < len; i += buf_len32) {
+               u32 cur_len = min(buf_len32, len - i);
+
+               bnx2x_write_big_buf(bp, addr + i * 4, cur_len);
+       }
+}
+
+/*********************************************************
+   There are different blobs for each PRAM section.
+   In addition, each blob write operation is divided into a few operations
+   in order to decrease the amount of phys. contiguous buffer needed.
+   Thus, when we select a blob the address may be with some offset
+   from the beginning of PRAM section.
+   The same holds for the INT_TABLE sections.
+**********************************************************/
+#define IF_IS_INT_TABLE_ADDR(base, addr) \
+                       if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
+
+#define IF_IS_PRAM_ADDR(base, addr) \
+                       if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
+
+static const u8 *bnx2x_sel_blob(struct bnx2x *bp, u32 addr, const u8 *data)
+{
+       IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
+               data = bp->tsem_int_table_data;
+       else IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
+               data = bp->csem_int_table_data;
+       else IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
+               data = bp->usem_int_table_data;
+       else IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
+               data = bp->xsem_int_table_data;
+       else IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
+               data = bp->tsem_pram_data;
+       else IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
+               data = bp->csem_pram_data;
+       else IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
+               data = bp->usem_pram_data;
+       else IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
+               data = bp->xsem_pram_data;
+
+       return data;
+}
+
+static void bnx2x_write_big_buf_wb(struct bnx2x *bp, u32 addr, u32 len)
+{
+       int offset = 0;
+
+       if (bp->dmae_ready) {
+               while (len > DMAE_LEN32_WR_MAX) {
+                       bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
+                                        addr + offset, DMAE_LEN32_WR_MAX);
+                       offset += DMAE_LEN32_WR_MAX * 4;
+                       len -= DMAE_LEN32_WR_MAX;
+               }
+               bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
+                                addr + offset, len);
+       } else
+               bnx2x_init_ind_wr(bp, addr, bp->gunzip_buf, len);
+}
+
+static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
+                            u32 len)
+{
+       /* This is needed for NO_ZIP mode, currently supported
+          in little endian mode only */
+       data = (const u32*)bnx2x_sel_blob(bp, addr, (const u8*)data);
+
+       if ((len * 4) > FW_BUF_SIZE) {
+               BNX2X_ERR("LARGE DMAE OPERATION ! "
+                         "addr 0x%x  len 0x%x\n", addr, len*4);
+               return;
+       }
+       memcpy(bp->gunzip_buf, data, len * 4);
+
+       bnx2x_write_big_buf_wb(bp, addr, len);
+}
+
+static void bnx2x_init_wr_zp(struct bnx2x *bp, u32 addr,
+                            u32 len, u32 blob_off)
+{
+       int rc, i;
+        const u8 *data = NULL;
+
+       data = bnx2x_sel_blob(bp, addr, data) + 4*blob_off;
+
+       if (data == NULL) {
+               panic("Blob not found for addr 0x%x\n", addr);
+               return;
+       }
+
+       rc = bnx2x_gunzip(bp, data, len);
+       if (rc) {
+               BNX2X_ERR("gunzip failed ! addr 0x%x rc %d\n", addr, rc);
+               BNX2X_ERR("blob_offset=0x%x\n", blob_off);
+               return;
+       }
+
+       /* gunzip_outlen is in dwords */
+       len = bp->gunzip_outlen;
+       for (i = 0; i < len; i++)
+               ((u32 *)bp->gunzip_buf)[i] =
+                       cpu_to_le32(((u32 *)bp->gunzip_buf)[i]);
+
+       bnx2x_write_big_buf_wb(bp, addr, len);
+}
+
+static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage)
+{
+       int hw_wr, i;
+       u16 op_start =
+               bp->init_ops_offsets[BLOCK_OPS_IDX(block,stage,STAGE_START)];
+       u16 op_end =
+               bp->init_ops_offsets[BLOCK_OPS_IDX(block,stage,STAGE_END)];
+       union init_op *op;
+       u32 op_type, addr, len;
+       const u32 *data, *data_base;
+
+       /* If empty block */
+       if (op_start == op_end)
+               return;
+
+       if (CHIP_REV_IS_FPGA(bp))
+               hw_wr = OP_WR_FPGA;
+       else if (CHIP_REV_IS_EMUL(bp))
+               hw_wr = OP_WR_EMUL;
+       else
+               hw_wr = OP_WR_ASIC;
+
+       data_base = bp->init_data;
+
+       for (i = op_start; i < op_end; i++) {
+
+               op = (union init_op *)&(bp->init_ops[i]);
+
+               op_type = op->str_wr.op;
+               addr = op->str_wr.offset;
+               len = op->str_wr.data_len;
+               data = data_base + op->str_wr.data_off;
+
+               /* HW/EMUL specific */
+               if (unlikely((op_type > OP_WB) && (op_type == hw_wr)))
+                       op_type = OP_WR;
+
+               switch (op_type) {
+               case OP_RD:
+                       REG_RD(bp, addr);
+                       break;
+               case OP_WR:
+                       REG_WR(bp, addr, op->write.val);
+                       break;
+               case OP_SW:
+                       bnx2x_init_str_wr(bp, addr, data, len);
+                       break;
+               case OP_WB:
+                       bnx2x_init_wr_wb(bp, addr, data, len);
+                       break;
+               case OP_SI:
+                       bnx2x_init_ind_wr(bp, addr, data, len);
+                       break;
+               case OP_ZR:
+                       bnx2x_init_fill(bp, addr, 0, op->zero.len);
+                       break;
+               case OP_ZP:
+                       bnx2x_init_wr_zp(bp, addr, len,
+                                        op->str_wr.data_off);
+                       break;
+               case OP_WR_64:
+                       bnx2x_init_wr_64(bp, addr, data, len);
+                       break;
+               default:
+                       /* happens whenever an op is of a diff HW */
+#if 0
+                       DP(NETIF_MSG_HW, "skipping init operation  "
+                          "index %d[%d:%d]: type %d  addr 0x%x  "
+                          "len %d(0x%x)\n",
+                          i, op_start, op_end, op_type, addr, len, len);
+#endif
+                       break;
+               }
+       }
+}
+
+/* PXP */
+static void bnx2x_init_pxp(struct bnx2x *bp)
+{
+       u16 devctl;
+       int r_order, w_order;
+       u32 val, i;
+
+       pci_read_config_word(bp->pdev,
+                            bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
+       DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
+       w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
+       if (bp->mrrs == -1)
+               r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
+       else {
+               DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
+               r_order = bp->mrrs;
+       }
+
+       if (r_order > MAX_RD_ORD) {
+               DP(NETIF_MSG_HW, "read order of %d  order adjusted to %d\n",
+                  r_order, MAX_RD_ORD);
+               r_order = MAX_RD_ORD;
+       }
+       if (w_order > MAX_WR_ORD) {
+               DP(NETIF_MSG_HW, "write order of %d  order adjusted to %d\n",
+                  w_order, MAX_WR_ORD);
+               w_order = MAX_WR_ORD;
+       }
+       if (CHIP_REV_IS_FPGA(bp)) {
+               DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
+               w_order = 0;
+       }
+       DP(NETIF_MSG_HW, "read order %d  write order %d\n", r_order, w_order);
+
+       for (i = 0; i < NUM_RD_Q-1; i++) {
+               REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l);
+               REG_WR(bp, read_arb_addr[i].add,
+                      read_arb_data[i][r_order].add);
+               REG_WR(bp, read_arb_addr[i].ubound,
+                      read_arb_data[i][r_order].ubound);
+       }
+
+       for (i = 0; i < NUM_WR_Q-1; i++) {
+               if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
+                   (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
+
+                       REG_WR(bp, write_arb_addr[i].l,
+                              write_arb_data[i][w_order].l);
+
+                       REG_WR(bp, write_arb_addr[i].add,
+                              write_arb_data[i][w_order].add);
+
+                       REG_WR(bp, write_arb_addr[i].ubound,
+                              write_arb_data[i][w_order].ubound);
+               } else {
+
+                       val = REG_RD(bp, write_arb_addr[i].l);
+                       REG_WR(bp, write_arb_addr[i].l,
+                              val | (write_arb_data[i][w_order].l << 10));
+
+                       val = REG_RD(bp, write_arb_addr[i].add);
+                       REG_WR(bp, write_arb_addr[i].add,
+                              val | (write_arb_data[i][w_order].add << 10));
+
+                       val = REG_RD(bp, write_arb_addr[i].ubound);
+                       REG_WR(bp, write_arb_addr[i].ubound,
+                              val | (write_arb_data[i][w_order].ubound << 7));
+               }
+       }
+
+       val =  write_arb_data[NUM_WR_Q-1][w_order].add;
+       val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
+       val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
+       REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val);
+
+       val =  read_arb_data[NUM_RD_Q-1][r_order].add;
+       val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
+       val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
+       REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val);
+
+       REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order);
+       REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order);
+       REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order);
+       REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order);
+
+       if (r_order == MAX_RD_ORD)
+               REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
+
+       REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
+
+       if (CHIP_IS_E1H(bp)) {
+               val = ((w_order == 0) ? 2 : 3);
+               REG_WR(bp, PXP2_REG_WR_HC_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_USDM_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_QM_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_TM_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_SRC_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_DBG_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */
+               REG_WR(bp, PXP2_REG_WR_CDU_MPS, val);
+       }
+}
+
+/*****************************************************************************
+ * Description:
+ *         Calculates crc 8 on a word value: polynomial 0-1-2-8
+ *         Code was translated from Verilog.
+ ****************************************************************************/
+static u8 calc_crc8(u32 data, u8 crc)
+{
+       u8 D[32];
+       u8 NewCRC[8];
+       u8 C[8];
+       u8 crc_res;
+       u8 i;
+
+       /* split the data into 31 bits */
+       for (i = 0; i < 32; i++) {
+               D[i] = data & 1;
+               data = data >> 1;
+       }
+
+       /* split the crc into 8 bits */
+       for (i = 0; i < 8; i++) {
+               C[i] = crc & 1;
+               crc = crc >> 1;
+       }
+
+       NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
+               D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
+               C[6] ^ C[7];
+       NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
+               D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
+               D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6];
+       NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
+               D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
+               C[0] ^ C[1] ^ C[4] ^ C[5];
+       NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
+               D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
+               C[1] ^ C[2] ^ C[5] ^ C[6];
+       NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
+               D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
+               C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
+       NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
+               D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
+               C[3] ^ C[4] ^ C[7];
+       NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
+               D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
+               C[5];
+       NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
+               D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
+               C[6];
+
+       crc_res = 0;
+       for (i = 0; i < 8; i++)
+               crc_res |= (NewCRC[i] << i);
+
+       return crc_res;
+}
+
+#endif /* BNX2X_INIT_OPS_H */
diff --git a/drivers/net/bnx2x_init_values.h b/drivers/net/bnx2x_init_values.h
deleted file mode 100644 (file)
index 1f22c9a..0000000
+++ /dev/null
@@ -1,16322 +0,0 @@
-#ifndef __BNX2X_INIT_VALUES_H__
-#define __BNX2X_INIT_VALUES_H__
-
-/* bnx2x_init_values.h: Broadcom NX2 10G network driver.
- *
- * Copyright (c) 2007-2009 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, except as noted below.
- *
- * This file contains firmware data derived from proprietary unpublished
- * source code, Copyright (c) 2007-2009 Broadcom Corporation.
- *
- * Permission is hereby granted for the distribution of this firmware data
- * in hexadecimal or equivalent format, provided this copyright notice is
- * accompanying it.
- *
- *
- * This array contains the list of operations needed to initialize the chip.
- *
- * For each block in the chip there are three init stages:
- * common - HW used by both ports,
- * port1 and port2 - initialization for a specific Ethernet port.
- * When a port is opened or closed, the management CPU tells the driver
- * whether to init/disable common HW in addition to the port HW.
- * This way the first port going up will first initializes the common HW,
- * and the last port going down also resets the common HW
- *
- * For each init stage/block there is a list of actions needed in a format:
- * {operation, register, data}
- * where:
- * OP_WR - write a value to the chip.
- * OP_RD - read a register (usually a clear on read register).
- * OP_SW - string write, write a section of consecutive addresses to the chip.
- * OP_SI - copy a string using indirect writes.
- * OP_ZR - clear a range of memory.
- * OP_ZP - unzip and copy using DMAE.
- * OP_WB - string copy using DMAE.
- *
- * The #defines mark the stages.
- *
- */
-
-static const struct raw_op init_ops[] = {
-#define PRS_COMMON_START        0
-       {OP_WR, PRS_REG_INC_VALUE, 0xf},
-       {OP_WR, PRS_REG_EVENT_ID_1, 0x45},
-       {OP_WR, PRS_REG_EVENT_ID_2, 0x84},
-       {OP_WR, PRS_REG_EVENT_ID_3, 0x6},
-       {OP_WR, PRS_REG_NO_MATCH_EVENT_ID, 0x4},
-       {OP_WR, PRS_REG_CM_HDR_TYPE_0, 0x0},
-       {OP_WR, PRS_REG_CM_HDR_TYPE_1, 0x12170000},
-       {OP_WR, PRS_REG_CM_HDR_TYPE_2, 0x22170000},
-       {OP_WR, PRS_REG_CM_HDR_TYPE_3, 0x32170000},
-       {OP_ZR, PRS_REG_CM_HDR_TYPE_4, 0x5},
-       {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_1, 0x12150000},
-       {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_2, 0x22150000},
-       {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_3, 0x32150000},
-       {OP_ZR, PRS_REG_CM_HDR_LOOPBACK_TYPE_4, 0x4},
-       {OP_WR, PRS_REG_CM_NO_MATCH_HDR, 0x2100000},
-       {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0, 0x100000},
-       {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0x10100000},
-       {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0x20100000},
-       {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0x30100000},
-       {OP_ZR_E1, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x4},
-       {OP_WR_E1H, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x40100000},
-       {OP_ZR_E1H, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5, 0x3},
-       {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0, 0x100000},
-       {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1, 0x12140000},
-       {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2, 0x22140000},
-       {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3, 0x32140000},
-       {OP_ZR_E1, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x4},
-       {OP_WR_E1H, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x42140000},
-       {OP_ZR_E1H, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5, 0x3},
-       {OP_RD, PRS_REG_NUM_OF_PACKETS, 0x0},
-       {OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0},
-       {OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0},
-       {OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0},
-       {OP_WR_E1H, PRS_REG_FCOE_TYPE, 0x8906},
-       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff},
-       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff},
-       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff},
-       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_3, 0xff},
-       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_4, 0xff},
-       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_5, 0xff},
-       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_6, 0xff},
-       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_7, 0xff},
-       {OP_WR, PRS_REG_PURE_REGIONS, 0x3e},
-       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_0, 0x0},
-       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_1, 0x3f},
-       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_2, 0x3f},
-       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_3, 0x3f},
-       {OP_WR_E1, PRS_REG_PACKET_REGIONS_TYPE_4, 0x0},
-       {OP_WR_E1H, PRS_REG_PACKET_REGIONS_TYPE_4, 0x3f},
-       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f},
-       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f},
-       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f},
-#define PRS_COMMON_END          52
-#define SRCH_COMMON_START       52
-       {OP_WR_E1H, SRC_REG_E1HMF_ENABLE, 0x1},
-#define SRCH_COMMON_END         53
-#define TSDM_COMMON_START       53
-       {OP_WR_E1, TSDM_REG_CFC_RSP_START_ADDR, 0x411},
-       {OP_WR_E1H, TSDM_REG_CFC_RSP_START_ADDR, 0x211},
-       {OP_WR_E1, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400},
-       {OP_WR_E1H, TSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
-       {OP_WR_E1, TSDM_REG_Q_COUNTER_START_ADDR, 0x404},
-       {OP_WR_E1H, TSDM_REG_Q_COUNTER_START_ADDR, 0x204},
-       {OP_WR_E1, TSDM_REG_PCK_END_MSG_START_ADDR, 0x419},
-       {OP_WR_E1H, TSDM_REG_PCK_END_MSG_START_ADDR, 0x219},
-       {OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff},
-       {OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff},
-       {OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff},
-       {OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff},
-       {OP_ZR_E1, TSDM_REG_AGG_INT_EVENT_0, 0x2},
-       {OP_WR_E1H, TSDM_REG_AGG_INT_EVENT_0, 0x20},
-       {OP_WR_E1H, TSDM_REG_AGG_INT_EVENT_1, 0x0},
-       {OP_WR, TSDM_REG_AGG_INT_EVENT_2, 0x34},
-       {OP_WR, TSDM_REG_AGG_INT_EVENT_3, 0x35},
-       {OP_ZR_E1, TSDM_REG_AGG_INT_EVENT_4, 0x7c},
-       {OP_ZR_E1H, TSDM_REG_AGG_INT_EVENT_4, 0x1c},
-       {OP_WR_E1H, TSDM_REG_AGG_INT_T_0, 0x1},
-       {OP_ZR_E1H, TSDM_REG_AGG_INT_T_1, 0x5f},
-       {OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff},
-       {OP_WR, TSDM_REG_ENABLE_IN2, 0x3f},
-       {OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff},
-       {OP_WR, TSDM_REG_ENABLE_OUT2, 0xf},
-       {OP_RD, TSDM_REG_NUM_OF_Q0_CMD, 0x0},
-       {OP_RD, TSDM_REG_NUM_OF_Q1_CMD, 0x0},
-       {OP_RD, TSDM_REG_NUM_OF_Q3_CMD, 0x0},
-       {OP_RD, TSDM_REG_NUM_OF_Q4_CMD, 0x0},
-       {OP_RD, TSDM_REG_NUM_OF_Q5_CMD, 0x0},
-       {OP_RD, TSDM_REG_NUM_OF_Q6_CMD, 0x0},
-       {OP_RD, TSDM_REG_NUM_OF_Q7_CMD, 0x0},
-       {OP_RD, TSDM_REG_NUM_OF_Q8_CMD, 0x0},
-       {OP_RD, TSDM_REG_NUM_OF_Q9_CMD, 0x0},
-       {OP_RD, TSDM_REG_NUM_OF_Q10_CMD, 0x0},
-       {OP_RD, TSDM_REG_NUM_OF_Q11_CMD, 0x0},
-       {OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
-       {OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
-       {OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
-       {OP_WR_E1, TSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
-       {OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8},
-       {OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1},
-       {OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa},
-#define TSDM_COMMON_END         96
-#define TCM_COMMON_START        96
-       {OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20},
-       {OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32},
-       {OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020},
-       {OP_WR, TCM_REG_TQM_TCM_HDR_S, 0x2150020},
-       {OP_WR, TCM_REG_TM_TCM_HDR, 0x30},
-       {OP_WR, TCM_REG_ERR_TCM_HDR, 0x8100000},
-       {OP_WR, TCM_REG_ERR_EVNT_ID, 0x33},
-       {OP_WR, TCM_REG_EXPR_EVNT_ID, 0x30},
-       {OP_WR, TCM_REG_STOP_EVNT_ID, 0x31},
-       {OP_WR, TCM_REG_STORM_WEIGHT, 0x2},
-       {OP_WR, TCM_REG_PRS_WEIGHT, 0x5},
-       {OP_WR, TCM_REG_PBF_WEIGHT, 0x6},
-       {OP_WR, TCM_REG_USEM_WEIGHT, 0x2},
-       {OP_WR, TCM_REG_CSEM_WEIGHT, 0x2},
-       {OP_WR, TCM_REG_CP_WEIGHT, 0x0},
-       {OP_WR, TCM_REG_TSDM_WEIGHT, 0x5},
-       {OP_WR, TCM_REG_TQM_P_WEIGHT, 0x2},
-       {OP_WR, TCM_REG_TQM_S_WEIGHT, 0x2},
-       {OP_WR, TCM_REG_TM_WEIGHT, 0x2},
-       {OP_WR, TCM_REG_TCM_TQM_USE_Q, 0x1},
-       {OP_WR, TCM_REG_GR_ARB_TYPE, 0x1},
-       {OP_WR, TCM_REG_GR_LD0_PR, 0x1},
-       {OP_WR, TCM_REG_GR_LD1_PR, 0x2},
-       {OP_WR, TCM_REG_CFC_INIT_CRD, 0x1},
-       {OP_WR, TCM_REG_FIC0_INIT_CRD, 0x40},
-       {OP_WR, TCM_REG_FIC1_INIT_CRD, 0x40},
-       {OP_WR, TCM_REG_TQM_INIT_CRD, 0x20},
-       {OP_WR, TCM_REG_XX_INIT_CRD, 0x13},
-       {OP_WR, TCM_REG_XX_MSG_NUM, 0x20},
-       {OP_ZR, TCM_REG_XX_TABLE, 0xa},
-       {OP_SW, TCM_REG_XX_DESCR_TABLE, 0x200000},
-       {OP_WR, TCM_REG_N_SM_CTX_LD_0, 0x7},
-       {OP_WR, TCM_REG_N_SM_CTX_LD_1, 0x7},
-       {OP_WR, TCM_REG_N_SM_CTX_LD_2, 0x8},
-       {OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8},
-       {OP_ZR_E1, TCM_REG_N_SM_CTX_LD_4, 0x4},
-       {OP_WR_E1H, TCM_REG_N_SM_CTX_LD_4, 0x1},
-       {OP_ZR_E1H, TCM_REG_N_SM_CTX_LD_5, 0x3},
-       {OP_WR, TCM_REG_TCM_REG0_SZ, 0x6},
-       {OP_WR_E1, TCM_REG_PHYS_QNUM0_0, 0xd},
-       {OP_WR_E1, TCM_REG_PHYS_QNUM0_1, 0x2d},
-       {OP_WR_E1, TCM_REG_PHYS_QNUM1_0, 0x7},
-       {OP_WR_E1, TCM_REG_PHYS_QNUM1_1, 0x27},
-       {OP_WR_E1, TCM_REG_PHYS_QNUM2_0, 0x7},
-       {OP_WR_E1, TCM_REG_PHYS_QNUM2_1, 0x27},
-       {OP_WR_E1, TCM_REG_PHYS_QNUM3_0, 0x7},
-       {OP_WR_E1, TCM_REG_PHYS_QNUM3_1, 0x27},
-       {OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1},
-       {OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1},
-       {OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1},
-       {OP_WR, TCM_REG_STORM_TCM_IFEN, 0x1},
-       {OP_WR, TCM_REG_TQM_TCM_IFEN, 0x1},
-       {OP_WR, TCM_REG_TSDM_IFEN, 0x1},
-       {OP_WR, TCM_REG_TM_TCM_IFEN, 0x1},
-       {OP_WR, TCM_REG_PRS_IFEN, 0x1},
-       {OP_WR, TCM_REG_PBF_IFEN, 0x1},
-       {OP_WR, TCM_REG_USEM_IFEN, 0x1},
-       {OP_WR, TCM_REG_CSEM_IFEN, 0x1},
-       {OP_WR, TCM_REG_CDU_AG_WR_IFEN, 0x1},
-       {OP_WR, TCM_REG_CDU_AG_RD_IFEN, 0x1},
-       {OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1},
-       {OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1},
-       {OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1},
-#define TCM_COMMON_END          159
-#define TCM_FUNC0_START         159
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0xd},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x7},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x7},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x7},
-#define TCM_FUNC0_END           163
-#define TCM_FUNC1_START         163
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x2d},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x27},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x27},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x27},
-#define TCM_FUNC1_END           167
-#define TCM_FUNC2_START         167
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x1d},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x17},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x17},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x17},
-#define TCM_FUNC2_END           171
-#define TCM_FUNC3_START         171
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x3d},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x37},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x37},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x37},
-#define TCM_FUNC3_END           175
-#define TCM_FUNC4_START         175
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x4d},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x47},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x47},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x47},
-#define TCM_FUNC4_END           179
-#define TCM_FUNC5_START         179
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x6d},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x67},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x67},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x67},
-#define TCM_FUNC5_END           183
-#define TCM_FUNC6_START         183
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x5d},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x57},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x57},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x57},
-#define TCM_FUNC6_END           187
-#define TCM_FUNC7_START         187
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x7d},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x77},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x77},
-       {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x77},
-#define TCM_FUNC7_END           191
-#define BRB1_COMMON_START       191
-       {OP_SW, BRB1_REG_LL_RAM, 0x2000020},
-       {OP_WR, BRB1_REG_SOFT_RESET, 0x1},
-       {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0},
-       {OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220},
-       {OP_WR, BRB1_REG_SOFT_RESET, 0x0},
-#define BRB1_COMMON_END         196
-#define BRB1_PORT0_START        196
-       {OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0xb8},
-       {OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 0x114},
-       {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0},
-       {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0},
-#define BRB1_PORT0_END          200
-#define BRB1_PORT1_START        200
-       {OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0xb8},
-       {OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 0x114},
-       {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0},
-       {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0},
-#define BRB1_PORT1_END          204
-#define TSEM_COMMON_START       204
-       {OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0},
-       {OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0},
-       {OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0},
-       {OP_RD, TSEM_REG_MSG_NUM_FOC1, 0x0},
-       {OP_RD, TSEM_REG_MSG_NUM_FOC2, 0x0},
-       {OP_RD, TSEM_REG_MSG_NUM_FOC3, 0x0},
-       {OP_WR, TSEM_REG_ARB_ELEMENT0, 0x1},
-       {OP_WR, TSEM_REG_ARB_ELEMENT1, 0x2},
-       {OP_WR, TSEM_REG_ARB_ELEMENT2, 0x3},
-       {OP_WR, TSEM_REG_ARB_ELEMENT3, 0x0},
-       {OP_WR, TSEM_REG_ARB_ELEMENT4, 0x4},
-       {OP_WR, TSEM_REG_ARB_CYCLE_SIZE, 0x1},
-       {OP_WR, TSEM_REG_TS_0_AS, 0x0},
-       {OP_WR, TSEM_REG_TS_1_AS, 0x1},
-       {OP_WR, TSEM_REG_TS_2_AS, 0x4},
-       {OP_WR, TSEM_REG_TS_3_AS, 0x0},
-       {OP_WR, TSEM_REG_TS_4_AS, 0x1},
-       {OP_WR, TSEM_REG_TS_5_AS, 0x3},
-       {OP_WR, TSEM_REG_TS_6_AS, 0x0},
-       {OP_WR, TSEM_REG_TS_7_AS, 0x1},
-       {OP_WR, TSEM_REG_TS_8_AS, 0x4},
-       {OP_WR, TSEM_REG_TS_9_AS, 0x0},
-       {OP_WR, TSEM_REG_TS_10_AS, 0x1},
-       {OP_WR, TSEM_REG_TS_11_AS, 0x3},
-       {OP_WR, TSEM_REG_TS_12_AS, 0x0},
-       {OP_WR, TSEM_REG_TS_13_AS, 0x1},
-       {OP_WR, TSEM_REG_TS_14_AS, 0x4},
-       {OP_WR, TSEM_REG_TS_15_AS, 0x0},
-       {OP_WR, TSEM_REG_TS_16_AS, 0x4},
-       {OP_WR, TSEM_REG_TS_17_AS, 0x3},
-       {OP_ZR, TSEM_REG_TS_18_AS, 0x2},
-       {OP_WR, TSEM_REG_ENABLE_IN, 0x3fff},
-       {OP_WR, TSEM_REG_ENABLE_OUT, 0x3ff},
-       {OP_WR, TSEM_REG_FIC0_DISABLE, 0x0},
-       {OP_WR, TSEM_REG_FIC1_DISABLE, 0x0},
-       {OP_WR, TSEM_REG_PAS_DISABLE, 0x0},
-       {OP_WR, TSEM_REG_THREADS_LIST, 0xff},
-       {OP_ZR, TSEM_REG_PASSIVE_BUFFER, 0x400},
-       {OP_WR, TSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
-       {OP_WR, TSEM_REG_FAST_MEMORY + 0x18000, 0x34},
-       {OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18},
-       {OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc},
-       {OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20},
-       {OP_WR_ASIC, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
-       {OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x18300, 0x138},
-       {OP_WR_FPGA, TSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
-       {OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2000, 0xb2},
-       {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x11480, 0x1},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x23c8, 0xc1},
-       {OP_WR_EMUL_E1H, TSEM_REG_FAST_MEMORY + 0x11480, 0x0},
-       {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x23c8 + 0x304, 0x10223},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x1000, 0x2b3},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x1000 + 0xacc, 0x10223},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1000, 0x2},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa020, 0xc8},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1c18, 0x4},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa000, 0x2},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1c10, 0x2},
-       {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x1ad0, 0x0},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x1ad8, 0x4},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3678, 0x6},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x810, 0x4},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3670, 0x2},
-       {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x40224},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
-       {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x4cb0, 0x80228},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5008, 0x4},
-       {OP_ZP_E1, TSEM_REG_INT_TABLE, 0x930000},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5018, 0x4},
-       {OP_WR_64_E1, TSEM_REG_INT_TABLE + 0x360, 0x140230},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5028, 0x4},
-       {OP_ZP_E1, TSEM_REG_PRAM, 0x324f0000},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5038, 0x4},
-       {OP_ZP_E1, TSEM_REG_PRAM + 0x8000, 0x33250c94},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5048, 0x4},
-       {OP_ZP_E1, TSEM_REG_PRAM + 0x10000, 0xe4d195e},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5058, 0x4},
-       {OP_WR_64_E1, TSEM_REG_PRAM + 0x11e00, 0x5c400232},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5068, 0x4},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5078, 0x2},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x62c0, 0x200224},
-       {OP_ZP_E1H, TSEM_REG_INT_TABLE, 0x9b0000},
-       {OP_WR_64_E1H, TSEM_REG_INT_TABLE + 0x398, 0xd0244},
-       {OP_ZP_E1H, TSEM_REG_PRAM, 0x325e0000},
-       {OP_ZP_E1H, TSEM_REG_PRAM + 0x8000, 0x35960c98},
-       {OP_ZP_E1H, TSEM_REG_PRAM + 0x10000, 0x1aea19fe},
-       {OP_WR_64_E1H, TSEM_REG_PRAM + 0x143d0, 0x57860246},
-#define TSEM_COMMON_END         297
-#define TSEM_PORT0_START        297
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x22c8, 0x20},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x2000, 0x16c},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x4000, 0x16c},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb000, 0x28},
-       {OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b60, 0x0},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb140, 0xc},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1400, 0xa},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32c0, 0x12},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1450, 0x6},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3350, 0x64},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1500, 0x2},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8108, 0x2},
-       {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1500 + 0x8, 0x50234},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1500 + 0x1c, 0x7},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1570, 0x12},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x9c0, 0x4c},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x820, 0xe},
-       {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x20239},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2908, 0x2},
-#define TSEM_PORT0_END          317
-#define TSEM_PORT1_START        317
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2348, 0x20},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x25b0, 0x16c},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x45b0, 0x16c},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb0a0, 0x28},
-       {OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b64, 0x0},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb170, 0xc},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1428, 0xa},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3308, 0x12},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1468, 0x6},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x34e0, 0x64},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1538, 0x2},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8110, 0x2},
-       {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1538 + 0x8, 0x5023b},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1538 + 0x1c, 0x7},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x15b8, 0x12},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0xaf0, 0x4c},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x858, 0xe},
-       {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb8, 0x20240},
-       {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2910, 0x2},
-#define TSEM_PORT1_END          337
-#define TSEM_FUNC0_START        337
-       {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b60, 0x0},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3000, 0x2},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3000 + 0x8, 0x50248},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3000 + 0x1c, 0x7},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31c0, 0x8},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5080, 0x12},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
-#define TSEM_FUNC0_END          345
-#define TSEM_FUNC1_START        345
-       {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b64, 0x0},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3038, 0x2},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3038 + 0x8, 0x5024d},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3038 + 0x1c, 0x7},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31e0, 0x8},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5010, 0x2},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x50c8, 0x12},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
-#define TSEM_FUNC1_END          353
-#define TSEM_FUNC2_START        353
-       {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b68, 0x0},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3070, 0x2},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3070 + 0x8, 0x50252},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3070 + 0x1c, 0x7},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3200, 0x8},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5020, 0x2},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5110, 0x12},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4010, 0x20257},
-#define TSEM_FUNC2_END          361
-#define TSEM_FUNC3_START        361
-       {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b6c, 0x0},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30a8, 0x2},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x30a8 + 0x8, 0x50259},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30a8 + 0x1c, 0x7},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3220, 0x8},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5030, 0x2},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5158, 0x12},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4018, 0x2025e},
-#define TSEM_FUNC3_END          369
-#define TSEM_FUNC4_START        369
-       {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b70, 0x0},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30e0, 0x2},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x30e0 + 0x8, 0x50260},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30e0 + 0x1c, 0x7},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3240, 0x8},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5040, 0x2},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51a0, 0x12},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4020, 0x20265},
-#define TSEM_FUNC4_END          377
-#define TSEM_FUNC5_START        377
-       {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b74, 0x0},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3118, 0x2},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3118 + 0x8, 0x50267},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3118 + 0x1c, 0x7},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3260, 0x8},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5050, 0x2},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51e8, 0x12},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4028, 0x2026c},
-#define TSEM_FUNC5_END          385
-#define TSEM_FUNC6_START        385
-       {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b78, 0x0},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3150, 0x2},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3150 + 0x8, 0x5026e},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3150 + 0x1c, 0x7},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3280, 0x8},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5060, 0x2},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5230, 0x12},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4030, 0x20273},
-#define TSEM_FUNC6_END          393
-#define TSEM_FUNC7_START        393
-       {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b7c, 0x0},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3188, 0x2},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3188 + 0x8, 0x50275},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3188 + 0x1c, 0x7},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32a0, 0x8},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5070, 0x2},
-       {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5278, 0x12},
-       {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4038, 0x2027a},
-#define TSEM_FUNC7_END          401
-#define MISC_COMMON_START       401
-       {OP_WR_E1, MISC_REG_GRC_TIMEOUT_EN, 0x1},
-       {OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911},
-       {OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0},
-       {OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424},
-       {OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0},
-       {OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209},
-       {OP_WR_E1, MISC_REG_SPIO, 0xff000000},
-#define MISC_COMMON_END         408
-#define MISC_FUNC0_START        408
-       {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
-#define MISC_FUNC0_END          409
-#define MISC_FUNC1_START        409
-       {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
-#define MISC_FUNC1_END          410
-#define MISC_FUNC2_START        410
-       {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
-#define MISC_FUNC2_END          411
-#define MISC_FUNC3_START        411
-       {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
-#define MISC_FUNC3_END          412
-#define MISC_FUNC4_START        412
-       {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
-#define MISC_FUNC4_END          413
-#define MISC_FUNC5_START        413
-       {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
-#define MISC_FUNC5_END          414
-#define MISC_FUNC6_START        414
-       {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
-#define MISC_FUNC6_END          415
-#define MISC_FUNC7_START        415
-       {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
-#define MISC_FUNC7_END          416
-#define NIG_COMMON_START        416
-       {OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1},
-       {OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1},
-       {OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1},
-       {OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1},
-       {OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1},
-#define NIG_COMMON_END          421
-#define NIG_PORT0_START         421
-       {OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000},
-       {OP_WR, NIG_REG_LLH0_EVENT_ID, 0x28},
-       {OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0},
-       {OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4},
-       {OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1},
-       {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0},
-       {OP_WR_E1H, NIG_REG_LLH0_CLS_TYPE, 0x1},
-       {OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30},
-       {OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1},
-       {OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1},
-       {OP_WR, NIG_REG_BRB0_OUT_EN, 0x1},
-       {OP_WR, NIG_REG_XCM0_OUT_EN, 0x1},
-#define NIG_PORT0_END           433
-#define NIG_PORT1_START         433
-       {OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000},
-       {OP_WR, NIG_REG_LLH1_EVENT_ID, 0x28},
-       {OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0},
-       {OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4},
-       {OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1},
-       {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0},
-       {OP_WR_E1H, NIG_REG_LLH1_CLS_TYPE, 0x1},
-       {OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30},
-       {OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1},
-       {OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1},
-       {OP_WR, NIG_REG_BRB1_OUT_EN, 0x1},
-       {OP_WR, NIG_REG_XCM1_OUT_EN, 0x1},
-#define NIG_PORT1_END           445
-#define UPB_COMMON_START        445
-       {OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20},
-#define UPB_COMMON_END          446
-#define CSDM_COMMON_START       446
-       {OP_WR_E1, CSDM_REG_CFC_RSP_START_ADDR, 0xa11},
-       {OP_WR_E1H, CSDM_REG_CFC_RSP_START_ADDR, 0x211},
-       {OP_WR_E1, CSDM_REG_CMP_COUNTER_START_ADDR, 0xa00},
-       {OP_WR_E1H, CSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
-       {OP_WR_E1, CSDM_REG_Q_COUNTER_START_ADDR, 0xa04},
-       {OP_WR_E1H, CSDM_REG_Q_COUNTER_START_ADDR, 0x204},
-       {OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff},
-       {OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff},
-       {OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff},
-       {OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff},
-       {OP_WR, CSDM_REG_AGG_INT_EVENT_0, 0xc6},
-       {OP_WR, CSDM_REG_AGG_INT_EVENT_1, 0x0},
-       {OP_WR, CSDM_REG_AGG_INT_EVENT_2, 0x34},
-       {OP_WR, CSDM_REG_AGG_INT_EVENT_3, 0x35},
-       {OP_ZR, CSDM_REG_AGG_INT_EVENT_4, 0x1c},
-       {OP_WR, CSDM_REG_AGG_INT_T_0, 0x1},
-       {OP_ZR, CSDM_REG_AGG_INT_T_1, 0x5f},
-       {OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff},
-       {OP_WR, CSDM_REG_ENABLE_IN2, 0x3f},
-       {OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff},
-       {OP_WR, CSDM_REG_ENABLE_OUT2, 0xf},
-       {OP_RD, CSDM_REG_NUM_OF_Q0_CMD, 0x0},
-       {OP_RD, CSDM_REG_NUM_OF_Q1_CMD, 0x0},
-       {OP_RD, CSDM_REG_NUM_OF_Q3_CMD, 0x0},
-       {OP_RD, CSDM_REG_NUM_OF_Q4_CMD, 0x0},
-       {OP_RD, CSDM_REG_NUM_OF_Q5_CMD, 0x0},
-       {OP_RD, CSDM_REG_NUM_OF_Q6_CMD, 0x0},
-       {OP_RD, CSDM_REG_NUM_OF_Q7_CMD, 0x0},
-       {OP_RD, CSDM_REG_NUM_OF_Q8_CMD, 0x0},
-       {OP_RD, CSDM_REG_NUM_OF_Q9_CMD, 0x0},
-       {OP_RD, CSDM_REG_NUM_OF_Q10_CMD, 0x0},
-       {OP_RD, CSDM_REG_NUM_OF_Q11_CMD, 0x0},
-       {OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
-       {OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
-       {OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
-       {OP_WR_E1, CSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
-       {OP_WR_ASIC, CSDM_REG_TIMER_TICK, 0x3e8},
-       {OP_WR_EMUL, CSDM_REG_TIMER_TICK, 0x1},
-       {OP_WR_FPGA, CSDM_REG_TIMER_TICK, 0xa},
-#define CSDM_COMMON_END         485
-#define USDM_COMMON_START       485
-       {OP_WR_E1, USDM_REG_CFC_RSP_START_ADDR, 0xa11},
-       {OP_WR_E1H, USDM_REG_CFC_RSP_START_ADDR, 0x411},
-       {OP_WR_E1, USDM_REG_CMP_COUNTER_START_ADDR, 0xa00},
-       {OP_WR_E1H, USDM_REG_CMP_COUNTER_START_ADDR, 0x400},
-       {OP_WR_E1, USDM_REG_Q_COUNTER_START_ADDR, 0xa04},
-       {OP_WR_E1H, USDM_REG_Q_COUNTER_START_ADDR, 0x404},
-       {OP_WR_E1, USDM_REG_PCK_END_MSG_START_ADDR, 0xa21},
-       {OP_WR_E1H, USDM_REG_PCK_END_MSG_START_ADDR, 0x421},
-       {OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff},
-       {OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff},
-       {OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff},
-       {OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff},
-       {OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46},
-       {OP_WR, USDM_REG_AGG_INT_EVENT_1, 0x5},
-       {OP_WR, USDM_REG_AGG_INT_EVENT_2, 0x34},
-       {OP_WR, USDM_REG_AGG_INT_EVENT_3, 0x35},
-       {OP_ZR_E1, USDM_REG_AGG_INT_EVENT_4, 0x5c},
-       {OP_WR_E1H, USDM_REG_AGG_INT_EVENT_4, 0x7},
-       {OP_ZR_E1H, USDM_REG_AGG_INT_EVENT_5, 0x5b},
-       {OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1},
-       {OP_ZR_E1, USDM_REG_AGG_INT_MODE_1, 0x1f},
-       {OP_ZR_E1H, USDM_REG_AGG_INT_MODE_1, 0x3},
-       {OP_WR_E1H, USDM_REG_AGG_INT_MODE_4, 0x1},
-       {OP_ZR_E1H, USDM_REG_AGG_INT_MODE_5, 0x1b},
-       {OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff},
-       {OP_WR, USDM_REG_ENABLE_IN2, 0x3f},
-       {OP_WR, USDM_REG_ENABLE_OUT1, 0x7ffffff},
-       {OP_WR, USDM_REG_ENABLE_OUT2, 0xf},
-       {OP_RD, USDM_REG_NUM_OF_Q0_CMD, 0x0},
-       {OP_RD, USDM_REG_NUM_OF_Q1_CMD, 0x0},
-       {OP_RD, USDM_REG_NUM_OF_Q2_CMD, 0x0},
-       {OP_RD, USDM_REG_NUM_OF_Q3_CMD, 0x0},
-       {OP_RD, USDM_REG_NUM_OF_Q4_CMD, 0x0},
-       {OP_RD, USDM_REG_NUM_OF_Q5_CMD, 0x0},
-       {OP_RD, USDM_REG_NUM_OF_Q6_CMD, 0x0},
-       {OP_RD, USDM_REG_NUM_OF_Q7_CMD, 0x0},
-       {OP_RD, USDM_REG_NUM_OF_Q8_CMD, 0x0},
-       {OP_RD, USDM_REG_NUM_OF_Q9_CMD, 0x0},
-       {OP_RD, USDM_REG_NUM_OF_Q10_CMD, 0x0},
-       {OP_RD, USDM_REG_NUM_OF_Q11_CMD, 0x0},
-       {OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0},
-       {OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
-       {OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
-       {OP_WR_E1, USDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
-       {OP_WR_ASIC, USDM_REG_TIMER_TICK, 0x3e8},
-       {OP_WR_EMUL, USDM_REG_TIMER_TICK, 0x1},
-       {OP_WR_FPGA, USDM_REG_TIMER_TICK, 0xa},
-#define USDM_COMMON_END         532
-#define CCM_COMMON_START        532
-       {OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32},
-       {OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020},
-       {OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020},
-       {OP_WR, CCM_REG_ERR_CCM_HDR, 0x8100000},
-       {OP_WR, CCM_REG_ERR_EVNT_ID, 0x33},
-       {OP_WR, CCM_REG_STORM_WEIGHT, 0x2},
-       {OP_WR, CCM_REG_TSEM_WEIGHT, 0x0},
-       {OP_WR, CCM_REG_XSEM_WEIGHT, 0x5},
-       {OP_WR, CCM_REG_USEM_WEIGHT, 0x5},
-       {OP_ZR, CCM_REG_PBF_WEIGHT, 0x2},
-       {OP_WR, CCM_REG_CSDM_WEIGHT, 0x2},
-       {OP_WR, CCM_REG_CQM_P_WEIGHT, 0x3},
-       {OP_WR, CCM_REG_CQM_S_WEIGHT, 0x2},
-       {OP_WR, CCM_REG_CCM_CQM_USE_Q, 0x1},
-       {OP_WR, CCM_REG_CNT_AUX1_Q, 0x2},
-       {OP_WR, CCM_REG_CNT_AUX2_Q, 0x2},
-       {OP_WR, CCM_REG_INV_DONE_Q, 0x1},
-       {OP_WR, CCM_REG_GR_ARB_TYPE, 0x1},
-       {OP_WR, CCM_REG_GR_LD0_PR, 0x1},
-       {OP_WR, CCM_REG_GR_LD1_PR, 0x2},
-       {OP_WR, CCM_REG_CFC_INIT_CRD, 0x1},
-       {OP_WR, CCM_REG_CQM_INIT_CRD, 0x20},
-       {OP_WR, CCM_REG_FIC0_INIT_CRD, 0x40},
-       {OP_WR, CCM_REG_FIC1_INIT_CRD, 0x40},
-       {OP_WR, CCM_REG_XX_INIT_CRD, 0x3},
-       {OP_WR, CCM_REG_XX_MSG_NUM, 0x18},
-       {OP_ZR, CCM_REG_XX_TABLE, 0x12},
-       {OP_SW_E1, CCM_REG_XX_DESCR_TABLE, 0x240242},
-       {OP_SW_E1H, CCM_REG_XX_DESCR_TABLE, 0x24027c},
-       {OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1},
-       {OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2},
-       {OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8},
-       {OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8},
-       {OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4},
-       {OP_WR, CCM_REG_CCM_REG0_SZ, 0x4},
-       {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
-       {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
-       {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
-       {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
-       {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM2_0, 0x7},
-       {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM2_1, 0x27},
-       {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM3_0, 0x7},
-       {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM3_1, 0x27},
-       {OP_WR_E1, CCM_REG_PHYS_QNUM1_0, 0xc},
-       {OP_WR_E1, CCM_REG_PHYS_QNUM1_1, 0x2c},
-       {OP_WR_E1, CCM_REG_PHYS_QNUM2_0, 0xc},
-       {OP_WR_E1, CCM_REG_PHYS_QNUM2_1, 0x2c},
-       {OP_WR_E1, CCM_REG_PHYS_QNUM3_0, 0xc},
-       {OP_WR_E1, CCM_REG_PHYS_QNUM3_1, 0x2c},
-       {OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1},
-       {OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1},
-       {OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1},
-       {OP_WR, CCM_REG_STORM_CCM_IFEN, 0x1},
-       {OP_WR, CCM_REG_CQM_CCM_IFEN, 0x1},
-       {OP_WR, CCM_REG_CSDM_IFEN, 0x1},
-       {OP_WR, CCM_REG_TSEM_IFEN, 0x1},
-       {OP_WR, CCM_REG_XSEM_IFEN, 0x1},
-       {OP_WR, CCM_REG_USEM_IFEN, 0x1},
-       {OP_WR, CCM_REG_PBF_IFEN, 0x1},
-       {OP_WR, CCM_REG_CDU_AG_WR_IFEN, 0x1},
-       {OP_WR, CCM_REG_CDU_AG_RD_IFEN, 0x1},
-       {OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1},
-       {OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1},
-       {OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1},
-#define CCM_COMMON_END          596
-#define CCM_FUNC0_START         596
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x7},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x7},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0xc},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0xb},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x7},
-#define CCM_FUNC0_END           603
-#define CCM_FUNC1_START         603
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x27},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x27},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x2c},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x2b},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x27},
-#define CCM_FUNC1_END           610
-#define CCM_FUNC2_START         610
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x19},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x1a},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x17},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x17},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x1c},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x1b},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x17},
-#define CCM_FUNC2_END           617
-#define CCM_FUNC3_START         617
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x39},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x3a},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x37},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x37},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x3c},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x3b},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x37},
-#define CCM_FUNC3_END           624
-#define CCM_FUNC4_START         624
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x49},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x4a},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x47},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x47},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x4c},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x4b},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x47},
-#define CCM_FUNC4_END           631
-#define CCM_FUNC5_START         631
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x69},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x6a},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x67},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x67},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x6c},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x6b},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x67},
-#define CCM_FUNC5_END           638
-#define CCM_FUNC6_START         638
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x59},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x5a},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x57},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x57},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x5c},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x5b},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x57},
-#define CCM_FUNC6_END           645
-#define CCM_FUNC7_START         645
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x79},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x7a},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x77},
-       {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x77},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x7c},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x7b},
-       {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x77},
-#define CCM_FUNC7_END           652
-#define UCM_COMMON_START        652
-       {OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32},
-       {OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020},
-       {OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020},
-       {OP_WR, UCM_REG_TM_UCM_HDR, 0x30},
-       {OP_WR, UCM_REG_ERR_UCM_HDR, 0x8100000},
-       {OP_WR, UCM_REG_ERR_EVNT_ID, 0x33},
-       {OP_WR, UCM_REG_EXPR_EVNT_ID, 0x30},
-       {OP_WR, UCM_REG_STOP_EVNT_ID, 0x31},
-       {OP_WR, UCM_REG_STORM_WEIGHT, 0x2},
-       {OP_WR, UCM_REG_TSEM_WEIGHT, 0x4},
-       {OP_WR, UCM_REG_CSEM_WEIGHT, 0x0},
-       {OP_WR, UCM_REG_XSEM_WEIGHT, 0x2},
-       {OP_WR, UCM_REG_DORQ_WEIGHT, 0x2},
-       {OP_WR, UCM_REG_CP_WEIGHT, 0x0},
-       {OP_WR, UCM_REG_USDM_WEIGHT, 0x2},
-       {OP_WR, UCM_REG_UQM_P_WEIGHT, 0x7},
-       {OP_WR, UCM_REG_UQM_S_WEIGHT, 0x2},
-       {OP_WR, UCM_REG_TM_WEIGHT, 0x2},
-       {OP_WR, UCM_REG_UCM_UQM_USE_Q, 0x1},
-       {OP_WR, UCM_REG_INV_CFLG_Q, 0x1},
-       {OP_WR, UCM_REG_GR_ARB_TYPE, 0x1},
-       {OP_WR, UCM_REG_GR_LD0_PR, 0x1},
-       {OP_WR, UCM_REG_GR_LD1_PR, 0x2},
-       {OP_WR, UCM_REG_CFC_INIT_CRD, 0x1},
-       {OP_WR, UCM_REG_FIC0_INIT_CRD, 0x40},
-       {OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40},
-       {OP_WR, UCM_REG_TM_INIT_CRD, 0x4},
-       {OP_WR, UCM_REG_UQM_INIT_CRD, 0x20},
-       {OP_WR, UCM_REG_XX_INIT_CRD, 0xe},
-       {OP_WR, UCM_REG_XX_MSG_NUM, 0x1b},
-       {OP_ZR, UCM_REG_XX_TABLE, 0x12},
-       {OP_SW_E1, UCM_REG_XX_DESCR_TABLE, 0x1b0266},
-       {OP_SW_E1H, UCM_REG_XX_DESCR_TABLE, 0x1b02a0},
-       {OP_WR, UCM_REG_N_SM_CTX_LD_0, 0x10},
-       {OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x7},
-       {OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf},
-       {OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10},
-       {OP_ZR_E1, UCM_REG_N_SM_CTX_LD_4, 0x4},
-       {OP_WR_E1H, UCM_REG_N_SM_CTX_LD_4, 0xb},
-       {OP_ZR_E1H, UCM_REG_N_SM_CTX_LD_5, 0x3},
-       {OP_WR, UCM_REG_UCM_REG0_SZ, 0x3},
-       {OP_WR_E1, UCM_REG_PHYS_QNUM0_0, 0xf},
-       {OP_WR_E1, UCM_REG_PHYS_QNUM0_1, 0x2f},
-       {OP_WR_E1, UCM_REG_PHYS_QNUM1_0, 0xe},
-       {OP_WR_E1, UCM_REG_PHYS_QNUM1_1, 0x2e},
-       {OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1},
-       {OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1},
-       {OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1},
-       {OP_WR, UCM_REG_STORM_UCM_IFEN, 0x1},
-       {OP_WR, UCM_REG_UQM_UCM_IFEN, 0x1},
-       {OP_WR, UCM_REG_USDM_IFEN, 0x1},
-       {OP_WR, UCM_REG_TM_UCM_IFEN, 0x1},
-       {OP_WR, UCM_REG_UCM_TM_IFEN, 0x1},
-       {OP_WR, UCM_REG_TSEM_IFEN, 0x1},
-       {OP_WR, UCM_REG_CSEM_IFEN, 0x1},
-       {OP_WR, UCM_REG_XSEM_IFEN, 0x1},
-       {OP_WR, UCM_REG_DORQ_IFEN, 0x1},
-       {OP_WR, UCM_REG_CDU_AG_WR_IFEN, 0x1},
-       {OP_WR, UCM_REG_CDU_AG_RD_IFEN, 0x1},
-       {OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1},
-       {OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1},
-       {OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1},
-#define UCM_COMMON_END          714
-#define UCM_FUNC0_START         714
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0xf},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0xe},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
-#define UCM_FUNC0_END           718
-#define UCM_FUNC1_START         718
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x2f},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x2e},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
-#define UCM_FUNC1_END           722
-#define UCM_FUNC2_START         722
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x1f},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x1e},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
-#define UCM_FUNC2_END           726
-#define UCM_FUNC3_START         726
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x3f},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x3e},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
-#define UCM_FUNC3_END           730
-#define UCM_FUNC4_START         730
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x4f},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x4e},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
-#define UCM_FUNC4_END           734
-#define UCM_FUNC5_START         734
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x6f},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x6e},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
-#define UCM_FUNC5_END           738
-#define UCM_FUNC6_START         738
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x5f},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x5e},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
-#define UCM_FUNC6_END           742
-#define UCM_FUNC7_START         742
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x7f},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x7e},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
-       {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
-#define UCM_FUNC7_END           746
-#define USEM_COMMON_START       746
-       {OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0},
-       {OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0},
-       {OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0},
-       {OP_RD, USEM_REG_MSG_NUM_FOC1, 0x0},
-       {OP_RD, USEM_REG_MSG_NUM_FOC2, 0x0},
-       {OP_RD, USEM_REG_MSG_NUM_FOC3, 0x0},
-       {OP_WR, USEM_REG_ARB_ELEMENT0, 0x1},
-       {OP_WR, USEM_REG_ARB_ELEMENT1, 0x2},
-       {OP_WR, USEM_REG_ARB_ELEMENT2, 0x3},
-       {OP_WR, USEM_REG_ARB_ELEMENT3, 0x0},
-       {OP_WR, USEM_REG_ARB_ELEMENT4, 0x4},
-       {OP_WR, USEM_REG_ARB_CYCLE_SIZE, 0x1},
-       {OP_WR, USEM_REG_TS_0_AS, 0x0},
-       {OP_WR, USEM_REG_TS_1_AS, 0x1},
-       {OP_WR, USEM_REG_TS_2_AS, 0x4},
-       {OP_WR, USEM_REG_TS_3_AS, 0x0},
-       {OP_WR, USEM_REG_TS_4_AS, 0x1},
-       {OP_WR, USEM_REG_TS_5_AS, 0x3},
-       {OP_WR, USEM_REG_TS_6_AS, 0x0},
-       {OP_WR, USEM_REG_TS_7_AS, 0x1},
-       {OP_WR, USEM_REG_TS_8_AS, 0x4},
-       {OP_WR, USEM_REG_TS_9_AS, 0x0},
-       {OP_WR, USEM_REG_TS_10_AS, 0x1},
-       {OP_WR, USEM_REG_TS_11_AS, 0x3},
-       {OP_WR, USEM_REG_TS_12_AS, 0x0},
-       {OP_WR, USEM_REG_TS_13_AS, 0x1},
-       {OP_WR, USEM_REG_TS_14_AS, 0x4},
-       {OP_WR, USEM_REG_TS_15_AS, 0x0},
-       {OP_WR, USEM_REG_TS_16_AS, 0x4},
-       {OP_WR, USEM_REG_TS_17_AS, 0x3},
-       {OP_ZR, USEM_REG_TS_18_AS, 0x2},
-       {OP_WR, USEM_REG_ENABLE_IN, 0x3fff},
-       {OP_WR, USEM_REG_ENABLE_OUT, 0x3ff},
-       {OP_WR, USEM_REG_FIC0_DISABLE, 0x0},
-       {OP_WR, USEM_REG_FIC1_DISABLE, 0x0},
-       {OP_WR, USEM_REG_PAS_DISABLE, 0x0},
-       {OP_WR, USEM_REG_THREADS_LIST, 0xffff},
-       {OP_ZR, USEM_REG_PASSIVE_BUFFER, 0x800},
-       {OP_WR, USEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
-       {OP_WR, USEM_REG_FAST_MEMORY + 0x18000, 0x1a},
-       {OP_WR, USEM_REG_FAST_MEMORY + 0x18040, 0x4e},
-       {OP_WR, USEM_REG_FAST_MEMORY + 0x18080, 0x10},
-       {OP_WR, USEM_REG_FAST_MEMORY + 0x180c0, 0x20},
-       {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
-       {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18300, 0x138},
-       {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18300, 0x1388},
-       {OP_WR, USEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
-       {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
-       {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
-       {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5000, 0xc2},
-       {OP_WR_EMUL_E1H, USEM_REG_FAST_MEMORY + 0x11480, 0x0},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1020, 0xc8},
-       {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x11480, 0x1},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1000, 0x2},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x2000, 0x102},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4640, 0x40},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8980, 0xc8},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x57f0, 0x4},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8960, 0x2},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x57d8, 0x5},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3228, 0x4},
-       {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x57d8 + 0x14, 0x10281},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3200, 0x9},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1c60, 0x20},
-       {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x3200 + 0x24, 0x102bb},
-       {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2830, 0x20282},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3180, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x400},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4000, 0x2},
-       {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x4000 + 0x8, 0x102bc},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4000 + 0xc, 0x3},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b68, 0x2},
-       {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x202bd},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b10, 0x2},
-       {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x74c0, 0x202bf},
-       {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
-       {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c00, 0x100284},
-       {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c00, 0x1002c1},
-       {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0},
-       {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c40, 0x100294},
-       {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002d1},
-       {OP_ZP_E1, USEM_REG_INT_TABLE, 0xc30000},
-       {OP_ZP_E1H, USEM_REG_INT_TABLE, 0xd20000},
-       {OP_WR_64_E1, USEM_REG_INT_TABLE + 0x368, 0x1302a4},
-       {OP_WR_64_E1H, USEM_REG_INT_TABLE + 0x3a8, 0xb02e1},
-       {OP_ZP_E1, USEM_REG_PRAM, 0x314c0000},
-       {OP_ZP_E1H, USEM_REG_PRAM, 0x31b60000},
-       {OP_ZP_E1, USEM_REG_PRAM + 0x8000, 0x35ef0c53},
-       {OP_ZP_E1H, USEM_REG_PRAM + 0x8000, 0x36500c6e},
-       {OP_ZP_E1, USEM_REG_PRAM + 0x10000, 0x361319cf},
-       {OP_ZP_E1H, USEM_REG_PRAM + 0x10000, 0x37591a02},
-       {OP_ZP_E1, USEM_REG_PRAM + 0x18000, 0x7112754},
-       {OP_ZP_E1H, USEM_REG_PRAM + 0x18000, 0x286127d9},
-       {OP_WR_64_E1, USEM_REG_PRAM + 0x18ee0, 0x4e2402a6},
-       {OP_WR_64_E1H, USEM_REG_PRAM + 0x1ff40, 0x401802e3},
-#define USEM_COMMON_END         842
-#define USEM_PORT0_START        842
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1400, 0xa0},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9000, 0xa0},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1900, 0x10},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9500, 0x40},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1980, 0x30},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9700, 0x3c},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4740, 0xb4},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x2450, 0xb4},
-       {OP_WR_E1, USEM_REG_FAST_MEMORY + 0x1d90, 0x0},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x2ad0, 0x2},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1b40, 0x4},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3080, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1b60, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8000, 0x12c},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5318, 0x98},
-       {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x3238, 0x0},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5100, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5200, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5300, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5400, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5500, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5600, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5700, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5800, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5900, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a00, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b00, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c00, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d00, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e00, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f00, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b78, 0x52},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e08, 0xc},
-#define USEM_PORT0_END          876
-#define USEM_PORT1_START        876
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1680, 0xa0},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9280, 0xa0},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1940, 0x10},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9600, 0x40},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1a40, 0x30},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x97f0, 0x3c},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4a10, 0xb4},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x2720, 0xb4},
-       {OP_WR_E1, USEM_REG_FAST_MEMORY + 0x1d94, 0x0},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x2ad8, 0x2},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1b50, 0x4},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3100, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1be0, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x84b0, 0x12c},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5578, 0x98},
-       {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x323c, 0x0},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5080, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5180, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5280, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5380, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5480, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5580, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5680, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5780, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5880, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5980, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a80, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b80, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c80, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d80, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e80, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f80, 0x20},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6cc0, 0x52},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e38, 0xc},
-#define USEM_PORT1_END          910
-#define USEM_FUNC0_START        910
-       {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x2a30, 0x0},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3000, 0x4},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4018, 0x2},
-#define USEM_FUNC0_END          913
-#define USEM_FUNC1_START        913
-       {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x2a34, 0x0},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3010, 0x4},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4028, 0x2},
-#define USEM_FUNC1_END          916
-#define USEM_FUNC2_START        916
-       {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x2a38, 0x0},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3020, 0x4},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4038, 0x2},
-#define USEM_FUNC2_END          919
-#define USEM_FUNC3_START        919
-       {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x2a3c, 0x0},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3030, 0x4},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4048, 0x2},
-#define USEM_FUNC3_END          922
-#define USEM_FUNC4_START        922
-       {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x2a40, 0x0},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3040, 0x4},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4058, 0x2},
-#define USEM_FUNC4_END          925
-#define USEM_FUNC5_START        925
-       {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x2a44, 0x0},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3050, 0x4},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4068, 0x2},
-#define USEM_FUNC5_END          928
-#define USEM_FUNC6_START        928
-       {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x2a48, 0x0},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3060, 0x4},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4078, 0x2},
-#define USEM_FUNC6_END          931
-#define USEM_FUNC7_START        931
-       {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x2a4c, 0x0},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3070, 0x4},
-       {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4088, 0x2},
-#define USEM_FUNC7_END          934
-#define CSEM_COMMON_START       934
-       {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0},
-       {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0},
-       {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0},
-       {OP_RD, CSEM_REG_MSG_NUM_FOC1, 0x0},
-       {OP_RD, CSEM_REG_MSG_NUM_FOC2, 0x0},
-       {OP_RD, CSEM_REG_MSG_NUM_FOC3, 0x0},
-       {OP_WR, CSEM_REG_ARB_ELEMENT0, 0x1},
-       {OP_WR, CSEM_REG_ARB_ELEMENT1, 0x2},
-       {OP_WR, CSEM_REG_ARB_ELEMENT2, 0x3},
-       {OP_WR, CSEM_REG_ARB_ELEMENT3, 0x0},
-       {OP_WR, CSEM_REG_ARB_ELEMENT4, 0x4},
-       {OP_WR, CSEM_REG_ARB_CYCLE_SIZE, 0x1},
-       {OP_WR, CSEM_REG_TS_0_AS, 0x0},
-       {OP_WR, CSEM_REG_TS_1_AS, 0x1},
-       {OP_WR, CSEM_REG_TS_2_AS, 0x4},
-       {OP_WR, CSEM_REG_TS_3_AS, 0x0},
-       {OP_WR, CSEM_REG_TS_4_AS, 0x1},
-       {OP_WR, CSEM_REG_TS_5_AS, 0x3},
-       {OP_WR, CSEM_REG_TS_6_AS, 0x0},
-       {OP_WR, CSEM_REG_TS_7_AS, 0x1},
-       {OP_WR, CSEM_REG_TS_8_AS, 0x4},
-       {OP_WR, CSEM_REG_TS_9_AS, 0x0},
-       {OP_WR, CSEM_REG_TS_10_AS, 0x1},
-       {OP_WR, CSEM_REG_TS_11_AS, 0x3},
-       {OP_WR, CSEM_REG_TS_12_AS, 0x0},
-       {OP_WR, CSEM_REG_TS_13_AS, 0x1},
-       {OP_WR, CSEM_REG_TS_14_AS, 0x4},
-       {OP_WR, CSEM_REG_TS_15_AS, 0x0},
-       {OP_WR, CSEM_REG_TS_16_AS, 0x4},
-       {OP_WR, CSEM_REG_TS_17_AS, 0x3},
-       {OP_ZR, CSEM_REG_TS_18_AS, 0x2},
-       {OP_WR, CSEM_REG_ENABLE_IN, 0x3fff},
-       {OP_WR, CSEM_REG_ENABLE_OUT, 0x3ff},
-       {OP_WR, CSEM_REG_FIC0_DISABLE, 0x0},
-       {OP_WR, CSEM_REG_FIC1_DISABLE, 0x0},
-       {OP_WR, CSEM_REG_PAS_DISABLE, 0x0},
-       {OP_WR, CSEM_REG_THREADS_LIST, 0xffff},
-       {OP_ZR, CSEM_REG_PASSIVE_BUFFER, 0x800},
-       {OP_WR, CSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
-       {OP_WR, CSEM_REG_FAST_MEMORY + 0x18000, 0x10},
-       {OP_WR, CSEM_REG_FAST_MEMORY + 0x18040, 0x12},
-       {OP_WR, CSEM_REG_FAST_MEMORY + 0x18080, 0x30},
-       {OP_WR, CSEM_REG_FAST_MEMORY + 0x180c0, 0xe},
-       {OP_WR, CSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x5000, 0x42},
-       {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x11480, 0x1},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
-       {OP_WR_EMUL_E1H, CSEM_REG_FAST_MEMORY + 0x11480, 0x0},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1000, 0x2},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x1000, 0x42},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2000, 0xc0},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x7020, 0xc8},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3070, 0x80},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x7000, 0x2},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x4280, 0x4},
-       {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x11e8, 0x0},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3000, 0xc0},
-       {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802a8},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4070, 0x80},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x5280, 0x4},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6700, 0x100},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x9000, 0x400},
-       {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x6b08, 0x2002e5},
-       {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff},
-       {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002b0},
-       {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c00, 0x100305},
-       {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0},
-       {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002c0},
-       {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c40, 0x100315},
-       {OP_ZP_E1, CSEM_REG_INT_TABLE, 0x710000},
-       {OP_ZP_E1H, CSEM_REG_INT_TABLE, 0x740000},
-       {OP_WR_64_E1, CSEM_REG_INT_TABLE + 0x380, 0x1002d0},
-       {OP_WR_64_E1H, CSEM_REG_INT_TABLE + 0x380, 0x100325},
-       {OP_ZP_E1, CSEM_REG_PRAM, 0x32290000},
-       {OP_ZP_E1H, CSEM_REG_PRAM, 0x32260000},
-       {OP_ZP_E1, CSEM_REG_PRAM + 0x8000, 0x23630c8b},
-       {OP_ZP_E1H, CSEM_REG_PRAM + 0x8000, 0x246e0c8a},
-       {OP_WR_64_E1, CSEM_REG_PRAM + 0xc930, 0x654002d2},
-       {OP_WR_64_E1H, CSEM_REG_PRAM + 0xcbb0, 0x64f00327},
-#define CSEM_COMMON_END         1014
-#define CSEM_PORT0_START        1014
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1400, 0xa0},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8000, 0xa0},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1900, 0x10},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8500, 0x40},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1980, 0x30},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8700, 0x3c},
-       {OP_WR_E1, CSEM_REG_FAST_MEMORY + 0x5118, 0x0},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4040, 0x6},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2300, 0xe},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3040, 0x6},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2410, 0x30},
-#define CSEM_PORT0_END          1025
-#define CSEM_PORT1_START        1025
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1680, 0xa0},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8280, 0xa0},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1940, 0x10},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8600, 0x40},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1a40, 0x30},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x87f0, 0x3c},
-       {OP_WR_E1, CSEM_REG_FAST_MEMORY + 0x511c, 0x0},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4058, 0x6},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2338, 0xe},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3058, 0x6},
-       {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30},
-#define CSEM_PORT1_END          1036
-#define CSEM_FUNC0_START        1036
-       {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1148, 0x0},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3300, 0x2},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6040, 0x30},
-#define CSEM_FUNC0_END          1039
-#define CSEM_FUNC1_START        1039
-       {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x114c, 0x0},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3308, 0x2},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6100, 0x30},
-#define CSEM_FUNC1_END          1042
-#define CSEM_FUNC2_START        1042
-       {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1150, 0x0},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3310, 0x2},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x61c0, 0x30},
-#define CSEM_FUNC2_END          1045
-#define CSEM_FUNC3_START        1045
-       {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1154, 0x0},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3318, 0x2},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6280, 0x30},
-#define CSEM_FUNC3_END          1048
-#define CSEM_FUNC4_START        1048
-       {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1158, 0x0},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3320, 0x2},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6340, 0x30},
-#define CSEM_FUNC4_END          1051
-#define CSEM_FUNC5_START        1051
-       {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x115c, 0x0},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3328, 0x2},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6400, 0x30},
-#define CSEM_FUNC5_END          1054
-#define CSEM_FUNC6_START        1054
-       {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1160, 0x0},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3330, 0x2},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x64c0, 0x30},
-#define CSEM_FUNC6_END          1057
-#define CSEM_FUNC7_START        1057
-       {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1164, 0x0},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3338, 0x2},
-       {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6580, 0x30},
-#define CSEM_FUNC7_END          1060
-#define XPB_COMMON_START        1060
-       {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x20},
-#define XPB_COMMON_END          1061
-#define DQ_COMMON_START         1061
-       {OP_WR, DORQ_REG_MODE_ACT, 0x2},
-       {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3},
-       {OP_WR, DORQ_REG_OUTST_REQ, 0x4},
-       {OP_WR, DORQ_REG_DPM_CID_ADDR, 0x8},
-       {OP_WR, DORQ_REG_RSP_INIT_CRD, 0x2},
-       {OP_WR, DORQ_REG_NORM_CMHEAD_TX, 0x90},
-       {OP_WR, DORQ_REG_CMHEAD_RX, 0x90},
-       {OP_WR, DORQ_REG_SHRT_CMHEAD, 0x800090},
-       {OP_WR, DORQ_REG_ERR_CMHEAD, 0x8140000},
-       {OP_WR, DORQ_REG_AGG_CMD0, 0x8a},
-       {OP_WR, DORQ_REG_AGG_CMD1, 0x80},
-       {OP_WR, DORQ_REG_AGG_CMD2, 0x90},
-       {OP_WR, DORQ_REG_AGG_CMD3, 0x80},
-       {OP_WR, DORQ_REG_SHRT_ACT_CNT, 0x6},
-       {OP_WR, DORQ_REG_DQ_FIFO_FULL_TH, 0x7d0},
-       {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c},
-       {OP_WR, DORQ_REG_REGN, 0x7c1004},
-       {OP_WR, DORQ_REG_IF_EN, 0xf},
-#define DQ_COMMON_END           1079
-#define TIMERS_COMMON_START     1079
-       {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2},
-       {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c},
-       {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1},
-       {OP_WR, TM_REG_CFC_CLD_CRDCNT_VAL, 0x1},
-       {OP_WR, TM_REG_CLOUT_CRDCNT0_VAL, 0x1},
-       {OP_WR, TM_REG_CLOUT_CRDCNT1_VAL, 0x1},
-       {OP_WR, TM_REG_CLOUT_CRDCNT2_VAL, 0x1},
-       {OP_WR, TM_REG_EXP_CRDCNT_VAL, 0x1},
-       {OP_WR_E1, TM_REG_PCIARB_CRDCNT_VAL, 0x1},
-       {OP_WR_E1H, TM_REG_PCIARB_CRDCNT_VAL, 0x2},
-       {OP_WR_ASIC, TM_REG_TIMER_TICK_SIZE, 0x3d090},
-       {OP_WR_EMUL, TM_REG_TIMER_TICK_SIZE, 0x9c},
-       {OP_WR_FPGA, TM_REG_TIMER_TICK_SIZE, 0x9c4},
-       {OP_WR, TM_REG_CL0_CONT_REGION, 0x8},
-       {OP_WR, TM_REG_CL1_CONT_REGION, 0xc},
-       {OP_WR, TM_REG_CL2_CONT_REGION, 0x10},
-       {OP_WR, TM_REG_TM_CONTEXT_REGION, 0x20},
-       {OP_WR, TM_REG_EN_TIMERS, 0x1},
-       {OP_WR, TM_REG_EN_REAL_TIME_CNT, 0x1},
-       {OP_WR, TM_REG_EN_CL0_INPUT, 0x1},
-       {OP_WR, TM_REG_EN_CL1_INPUT, 0x1},
-       {OP_WR, TM_REG_EN_CL2_INPUT, 0x1},
-#define TIMERS_COMMON_END       1101
-#define TIMERS_PORT0_START      1101
-       {OP_WR, TM_REG_LIN0_LOGIC_ADDR, 0x0},
-       {OP_WR, TM_REG_LIN0_PHY_ADDR_VALID, 0x0},
-       {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2},
-#define TIMERS_PORT0_END        1104
-#define TIMERS_PORT1_START      1104
-       {OP_WR, TM_REG_LIN1_LOGIC_ADDR, 0x0},
-       {OP_WR, TM_REG_LIN1_PHY_ADDR_VALID, 0x0},
-       {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2},
-#define TIMERS_PORT1_END        1107
-#define XSDM_COMMON_START       1107
-       {OP_WR_E1, XSDM_REG_CFC_RSP_START_ADDR, 0x614},
-       {OP_WR_E1H, XSDM_REG_CFC_RSP_START_ADDR, 0x424},
-       {OP_WR_E1, XSDM_REG_CMP_COUNTER_START_ADDR, 0x600},
-       {OP_WR_E1H, XSDM_REG_CMP_COUNTER_START_ADDR, 0x410},
-       {OP_WR_E1, XSDM_REG_Q_COUNTER_START_ADDR, 0x604},
-       {OP_WR_E1H, XSDM_REG_Q_COUNTER_START_ADDR, 0x414},
-       {OP_WR, XSDM_REG_CMP_COUNTER_MAX0, 0xffff},
-       {OP_WR, XSDM_REG_CMP_COUNTER_MAX1, 0xffff},
-       {OP_WR, XSDM_REG_CMP_COUNTER_MAX2, 0xffff},
-       {OP_WR, XSDM_REG_CMP_COUNTER_MAX3, 0xffff},
-       {OP_WR, XSDM_REG_AGG_INT_EVENT_0, 0x20},
-       {OP_WR, XSDM_REG_AGG_INT_EVENT_1, 0x20},
-       {OP_WR, XSDM_REG_AGG_INT_EVENT_2, 0x34},
-       {OP_WR, XSDM_REG_AGG_INT_EVENT_3, 0x35},
-       {OP_WR, XSDM_REG_AGG_INT_EVENT_4, 0x23},
-       {OP_WR, XSDM_REG_AGG_INT_EVENT_5, 0x24},
-       {OP_WR, XSDM_REG_AGG_INT_EVENT_6, 0x25},
-       {OP_WR, XSDM_REG_AGG_INT_EVENT_7, 0x26},
-       {OP_WR, XSDM_REG_AGG_INT_EVENT_8, 0x27},
-       {OP_WR, XSDM_REG_AGG_INT_EVENT_9, 0x29},
-       {OP_WR, XSDM_REG_AGG_INT_EVENT_10, 0x2a},
-       {OP_WR, XSDM_REG_AGG_INT_EVENT_11, 0x2b},
-       {OP_WR, XSDM_REG_AGG_INT_EVENT_12, 0x2c},
-       {OP_WR, XSDM_REG_AGG_INT_EVENT_13, 0x2d},
-       {OP_ZR, XSDM_REG_AGG_INT_EVENT_14, 0x52},
-       {OP_WR, XSDM_REG_AGG_INT_MODE_0, 0x1},
-       {OP_ZR, XSDM_REG_AGG_INT_MODE_1, 0x1f},
-       {OP_WR, XSDM_REG_ENABLE_IN1, 0x7ffffff},
-       {OP_WR, XSDM_REG_ENABLE_IN2, 0x3f},
-       {OP_WR, XSDM_REG_ENABLE_OUT1, 0x7ffffff},
-       {OP_WR, XSDM_REG_ENABLE_OUT2, 0xf},
-       {OP_RD, XSDM_REG_NUM_OF_Q0_CMD, 0x0},
-       {OP_RD, XSDM_REG_NUM_OF_Q1_CMD, 0x0},
-       {OP_RD, XSDM_REG_NUM_OF_Q3_CMD, 0x0},
-       {OP_RD, XSDM_REG_NUM_OF_Q4_CMD, 0x0},
-       {OP_RD, XSDM_REG_NUM_OF_Q5_CMD, 0x0},
-       {OP_RD, XSDM_REG_NUM_OF_Q6_CMD, 0x0},
-       {OP_RD, XSDM_REG_NUM_OF_Q7_CMD, 0x0},
-       {OP_RD, XSDM_REG_NUM_OF_Q8_CMD, 0x0},
-       {OP_RD, XSDM_REG_NUM_OF_Q9_CMD, 0x0},
-       {OP_RD, XSDM_REG_NUM_OF_Q10_CMD, 0x0},
-       {OP_RD, XSDM_REG_NUM_OF_Q11_CMD, 0x0},
-       {OP_RD, XSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
-       {OP_RD, XSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
-       {OP_RD, XSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
-       {OP_WR_E1, XSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
-       {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8},
-       {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1},
-       {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa},
-#define XSDM_COMMON_END         1156
-#define QM_COMMON_START         1156
-       {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6},
-       {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5},
-       {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa},
-       {OP_WR, QM_REG_ACTCTRINITVAL_3, 0x5},
-       {OP_WR, QM_REG_PCIREQAT, 0x2},
-       {OP_WR, QM_REG_CMINITCRD_0, 0x4},
-       {OP_WR, QM_REG_CMINITCRD_1, 0x4},
-       {OP_WR, QM_REG_CMINITCRD_2, 0x4},
-       {OP_WR, QM_REG_CMINITCRD_3, 0x4},
-       {OP_WR, QM_REG_CMINITCRD_4, 0x4},
-       {OP_WR, QM_REG_CMINITCRD_5, 0x4},
-       {OP_WR, QM_REG_CMINITCRD_6, 0x4},
-       {OP_WR, QM_REG_CMINITCRD_7, 0x4},
-       {OP_WR, QM_REG_OUTLDREQ, 0x4},
-       {OP_WR, QM_REG_CTXREG_0, 0x7c},
-       {OP_WR, QM_REG_CTXREG_1, 0x3d},
-       {OP_WR, QM_REG_CTXREG_2, 0x3f},
-       {OP_WR, QM_REG_CTXREG_3, 0x9c},
-       {OP_WR, QM_REG_ENSEC, 0x7},
-       {OP_ZR, QM_REG_QVOQIDX_0, 0x5},
-       {OP_WR, QM_REG_WRRWEIGHTS_0, 0x1010101},
-       {OP_WR, QM_REG_QVOQIDX_5, 0x0},
-       {OP_WR, QM_REG_QVOQIDX_6, 0x4},
-       {OP_WR, QM_REG_QVOQIDX_7, 0x4},
-       {OP_WR, QM_REG_QVOQIDX_8, 0x2},
-       {OP_WR, QM_REG_WRRWEIGHTS_1, 0x8012004},
-       {OP_WR, QM_REG_QVOQIDX_9, 0x5},
-       {OP_WR, QM_REG_QVOQIDX_10, 0x5},
-       {OP_WR, QM_REG_QVOQIDX_11, 0x5},
-       {OP_WR, QM_REG_QVOQIDX_12, 0x5},
-       {OP_WR, QM_REG_WRRWEIGHTS_2, 0x20081001},
-       {OP_WR, QM_REG_QVOQIDX_13, 0x8},
-       {OP_WR, QM_REG_QVOQIDX_14, 0x6},
-       {OP_WR, QM_REG_QVOQIDX_15, 0x7},
-       {OP_WR, QM_REG_QVOQIDX_16, 0x0},
-       {OP_WR, QM_REG_WRRWEIGHTS_3, 0x1010120},
-       {OP_ZR, QM_REG_QVOQIDX_17, 0x4},
-       {OP_WR, QM_REG_WRRWEIGHTS_4, 0x1010101},
-       {OP_ZR_E1, QM_REG_QVOQIDX_21, 0x4},
-       {OP_WR_E1H, QM_REG_QVOQIDX_21, 0x0},
-       {OP_WR_E1, QM_REG_WRRWEIGHTS_5, 0x1010101},
-       {OP_WR_E1H, QM_REG_QVOQIDX_22, 0x4},
-       {OP_ZR_E1, QM_REG_QVOQIDX_25, 0x4},
-       {OP_WR_E1H, QM_REG_QVOQIDX_23, 0x4},
-       {OP_WR_E1, QM_REG_WRRWEIGHTS_6, 0x1010101},
-       {OP_WR_E1H, QM_REG_QVOQIDX_24, 0x2},
-       {OP_ZR_E1, QM_REG_QVOQIDX_29, 0x3},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_5, 0x8012004},
-       {OP_WR_E1H, QM_REG_QVOQIDX_25, 0x5},
-       {OP_WR_E1H, QM_REG_QVOQIDX_26, 0x5},
-       {OP_WR_E1H, QM_REG_QVOQIDX_27, 0x5},
-       {OP_WR_E1H, QM_REG_QVOQIDX_28, 0x5},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_6, 0x20081001},
-       {OP_WR_E1H, QM_REG_QVOQIDX_29, 0x8},
-       {OP_WR_E1H, QM_REG_QVOQIDX_30, 0x6},
-       {OP_WR_E1H, QM_REG_QVOQIDX_31, 0x7},
-       {OP_WR, QM_REG_QVOQIDX_32, 0x1},
-       {OP_WR_E1, QM_REG_WRRWEIGHTS_7, 0x1010101},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_7, 0x1010120},
-       {OP_WR, QM_REG_QVOQIDX_33, 0x1},
-       {OP_WR, QM_REG_QVOQIDX_34, 0x1},
-       {OP_WR, QM_REG_QVOQIDX_35, 0x1},
-       {OP_WR, QM_REG_QVOQIDX_36, 0x1},
-       {OP_WR, QM_REG_WRRWEIGHTS_8, 0x1010101},
-       {OP_WR, QM_REG_QVOQIDX_37, 0x1},
-       {OP_WR, QM_REG_QVOQIDX_38, 0x4},
-       {OP_WR, QM_REG_QVOQIDX_39, 0x4},
-       {OP_WR, QM_REG_QVOQIDX_40, 0x2},
-       {OP_WR, QM_REG_WRRWEIGHTS_9, 0x8012004},
-       {OP_WR, QM_REG_QVOQIDX_41, 0x5},
-       {OP_WR, QM_REG_QVOQIDX_42, 0x5},
-       {OP_WR, QM_REG_QVOQIDX_43, 0x5},
-       {OP_WR, QM_REG_QVOQIDX_44, 0x5},
-       {OP_WR, QM_REG_WRRWEIGHTS_10, 0x20081001},
-       {OP_WR, QM_REG_QVOQIDX_45, 0x8},
-       {OP_WR, QM_REG_QVOQIDX_46, 0x6},
-       {OP_WR, QM_REG_QVOQIDX_47, 0x7},
-       {OP_WR, QM_REG_QVOQIDX_48, 0x1},
-       {OP_WR, QM_REG_WRRWEIGHTS_11, 0x1010120},
-       {OP_WR, QM_REG_QVOQIDX_49, 0x1},
-       {OP_WR, QM_REG_QVOQIDX_50, 0x1},
-       {OP_WR, QM_REG_QVOQIDX_51, 0x1},
-       {OP_WR, QM_REG_QVOQIDX_52, 0x1},
-       {OP_WR, QM_REG_WRRWEIGHTS_12, 0x1010101},
-       {OP_WR, QM_REG_QVOQIDX_53, 0x1},
-       {OP_WR_E1, QM_REG_QVOQIDX_54, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_54, 0x4},
-       {OP_WR_E1, QM_REG_QVOQIDX_55, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_55, 0x4},
-       {OP_WR_E1, QM_REG_QVOQIDX_56, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_56, 0x2},
-       {OP_WR_E1, QM_REG_WRRWEIGHTS_13, 0x1010101},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_13, 0x8012004},
-       {OP_WR_E1, QM_REG_QVOQIDX_57, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_57, 0x5},
-       {OP_WR_E1, QM_REG_QVOQIDX_58, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_58, 0x5},
-       {OP_WR_E1, QM_REG_QVOQIDX_59, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_59, 0x5},
-       {OP_WR_E1, QM_REG_QVOQIDX_60, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_60, 0x5},
-       {OP_WR_E1, QM_REG_WRRWEIGHTS_14, 0x1010101},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_14, 0x20081001},
-       {OP_WR_E1, QM_REG_QVOQIDX_61, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_61, 0x8},
-       {OP_WR_E1, QM_REG_QVOQIDX_62, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_62, 0x6},
-       {OP_WR_E1, QM_REG_QVOQIDX_63, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_63, 0x7},
-       {OP_WR_E1, QM_REG_WRRWEIGHTS_15, 0x1010101},
-       {OP_WR_E1H, QM_REG_QVOQIDX_64, 0x0},
-       {OP_WR_E1, QM_REG_VOQQMASK_0_LSB, 0xffff003f},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_15, 0x1010120},
-       {OP_ZR_E1, QM_REG_VOQQMASK_0_MSB, 0x2},
-       {OP_ZR_E1H, QM_REG_QVOQIDX_65, 0x4},
-       {OP_WR_E1, QM_REG_VOQQMASK_1_MSB, 0xffff003f},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_16, 0x1010101},
-       {OP_WR_E1, QM_REG_VOQQMASK_2_LSB, 0x100},
-       {OP_WR_E1H, QM_REG_QVOQIDX_69, 0x0},
-       {OP_WR_E1, QM_REG_VOQQMASK_2_MSB, 0x100},
-       {OP_WR_E1H, QM_REG_QVOQIDX_70, 0x4},
-       {OP_WR_E1H, QM_REG_QVOQIDX_71, 0x4},
-       {OP_WR_E1H, QM_REG_QVOQIDX_72, 0x2},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_17, 0x8012004},
-       {OP_WR_E1H, QM_REG_QVOQIDX_73, 0x5},
-       {OP_WR_E1H, QM_REG_QVOQIDX_74, 0x5},
-       {OP_WR_E1H, QM_REG_QVOQIDX_75, 0x5},
-       {OP_WR_E1H, QM_REG_QVOQIDX_76, 0x5},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_18, 0x20081001},
-       {OP_WR_E1H, QM_REG_QVOQIDX_77, 0x8},
-       {OP_WR_E1H, QM_REG_QVOQIDX_78, 0x6},
-       {OP_WR_E1H, QM_REG_QVOQIDX_79, 0x7},
-       {OP_WR_E1H, QM_REG_QVOQIDX_80, 0x0},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_19, 0x1010120},
-       {OP_ZR_E1H, QM_REG_QVOQIDX_81, 0x4},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_20, 0x1010101},
-       {OP_WR_E1H, QM_REG_QVOQIDX_85, 0x0},
-       {OP_WR_E1H, QM_REG_QVOQIDX_86, 0x4},
-       {OP_WR_E1H, QM_REG_QVOQIDX_87, 0x4},
-       {OP_WR_E1H, QM_REG_QVOQIDX_88, 0x2},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_21, 0x8012004},
-       {OP_WR_E1H, QM_REG_QVOQIDX_89, 0x5},
-       {OP_WR_E1H, QM_REG_QVOQIDX_90, 0x5},
-       {OP_WR_E1H, QM_REG_QVOQIDX_91, 0x5},
-       {OP_WR_E1H, QM_REG_QVOQIDX_92, 0x5},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_22, 0x20081001},
-       {OP_WR_E1H, QM_REG_QVOQIDX_93, 0x8},
-       {OP_WR_E1H, QM_REG_QVOQIDX_94, 0x6},
-       {OP_WR_E1H, QM_REG_QVOQIDX_95, 0x7},
-       {OP_WR_E1H, QM_REG_QVOQIDX_96, 0x1},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_23, 0x1010120},
-       {OP_WR_E1H, QM_REG_QVOQIDX_97, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_98, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_99, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_100, 0x1},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_24, 0x1010101},
-       {OP_WR_E1H, QM_REG_QVOQIDX_101, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_102, 0x4},
-       {OP_WR_E1H, QM_REG_QVOQIDX_103, 0x4},
-       {OP_WR_E1H, QM_REG_QVOQIDX_104, 0x2},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_25, 0x8012004},
-       {OP_WR_E1H, QM_REG_QVOQIDX_105, 0x5},
-       {OP_WR_E1H, QM_REG_QVOQIDX_106, 0x5},
-       {OP_WR_E1H, QM_REG_QVOQIDX_107, 0x5},
-       {OP_WR_E1H, QM_REG_QVOQIDX_108, 0x5},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_26, 0x20081001},
-       {OP_WR_E1H, QM_REG_QVOQIDX_109, 0x8},
-       {OP_WR_E1H, QM_REG_QVOQIDX_110, 0x6},
-       {OP_WR_E1H, QM_REG_QVOQIDX_111, 0x7},
-       {OP_WR_E1H, QM_REG_QVOQIDX_112, 0x1},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_27, 0x1010120},
-       {OP_WR_E1H, QM_REG_QVOQIDX_113, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_114, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_115, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_116, 0x1},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_28, 0x1010101},
-       {OP_WR_E1H, QM_REG_QVOQIDX_117, 0x1},
-       {OP_WR_E1H, QM_REG_QVOQIDX_118, 0x4},
-       {OP_WR_E1H, QM_REG_QVOQIDX_119, 0x4},
-       {OP_WR_E1H, QM_REG_QVOQIDX_120, 0x2},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_29, 0x8012004},
-       {OP_WR_E1H, QM_REG_QVOQIDX_121, 0x5},
-       {OP_WR_E1H, QM_REG_QVOQIDX_122, 0x5},
-       {OP_WR_E1H, QM_REG_QVOQIDX_123, 0x5},
-       {OP_WR_E1H, QM_REG_QVOQIDX_124, 0x5},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_30, 0x20081001},
-       {OP_WR_E1H, QM_REG_QVOQIDX_125, 0x8},
-       {OP_WR_E1H, QM_REG_QVOQIDX_126, 0x6},
-       {OP_WR_E1H, QM_REG_QVOQIDX_127, 0x7},
-       {OP_WR_E1H, QM_REG_WRRWEIGHTS_31, 0x1010120},
-       {OP_WR_E1H, QM_REG_VOQQMASK_0_LSB, 0x3f003f},
-       {OP_WR_E1H, QM_REG_VOQQMASK_0_MSB, 0x0},
-       {OP_WR_E1H, QM_REG_VOQQMASK_0_LSB_EXT_A, 0x3f003f},
-       {OP_WR_E1H, QM_REG_VOQQMASK_0_MSB_EXT_A, 0x0},
-       {OP_WR_E1H, QM_REG_VOQQMASK_1_LSB, 0x0},
-       {OP_WR_E1H, QM_REG_VOQQMASK_1_MSB, 0x3f003f},
-       {OP_WR_E1H, QM_REG_VOQQMASK_1_LSB_EXT_A, 0x0},
-       {OP_WR_E1H, QM_REG_VOQQMASK_1_MSB_EXT_A, 0x3f003f},
-       {OP_WR_E1H, QM_REG_VOQQMASK_2_LSB, 0x1000100},
-       {OP_WR_E1H, QM_REG_VOQQMASK_2_MSB, 0x1000100},
-       {OP_WR_E1H, QM_REG_VOQQMASK_2_LSB_EXT_A, 0x1000100},
-       {OP_WR_E1H, QM_REG_VOQQMASK_2_MSB_EXT_A, 0x1000100},
-       {OP_ZR, QM_REG_VOQQMASK_3_LSB, 0x2},
-       {OP_WR_E1, QM_REG_VOQQMASK_4_LSB, 0xc0},
-       {OP_WR_E1H, QM_REG_VOQQMASK_3_LSB_EXT_A, 0x0},
-       {OP_WR_E1, QM_REG_VOQQMASK_4_MSB, 0xc0},
-       {OP_WR_E1H, QM_REG_VOQQMASK_3_MSB_EXT_A, 0x0},
-       {OP_WR_E1, QM_REG_VOQQMASK_5_LSB, 0x1e00},
-       {OP_WR_E1H, QM_REG_VOQQMASK_4_LSB, 0xc000c0},
-       {OP_WR_E1, QM_REG_VOQQMASK_5_MSB, 0x1e00},
-       {OP_WR_E1H, QM_REG_VOQQMASK_4_MSB, 0xc000c0},
-       {OP_WR_E1, QM_REG_VOQQMASK_6_LSB, 0x4000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_4_LSB_EXT_A, 0xc000c0},
-       {OP_WR_E1, QM_REG_VOQQMASK_6_MSB, 0x4000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_4_MSB_EXT_A, 0xc000c0},
-       {OP_WR_E1, QM_REG_VOQQMASK_7_LSB, 0x8000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_5_LSB, 0x1e001e00},
-       {OP_WR_E1, QM_REG_VOQQMASK_7_MSB, 0x8000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_5_MSB, 0x1e001e00},
-       {OP_WR_E1, QM_REG_VOQQMASK_8_LSB, 0x2000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_5_LSB_EXT_A, 0x1e001e00},
-       {OP_WR_E1, QM_REG_VOQQMASK_8_MSB, 0x2000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_5_MSB_EXT_A, 0x1e001e00},
-       {OP_ZR_E1, QM_REG_VOQQMASK_9_LSB, 0x7},
-       {OP_WR_E1H, QM_REG_VOQQMASK_6_LSB, 0x40004000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_6_MSB, 0x40004000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_6_LSB_EXT_A, 0x40004000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_6_MSB_EXT_A, 0x40004000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_7_LSB, 0x80008000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_7_MSB, 0x80008000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_7_LSB_EXT_A, 0x80008000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_7_MSB_EXT_A, 0x80008000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_8_LSB, 0x20002000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_8_MSB, 0x20002000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_8_LSB_EXT_A, 0x20002000},
-       {OP_WR_E1H, QM_REG_VOQQMASK_8_MSB_EXT_A, 0x20002000},
-       {OP_ZR_E1H, QM_REG_VOQQMASK_9_LSB, 0x2},
-       {OP_WR_E1H, QM_REG_VOQQMASK_9_LSB_EXT_A, 0x0},
-       {OP_WR_E1H, QM_REG_VOQQMASK_9_MSB_EXT_A, 0x0},
-       {OP_WR_E1H, QM_REG_VOQQMASK_10_LSB, 0x0},
-       {OP_WR_E1H, QM_REG_VOQQMASK_10_MSB, 0x0},
-       {OP_WR_E1H, QM_REG_VOQQMASK_10_LSB_EXT_A, 0x0},
-       {OP_WR_E1H, QM_REG_VOQQMASK_10_MSB_EXT_A, 0x0},
-       {OP_WR_E1H, QM_REG_VOQQMASK_11_LSB, 0x0},
-       {OP_WR_E1H, QM_REG_VOQQMASK_11_MSB, 0x0},
-       {OP_WR_E1H, QM_REG_VOQQMASK_11_LSB_EXT_A, 0x0},
-       {OP_WR_E1H, QM_REG_VOQQMASK_11_MSB_EXT_A, 0x0},
-       {OP_WR_E1H, QM_REG_VOQPORT_0, 0x0},
-       {OP_WR, QM_REG_VOQPORT_1, 0x1},
-       {OP_ZR, QM_REG_VOQPORT_2, 0xa},
-       {OP_WR, QM_REG_CMINTVOQMASK_0, 0xc08},
-       {OP_WR, QM_REG_CMINTVOQMASK_1, 0x40},
-       {OP_WR, QM_REG_CMINTVOQMASK_2, 0x100},
-       {OP_WR, QM_REG_CMINTVOQMASK_3, 0x20},
-       {OP_WR, QM_REG_CMINTVOQMASK_4, 0x17},
-       {OP_WR, QM_REG_CMINTVOQMASK_5, 0x80},
-       {OP_WR, QM_REG_CMINTVOQMASK_6, 0x200},
-       {OP_WR, QM_REG_CMINTVOQMASK_7, 0x0},
-       {OP_WR_E1, QM_REG_HWAEMPTYMASK_LSB, 0xffff01ff},
-       {OP_WR_E1H, QM_REG_HWAEMPTYMASK_LSB, 0x1ff01ff},
-       {OP_WR_E1, QM_REG_HWAEMPTYMASK_MSB, 0xffff01ff},
-       {OP_WR_E1H, QM_REG_HWAEMPTYMASK_MSB, 0x1ff01ff},
-       {OP_WR_E1H, QM_REG_HWAEMPTYMASK_LSB_EXT_A, 0x1ff01ff},
-       {OP_WR_E1H, QM_REG_HWAEMPTYMASK_MSB_EXT_A, 0x1ff01ff},
-       {OP_WR, QM_REG_ENBYPVOQMASK, 0x13},
-       {OP_WR, QM_REG_VOQCREDITAFULLTHR, 0x13f},
-       {OP_WR, QM_REG_VOQINITCREDIT_0, 0x140},
-       {OP_WR, QM_REG_VOQINITCREDIT_1, 0x140},
-       {OP_ZR, QM_REG_VOQINITCREDIT_2, 0x2},
-       {OP_WR, QM_REG_VOQINITCREDIT_4, 0xc0},
-       {OP_ZR, QM_REG_VOQINITCREDIT_5, 0x7},
-       {OP_WR, QM_REG_TASKCRDCOST_0, 0x48},
-       {OP_WR, QM_REG_TASKCRDCOST_1, 0x48},
-       {OP_ZR, QM_REG_TASKCRDCOST_2, 0x2},
-       {OP_WR, QM_REG_TASKCRDCOST_4, 0x48},
-       {OP_ZR, QM_REG_TASKCRDCOST_5, 0x7},
-       {OP_WR, QM_REG_BYTECRDINITVAL, 0x8000},
-       {OP_WR, QM_REG_BYTECRDCOST, 0x25e4},
-       {OP_WR, QM_REG_BYTECREDITAFULLTHR, 0x7fff},
-       {OP_WR_E1, QM_REG_ENBYTECRD_LSB, 0x7},
-       {OP_WR_E1H, QM_REG_ENBYTECRD_LSB, 0x70007},
-       {OP_WR_E1, QM_REG_ENBYTECRD_MSB, 0x7},
-       {OP_WR_E1H, QM_REG_ENBYTECRD_MSB, 0x70007},
-       {OP_WR_E1H, QM_REG_ENBYTECRD_LSB_EXT_A, 0x70007},
-       {OP_WR_E1H, QM_REG_ENBYTECRD_MSB_EXT_A, 0x70007},
-       {OP_WR, QM_REG_BYTECRDPORT_LSB, 0x0},
-       {OP_WR, QM_REG_BYTECRDPORT_MSB, 0xffffffff},
-       {OP_WR_E1, QM_REG_FUNCNUMSEL_LSB, 0x0},
-       {OP_WR_E1H, QM_REG_BYTECRDPORT_LSB_EXT_A, 0x0},
-       {OP_WR_E1, QM_REG_FUNCNUMSEL_MSB, 0xffffffff},
-       {OP_WR_E1H, QM_REG_BYTECRDPORT_MSB_EXT_A, 0xffffffff},
-       {OP_WR_E1H, QM_REG_PQ2PCIFUNC_0, 0x0},
-       {OP_WR_E1H, QM_REG_PQ2PCIFUNC_1, 0x2},
-       {OP_WR_E1H, QM_REG_PQ2PCIFUNC_2, 0x1},
-       {OP_WR_E1H, QM_REG_PQ2PCIFUNC_3, 0x3},
-       {OP_WR_E1H, QM_REG_PQ2PCIFUNC_4, 0x4},
-       {OP_WR_E1H, QM_REG_PQ2PCIFUNC_5, 0x6},
-       {OP_WR_E1H, QM_REG_PQ2PCIFUNC_6, 0x5},
-       {OP_WR_E1H, QM_REG_PQ2PCIFUNC_7, 0x7},
-       {OP_WR, QM_REG_CMINTEN, 0xff},
-#define QM_COMMON_END           1456
-#define PBF_COMMON_START        1456
-       {OP_WR, PBF_REG_INIT, 0x1},
-       {OP_WR, PBF_REG_INIT_P4, 0x1},
-       {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1},
-       {OP_WR, PBF_REG_IF_ENABLE_REG, 0x7fff},
-       {OP_WR, PBF_REG_INIT_P4, 0x0},
-       {OP_WR, PBF_REG_INIT, 0x0},
-       {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0},
-#define PBF_COMMON_END          1463
-#define PBF_PORT0_START         1463
-       {OP_WR, PBF_REG_INIT_P0, 0x1},
-       {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1},
-       {OP_WR, PBF_REG_INIT_P0, 0x0},
-       {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0},
-#define PBF_PORT0_END           1467
-#define PBF_PORT1_START         1467
-       {OP_WR, PBF_REG_INIT_P1, 0x1},
-       {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1},
-       {OP_WR, PBF_REG_INIT_P1, 0x0},
-       {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0},
-#define PBF_PORT1_END           1471
-#define XCM_COMMON_START        1471
-       {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32},
-       {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020},
-       {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020},
-       {OP_WR, XCM_REG_TM_XCM_HDR, 0x1000030},
-       {OP_WR, XCM_REG_ERR_XCM_HDR, 0x8100000},
-       {OP_WR, XCM_REG_ERR_EVNT_ID, 0x33},
-       {OP_WR, XCM_REG_EXPR_EVNT_ID, 0x30},
-       {OP_WR, XCM_REG_STOP_EVNT_ID, 0x31},
-       {OP_WR, XCM_REG_STORM_WEIGHT, 0x3},
-       {OP_WR, XCM_REG_TSEM_WEIGHT, 0x6},
-       {OP_WR, XCM_REG_CSEM_WEIGHT, 0x3},
-       {OP_WR, XCM_REG_USEM_WEIGHT, 0x3},
-       {OP_WR, XCM_REG_DORQ_WEIGHT, 0x2},
-       {OP_WR, XCM_REG_PBF_WEIGHT, 0x0},
-       {OP_WR, XCM_REG_NIG0_WEIGHT, 0x2},
-       {OP_WR, XCM_REG_CP_WEIGHT, 0x0},
-       {OP_WR, XCM_REG_XSDM_WEIGHT, 0x6},
-       {OP_WR, XCM_REG_XQM_P_WEIGHT, 0x4},
-       {OP_WR, XCM_REG_XQM_S_WEIGHT, 0x2},
-       {OP_WR, XCM_REG_TM_WEIGHT, 0x2},
-       {OP_WR, XCM_REG_XCM_XQM_USE_Q, 0x1},
-       {OP_WR, XCM_REG_XQM_BYP_ACT_UPD, 0x6},
-       {OP_WR, XCM_REG_UNA_GT_NXT_Q, 0x0},
-       {OP_WR, XCM_REG_AUX1_Q, 0x2},
-       {OP_WR, XCM_REG_AUX_CNT_FLG_Q_19, 0x1},
-       {OP_WR, XCM_REG_GR_ARB_TYPE, 0x1},
-       {OP_WR, XCM_REG_GR_LD0_PR, 0x1},
-       {OP_WR, XCM_REG_GR_LD1_PR, 0x2},
-       {OP_WR, XCM_REG_CFC_INIT_CRD, 0x1},
-       {OP_WR, XCM_REG_FIC0_INIT_CRD, 0x40},
-       {OP_WR, XCM_REG_FIC1_INIT_CRD, 0x40},
-       {OP_WR, XCM_REG_TM_INIT_CRD, 0x4},
-       {OP_WR, XCM_REG_XQM_INIT_CRD, 0x20},
-       {OP_WR, XCM_REG_XX_INIT_CRD, 0x2},
-       {OP_WR_E1, XCM_REG_XX_MSG_NUM, 0x1f},
-       {OP_WR_E1H, XCM_REG_XX_MSG_NUM, 0x20},
-       {OP_ZR, XCM_REG_XX_TABLE, 0x12},
-       {OP_SW_E1, XCM_REG_XX_DESCR_TABLE, 0x1f02d4},
-       {OP_SW_E1H, XCM_REG_XX_DESCR_TABLE, 0x1f0329},
-       {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf},
-       {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7},
-       {OP_WR, XCM_REG_N_SM_CTX_LD_2, 0xb},
-       {OP_WR, XCM_REG_N_SM_CTX_LD_3, 0xe},
-       {OP_ZR_E1, XCM_REG_N_SM_CTX_LD_4, 0x4},
-       {OP_WR_E1H, XCM_REG_N_SM_CTX_LD_4, 0xe},
-       {OP_ZR_E1H, XCM_REG_N_SM_CTX_LD_5, 0x3},
-       {OP_WR, XCM_REG_XCM_REG0_SZ, 0x4},
-       {OP_WR, XCM_REG_XCM_STORM0_IFEN, 0x1},
-       {OP_WR, XCM_REG_XCM_STORM1_IFEN, 0x1},
-       {OP_WR, XCM_REG_XCM_XQM_IFEN, 0x1},
-       {OP_WR, XCM_REG_STORM_XCM_IFEN, 0x1},
-       {OP_WR, XCM_REG_XQM_XCM_IFEN, 0x1},
-       {OP_WR, XCM_REG_XSDM_IFEN, 0x1},
-       {OP_WR, XCM_REG_TM_XCM_IFEN, 0x1},
-       {OP_WR, XCM_REG_XCM_TM_IFEN, 0x1},
-       {OP_WR, XCM_REG_TSEM_IFEN, 0x1},
-       {OP_WR, XCM_REG_CSEM_IFEN, 0x1},
-       {OP_WR, XCM_REG_USEM_IFEN, 0x1},
-       {OP_WR, XCM_REG_DORQ_IFEN, 0x1},
-       {OP_WR, XCM_REG_PBF_IFEN, 0x1},
-       {OP_WR, XCM_REG_NIG0_IFEN, 0x1},
-       {OP_WR, XCM_REG_NIG1_IFEN, 0x1},
-       {OP_WR, XCM_REG_CDU_AG_WR_IFEN, 0x1},
-       {OP_WR, XCM_REG_CDU_AG_RD_IFEN, 0x1},
-       {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1},
-       {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1},
-       {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1},
-#define XCM_COMMON_END          1538
-#define XCM_PORT0_START         1538
-       {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
-       {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
-       {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
-       {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
-       {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD00, 0x2},
-       {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD10, 0x2},
-       {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
-       {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
-#define XCM_PORT0_END           1546
-#define XCM_PORT1_START         1546
-       {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
-       {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
-       {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
-       {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
-       {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD01, 0x2},
-       {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD11, 0x2},
-       {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
-       {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
-#define XCM_PORT1_END           1554
-#define XCM_FUNC0_START         1554
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
-       {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
-#define XCM_FUNC0_END           1563
-#define XCM_FUNC1_START         1563
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
-       {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
-#define XCM_FUNC1_END           1572
-#define XCM_FUNC2_START         1572
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
-       {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
-#define XCM_FUNC2_END           1581
-#define XCM_FUNC3_START         1581
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
-       {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
-#define XCM_FUNC3_END           1590
-#define XCM_FUNC4_START         1590
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
-       {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
-#define XCM_FUNC4_END           1599
-#define XCM_FUNC5_START         1599
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
-       {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
-#define XCM_FUNC5_END           1608
-#define XCM_FUNC6_START         1608
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
-       {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
-#define XCM_FUNC6_END           1617
-#define XCM_FUNC7_START         1617
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
-       {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
-       {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
-       {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
-#define XCM_FUNC7_END           1626
-#define XSEM_COMMON_START       1626
-       {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0},
-       {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0},
-       {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0},
-       {OP_RD, XSEM_REG_MSG_NUM_FOC1, 0x0},
-       {OP_RD, XSEM_REG_MSG_NUM_FOC2, 0x0},
-       {OP_RD, XSEM_REG_MSG_NUM_FOC3, 0x0},
-       {OP_WR, XSEM_REG_ARB_ELEMENT0, 0x1},
-       {OP_WR, XSEM_REG_ARB_ELEMENT1, 0x2},
-       {OP_WR, XSEM_REG_ARB_ELEMENT2, 0x3},
-       {OP_WR, XSEM_REG_ARB_ELEMENT3, 0x0},
-       {OP_WR, XSEM_REG_ARB_ELEMENT4, 0x4},
-       {OP_WR, XSEM_REG_ARB_CYCLE_SIZE, 0x1},
-       {OP_WR, XSEM_REG_TS_0_AS, 0x0},
-       {OP_WR, XSEM_REG_TS_1_AS, 0x1},
-       {OP_WR, XSEM_REG_TS_2_AS, 0x4},
-       {OP_WR, XSEM_REG_TS_3_AS, 0x0},
-       {OP_WR, XSEM_REG_TS_4_AS, 0x1},
-       {OP_WR, XSEM_REG_TS_5_AS, 0x3},
-       {OP_WR, XSEM_REG_TS_6_AS, 0x0},
-       {OP_WR, XSEM_REG_TS_7_AS, 0x1},
-       {OP_WR, XSEM_REG_TS_8_AS, 0x4},
-       {OP_WR, XSEM_REG_TS_9_AS, 0x0},
-       {OP_WR, XSEM_REG_TS_10_AS, 0x1},
-       {OP_WR, XSEM_REG_TS_11_AS, 0x3},
-       {OP_WR, XSEM_REG_TS_12_AS, 0x0},
-       {OP_WR, XSEM_REG_TS_13_AS, 0x1},
-       {OP_WR, XSEM_REG_TS_14_AS, 0x4},
-       {OP_WR, XSEM_REG_TS_15_AS, 0x0},
-       {OP_WR, XSEM_REG_TS_16_AS, 0x4},
-       {OP_WR, XSEM_REG_TS_17_AS, 0x3},
-       {OP_ZR, XSEM_REG_TS_18_AS, 0x2},
-       {OP_WR, XSEM_REG_ENABLE_IN, 0x3fff},
-       {OP_WR, XSEM_REG_ENABLE_OUT, 0x3ff},
-       {OP_WR, XSEM_REG_FIC0_DISABLE, 0x0},
-       {OP_WR, XSEM_REG_FIC1_DISABLE, 0x0},
-       {OP_WR, XSEM_REG_PAS_DISABLE, 0x0},
-       {OP_WR, XSEM_REG_THREADS_LIST, 0xffff},
-       {OP_ZR, XSEM_REG_PASSIVE_BUFFER, 0x800},
-       {OP_WR, XSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
-       {OP_WR, XSEM_REG_FAST_MEMORY + 0x18000, 0x0},
-       {OP_WR, XSEM_REG_FAST_MEMORY + 0x18040, 0x18},
-       {OP_WR, XSEM_REG_FAST_MEMORY + 0x18080, 0xc},
-       {OP_WR, XSEM_REG_FAST_MEMORY + 0x180c0, 0x66},
-       {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
-       {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18300, 0x138},
-       {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
-       {OP_WR, XSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
-       {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18340, 0x1f4},
-       {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18340, 0x0},
-       {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18340, 0x5},
-       {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
-       {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
-       {OP_WR_EMUL_E1H, XSEM_REG_FAST_MEMORY + 0x11480, 0x0},
-       {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3d60, 0x4},
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x11480, 0x1},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d60 + 0x10, 0x202f3},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x29c8, 0x4},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3000, 0x48},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29c8 + 0x10, 0x20348},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2080, 0x48},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1000, 0x2},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x9020, 0xc8},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3128, 0x8e},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x9000, 0x2},
-       {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3368, 0x0},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x21a8, 0x86},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3370, 0x202f5},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2000, 0x20},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3b90, 0x402f7},
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x23c8, 0x0},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3e20, 0x202fb},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x23d0, 0x2034a},
-       {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1518, 0x1},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2498, 0x4034c},
-       {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1830, 0x0},
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2c20, 0x0},
-       {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1838, 0x0},
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2c10, 0x0},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1820, 0x202fd},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2c08, 0x20350},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2},
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3010, 0x1},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b00, 0x4},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x4040, 0x10},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1f48, 0x202ff},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x4000, 0x100352},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6ac0, 0x2},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b00, 0x4},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x8408, 0x20362},
-       {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100301},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100364},
-       {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80311},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80374},
-       {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80319},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c60, 0x8037c},
-       {OP_ZP_E1, XSEM_REG_INT_TABLE, 0xb50000},
-       {OP_ZP_E1H, XSEM_REG_INT_TABLE, 0xbd0000},
-       {OP_WR_64_E1, XSEM_REG_INT_TABLE + 0x368, 0x130321},
-       {OP_WR_64_E1H, XSEM_REG_INT_TABLE + 0x3a8, 0xb0384},
-       {OP_ZP_E1, XSEM_REG_PRAM, 0x33660000},
-       {OP_ZP_E1H, XSEM_REG_PRAM, 0x34060000},
-       {OP_ZP_E1, XSEM_REG_PRAM + 0x8000, 0x38b30cda},
-       {OP_ZP_E1H, XSEM_REG_PRAM + 0x8000, 0x37960d02},
-       {OP_ZP_E1, XSEM_REG_PRAM + 0x10000, 0x3bb11b07},
-       {OP_ZP_E1H, XSEM_REG_PRAM + 0x10000, 0x3bc31ae8},
-       {OP_ZP_E1, XSEM_REG_PRAM + 0x18000, 0x2a2629f4},
-       {OP_ZP_E1H, XSEM_REG_PRAM + 0x18000, 0x382629d9},
-       {OP_WR_64_E1, XSEM_REG_PRAM + 0x1d6c0, 0x45280323},
-       {OP_ZP_E1H, XSEM_REG_PRAM + 0x20000, 0x124537e3},
-       {OP_WR_64_E1H, XSEM_REG_PRAM + 0x22220, 0x3bbc0386},
-#define XSEM_COMMON_END         1741
-#define XSEM_PORT0_START        1741
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3ba0, 0x14},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc000, 0xfc},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c40, 0x24},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x24a8, 0x14},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1400, 0xa},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2548, 0x24},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1450, 0x6},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2668, 0x24},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3378, 0xfc},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2788, 0x24},
-       {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b58, 0x0},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x28a8, 0x24},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d78, 0x20325},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa000, 0x28},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d88, 0x100327},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa140, 0xc},
-       {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1500, 0x0},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29e0, 0x20388},
-       {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1508, 0x1},
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3000, 0x1},
-       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5020, 0x2},
-       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5030, 0x2},
-       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5000, 0x2},
-       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5010, 0x2},
-       {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x5040, 0x0},
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x5208, 0x1},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x2038a},
-       {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50b8, 0x1},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b10, 0x42},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x20337},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b10, 0x42},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d20, 0x4},
-#define XSEM_PORT0_END          1775
-#define XSEM_PORT1_START        1775
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3bf0, 0x14},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc3f0, 0xfc},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3cd0, 0x24},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x24f8, 0x14},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1428, 0xa},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x25d8, 0x24},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1468, 0x6},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x26f8, 0x24},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3768, 0xfc},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2818, 0x24},
-       {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b5c, 0x0},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2938, 0x24},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d80, 0x20339},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa0a0, 0x28},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3dc8, 0x10033b},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa170, 0xc},
-       {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1504, 0x0},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29e8, 0x2038c},
-       {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x150c, 0x1},
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3004, 0x1},
-       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5028, 0x2},
-       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5038, 0x2},
-       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5008, 0x2},
-       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5018, 0x2},
-       {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x5044, 0x0},
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x520c, 0x1},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x2038e},
-       {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50bc, 0x1},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6c18, 0x42},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2034b},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4c18, 0x42},
-       {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d30, 0x4},
-#define XSEM_PORT1_END          1809
-#define XSEM_FUNC0_START        1809
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e0, 0x0},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29f0, 0x100390},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
-#define XSEM_FUNC0_END          1812
-#define XSEM_FUNC1_START        1812
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e4, 0x0},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a30, 0x1003a0},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
-#define XSEM_FUNC1_END          1815
-#define XSEM_FUNC2_START        1815
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e8, 0x0},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a70, 0x1003b0},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe},
-#define XSEM_FUNC2_END          1818
-#define XSEM_FUNC3_START        1818
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7ec, 0x0},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2ab0, 0x1003c0},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe},
-#define XSEM_FUNC3_END          1821
-#define XSEM_FUNC4_START        1821
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f0, 0x0},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2af0, 0x1003d0},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5128, 0xe},
-#define XSEM_FUNC4_END          1824
-#define XSEM_FUNC5_START        1824
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f4, 0x0},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2b30, 0x1003e0},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5160, 0xe},
-#define XSEM_FUNC5_END          1827
-#define XSEM_FUNC6_START        1827
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f8, 0x0},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2b70, 0x1003f0},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5198, 0xe},
-#define XSEM_FUNC6_END          1830
-#define XSEM_FUNC7_START        1830
-       {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7fc, 0x0},
-       {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2bb0, 0x100400},
-       {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x51d0, 0xe},
-#define XSEM_FUNC7_END          1833
-#define CDU_COMMON_START        1833
-       {OP_WR, CDU_REG_CDU_CONTROL0, 0x1},
-       {OP_WR_E1H, CDU_REG_MF_MODE, 0x1},
-       {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000},
-       {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d},
-       {OP_WB_E1, CDU_REG_L1TT, 0x200034d},
-       {OP_WB_E1H, CDU_REG_L1TT, 0x2000410},
-       {OP_WB_E1, CDU_REG_MATT, 0x20054d},
-       {OP_WB_E1H, CDU_REG_MATT, 0x280610},
-       {OP_ZR_E1, CDU_REG_MATT + 0x80, 0x2},
-       {OP_WB_E1, CDU_REG_MATT + 0x88, 0x6056d},
-       {OP_ZR, CDU_REG_MATT + 0xa0, 0x18},
-#define CDU_COMMON_END          1844
-#define DMAE_COMMON_START       1844
-       {OP_ZR, DMAE_REG_CMD_MEM, 0xe0},
-       {OP_WR, DMAE_REG_CRC16C_INIT, 0x0},
-       {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1},
-       {OP_WR_E1, DMAE_REG_PXP_REQ_INIT_CRD, 0x1},
-       {OP_WR_E1H, DMAE_REG_PXP_REQ_INIT_CRD, 0x2},
-       {OP_WR, DMAE_REG_PCI_IFEN, 0x1},
-       {OP_WR, DMAE_REG_GRC_IFEN, 0x1},
-#define DMAE_COMMON_END         1851
-#define PXP_COMMON_START        1851
-       {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x400, 0x50573},
-       {OP_WB_E1H, PXP_REG_HST_INBOUND_INT + 0x400, 0x50638},
-       {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x420, 0x50578},
-       {OP_WB_E1H, PXP_REG_HST_INBOUND_INT, 0x5063d},
-       {OP_WB_E1, PXP_REG_HST_INBOUND_INT, 0x5057d},
-       {OP_WB_E1H, PXP_REG_HST_INBOUND_INT + 0x20, 0x50642},
-#define PXP_COMMON_END          1857
-#define CFC_COMMON_START        1857
-       {OP_ZR_E1H, CFC_REG_LINK_LIST, 0x100},
-       {OP_WR, CFC_REG_CONTROL0, 0x10},
-       {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff},
-       {OP_WR, CFC_REG_INTERFACES, 0x280000},
-       {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a},
-       {OP_WR, CFC_REG_INTERFACES, 0x0},
-#define CFC_COMMON_END          1863
-#define HC_COMMON_START         1863
-       {OP_ZR_E1, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4},
-#define HC_COMMON_END           1864
-#define HC_PORT0_START          1864
-       {OP_WR_E1, HC_REG_CONFIG_0, 0x1080},
-       {OP_ZR_E1, HC_REG_UC_RAM_ADDR_0, 0x2},
-       {OP_WR_E1, HC_REG_ATTN_NUM_P0, 0x10},
-       {OP_WR_E1, HC_REG_LEADING_EDGE_0, 0xffff},
-       {OP_WR_E1, HC_REG_TRAILING_EDGE_0, 0xffff},
-       {OP_WR_E1, HC_REG_AGG_INT_0, 0x0},
-       {OP_WR_E1, HC_REG_ATTN_IDX, 0x0},
-       {OP_ZR_E1, HC_REG_ATTN_BIT, 0x2},
-       {OP_WR_E1, HC_REG_VQID_0, 0x2b5},
-       {OP_WR_E1, HC_REG_PCI_CONFIG_0, 0x0},
-       {OP_ZR_E1, HC_REG_P0_PROD_CONS, 0x4a},
-       {OP_WR_E1, HC_REG_INT_MASK, 0x1ffff},
-       {OP_ZR_E1, HC_REG_PBA_COMMAND, 0x2},
-       {OP_WR_E1, HC_REG_CONFIG_0, 0x1a80},
-       {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS, 0x24},
-       {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
-       {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
-       {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
-#define HC_PORT0_END            1882
-#define HC_PORT1_START          1882
-       {OP_WR_E1, HC_REG_CONFIG_1, 0x1080},
-       {OP_ZR_E1, HC_REG_UC_RAM_ADDR_1, 0x2},
-       {OP_WR_E1, HC_REG_ATTN_NUM_P1, 0x10},
-       {OP_WR_E1, HC_REG_LEADING_EDGE_1, 0xffff},
-       {OP_WR_E1, HC_REG_TRAILING_EDGE_1, 0xffff},
-       {OP_WR_E1, HC_REG_AGG_INT_1, 0x0},
-       {OP_WR_E1, HC_REG_ATTN_IDX + 0x4, 0x0},
-       {OP_ZR_E1, HC_REG_ATTN_BIT + 0x8, 0x2},
-       {OP_WR_E1, HC_REG_VQID_1, 0x2b5},
-       {OP_WR_E1, HC_REG_PCI_CONFIG_1, 0x0},
-       {OP_ZR_E1, HC_REG_P1_PROD_CONS, 0x4a},
-       {OP_WR_E1, HC_REG_INT_MASK + 0x4, 0x1ffff},
-       {OP_ZR_E1, HC_REG_PBA_COMMAND + 0x8, 0x2},
-       {OP_WR_E1, HC_REG_CONFIG_1, 0x1a80},
-       {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
-       {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
-       {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
-       {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
-#define HC_PORT1_END            1900
-#define HC_FUNC0_START          1900
-       {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
-       {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x0},
-       {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
-       {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
-       {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
-       {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
-       {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
-       {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
-       {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
-       {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
-       {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
-#define HC_FUNC0_END            1915
-#define HC_FUNC1_START          1915
-       {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
-       {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x1},
-       {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
-       {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
-       {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
-       {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
-       {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
-       {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
-       {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
-       {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
-       {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
-#define HC_FUNC1_END            1930
-#define HC_FUNC2_START          1930
-       {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
-       {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x2},
-       {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
-       {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
-       {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
-       {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
-       {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
-       {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
-       {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
-       {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
-       {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
-#define HC_FUNC2_END            1945
-#define HC_FUNC3_START          1945
-       {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
-       {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x3},
-       {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
-       {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
-       {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
-       {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
-       {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
-       {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
-       {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
-       {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
-       {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
-#define HC_FUNC3_END            1960
-#define HC_FUNC4_START          1960
-       {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
-       {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x4},
-       {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
-       {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
-       {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
-       {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
-       {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
-       {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
-       {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
-       {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
-       {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
-#define HC_FUNC4_END            1975
-#define HC_FUNC5_START          1975
-       {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
-       {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x5},
-       {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
-       {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
-       {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
-       {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
-       {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
-       {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
-       {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
-       {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
-       {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
-#define HC_FUNC5_END            1990
-#define HC_FUNC6_START          1990
-       {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
-       {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x6},
-       {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
-       {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
-       {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
-       {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
-       {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
-       {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
-       {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
-       {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
-       {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
-#define HC_FUNC6_END            2005
-#define HC_FUNC7_START          2005
-       {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
-       {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x7},
-       {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
-       {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
-       {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
-       {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
-       {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
-       {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
-       {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
-       {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
-       {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
-       {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
-#define HC_FUNC7_END            2020
-#define PXP2_COMMON_START       2020
-       {OP_WR_E1H, PXP2_REG_RQ_DRAM_ALIGN, 0x1},
-       {OP_WR, PXP2_REG_PGL_CONTROL0, 0xe38340},
-       {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10},
-       {OP_WR_E1H, PXP2_REG_RQ_ELT_DISABLE, 0x1},
-       {OP_WR_E1H, PXP2_REG_WR_REV_MODE, 0x0},
-       {OP_WR, PXP2_REG_PGL_INT_TSDM_0, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_TSDM_1, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_TSDM_2, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_TSDM_3, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_TSDM_4, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_TSDM_5, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_TSDM_6, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_TSDM_7, 0xffffffff},
-       {OP_WR_E1, PXP2_REG_PGL_INT_USDM_1, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_USDM_2, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_USDM_3, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_USDM_4, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_USDM_5, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_USDM_6, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_USDM_7, 0xffffffff},
-       {OP_WR_E1H, PXP2_REG_PGL_INT_XSDM_1, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_XSDM_2, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_XSDM_3, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_XSDM_4, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_XSDM_5, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_XSDM_6, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_XSDM_7, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_CSDM_0, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_CSDM_1, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_CSDM_2, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_CSDM_3, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_CSDM_4, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_CSDM_5, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_CSDM_6, 0xffffffff},
-       {OP_WR, PXP2_REG_PGL_INT_CSDM_7, 0xffffffff},
-       {OP_WR_E1, PXP2_REG_PGL_INT_XSDM_0, 0xffff3330},
-       {OP_WR_E1H, PXP2_REG_PGL_INT_XSDM_0, 0xff802000},
-       {OP_WR_E1, PXP2_REG_PGL_INT_XSDM_1, 0xffff3340},
-       {OP_WR_E1H, PXP2_REG_PGL_INT_USDM_0, 0xf0005000},
-       {OP_WR_E1, PXP2_REG_PGL_INT_USDM_0, 0xf0003000},
-       {OP_WR_E1H, PXP2_REG_PGL_INT_USDM_1, 0xf0008000},
-       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ6, 0x8},
-       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ9, 0x8},
-       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ10, 0x8},
-       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ11, 0x2},
-       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ17, 0x4},
-       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ18, 0x5},
-       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ19, 0x4},
-       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ22, 0x0},
-       {OP_WR, PXP2_REG_RD_START_INIT, 0x1},
-       {OP_WR, PXP2_REG_WR_DMAE_TH, 0x3f},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD0, 0x40},
-       {OP_WR, PXP2_REG_PSWRQ_BW_ADD1, 0x1808},
-       {OP_WR, PXP2_REG_PSWRQ_BW_ADD2, 0x803},
-       {OP_WR, PXP2_REG_PSWRQ_BW_ADD3, 0x803},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD4, 0x40},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD5, 0x3},
-       {OP_WR, PXP2_REG_PSWRQ_BW_ADD6, 0x803},
-       {OP_WR, PXP2_REG_PSWRQ_BW_ADD7, 0x803},
-       {OP_WR, PXP2_REG_PSWRQ_BW_ADD8, 0x803},
-       {OP_WR, PXP2_REG_PSWRQ_BW_ADD9, 0x10003},
-       {OP_WR, PXP2_REG_PSWRQ_BW_ADD10, 0x803},
-       {OP_WR, PXP2_REG_PSWRQ_BW_ADD11, 0x803},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD12, 0x3},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD13, 0x3},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD14, 0x3},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD15, 0x3},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD16, 0x3},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD17, 0x3},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD18, 0x3},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD19, 0x3},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD20, 0x3},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD22, 0x3},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD23, 0x3},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD24, 0x3},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD25, 0x3},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD26, 0x3},
-       {OP_WR, PXP2_REG_RQ_BW_RD_ADD27, 0x3},
-       {OP_WR, PXP2_REG_PSWRQ_BW_ADD28, 0x2403},
-       {OP_WR, PXP2_REG_RQ_BW_WR_ADD29, 0x2f},
-       {OP_WR, PXP2_REG_RQ_BW_WR_ADD30, 0x9},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND0, 0x19},
-       {OP_WR, PXP2_REG_PSWRQ_BW_UB1, 0x184},
-       {OP_WR, PXP2_REG_PSWRQ_BW_UB2, 0x183},
-       {OP_WR, PXP2_REG_PSWRQ_BW_UB3, 0x306},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND4, 0x19},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND5, 0x6},
-       {OP_WR, PXP2_REG_PSWRQ_BW_UB6, 0x306},
-       {OP_WR, PXP2_REG_PSWRQ_BW_UB7, 0x306},
-       {OP_WR, PXP2_REG_PSWRQ_BW_UB8, 0x306},
-       {OP_WR, PXP2_REG_PSWRQ_BW_UB9, 0xc86},
-       {OP_WR, PXP2_REG_PSWRQ_BW_UB10, 0x306},
-       {OP_WR, PXP2_REG_PSWRQ_BW_UB11, 0x306},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND12, 0x6},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND13, 0x6},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND14, 0x6},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND15, 0x6},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND16, 0x6},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND17, 0x6},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND18, 0x6},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND19, 0x6},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND20, 0x6},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND22, 0x6},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND23, 0x6},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND24, 0x6},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND25, 0x6},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND26, 0x6},
-       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND27, 0x6},
-       {OP_WR, PXP2_REG_PSWRQ_BW_UB28, 0x306},
-       {OP_WR, PXP2_REG_RQ_BW_WR_UBOUND29, 0x13},
-       {OP_WR, PXP2_REG_RQ_BW_WR_UBOUND30, 0x6},
-       {OP_WR, PXP2_REG_PSWRQ_BW_L1, 0x1004},
-       {OP_WR, PXP2_REG_PSWRQ_BW_L2, 0x1004},
-       {OP_WR, PXP2_REG_PSWRQ_BW_RD, 0x106440},
-       {OP_WR, PXP2_REG_PSWRQ_BW_WR, 0x106440},
-       {OP_WR_E1H, PXP2_REG_RQ_ILT_MODE, 0x1},
-       {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1},
-#define PXP2_COMMON_END         2137
-#define MISC_AEU_COMMON_START   2137
-       {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE4_NIG_0, 0xf0000000},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE4_PXP_0, 0xf0000000},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE4_NIG_1, 0xf0000000},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE1_PXP_1, 0x0},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE2_PXP_1, 0x10000},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE3_PXP_1, 0x5014},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
-       {OP_WR_E1H, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0xc00},
-       {OP_WR_E1H, MISC_REG_AEU_GENERAL_MASK, 0x3},
-#define MISC_AEU_COMMON_END     2156
-#define MISC_AEU_PORT0_START    2156
-       {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xff5c0000},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff55fff},
-       {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0, 0xffff},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0x500003e0},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0xf00003e0},
-       {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1, 0x0},
-       {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1, 0xa000},
-       {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1, 0x5},
-       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2, 0xfe00000},
-       {OP_ZR_E1, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x14},
-       {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x7},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4, 0x400},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
-       {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5, 0x3},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5, 0x1000},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE4_NIG_0, 0x0},
-       {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6, 0x3},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6, 0x4000},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555},
-       {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7, 0x3},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7, 0x10000},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE4_PXP_0, 0x0},
-       {OP_ZR_E1H, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x4},
-       {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0},
-       {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3},
-       {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7},
-#define MISC_AEU_PORT0_END      2188
-#define MISC_AEU_PORT1_START    2188
-       {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xff5c0000},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff55fff},
-       {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0, 0xffff},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0x500003e0},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0xf00003e0},
-       {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1, 0x0},
-       {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1, 0xa000},
-       {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1, 0x5},
-       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2, 0xfe00000},
-       {OP_ZR_E1, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x14},
-       {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x7},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4, 0x800},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555},
-       {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5, 0x3},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5, 0x2000},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE4_NIG_1, 0x0},
-       {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6, 0x3},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE1_PXP_1, 0x55540000},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6, 0x8000},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE2_PXP_1, 0x55555555},
-       {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7, 0x3},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE3_PXP_1, 0x5555},
-       {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7, 0x20000},
-       {OP_WR_E1, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
-       {OP_ZR_E1H, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x4},
-       {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0},
-       {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3},
-       {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7},
-#define MISC_AEU_PORT1_END      2220
-
-};
-
-static const u32 init_data_e1[] = {
-       0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0,
-       0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440,
-       0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0,
-       0x00135580, 0x00145a40, 0x00155f00, 0x001663c0, 0x00176880, 0x00186d40,
-       0x00197200, 0x001a76c0, 0x001b7b80, 0x001c8040, 0x001d8500, 0x001e89c0,
-       0x001f8e80, 0x00209340, 0x00002000, 0x00004000, 0x00006000, 0x00008000,
-       0x0000a000, 0x0000c000, 0x0000e000, 0x00010000, 0x00012000, 0x00014000,
-       0x00016000, 0x00018000, 0x0001a000, 0x0001c000, 0x0001e000, 0x00020000,
-       0x00022000, 0x00024000, 0x00026000, 0x00028000, 0x0002a000, 0x0002c000,
-       0x0002e000, 0x00030000, 0x00032000, 0x00034000, 0x00036000, 0x00038000,
-       0x0003a000, 0x0003c000, 0x0003e000, 0x00040000, 0x00042000, 0x00044000,
-       0x00046000, 0x00048000, 0x0004a000, 0x0004c000, 0x0004e000, 0x00050000,
-       0x00052000, 0x00054000, 0x00056000, 0x00058000, 0x0005a000, 0x0005c000,
-       0x0005e000, 0x00060000, 0x00062000, 0x00064000, 0x00066000, 0x00068000,
-       0x0006a000, 0x0006c000, 0x0006e000, 0x00070000, 0x00072000, 0x00074000,
-       0x00076000, 0x00078000, 0x0007a000, 0x0007c000, 0x0007e000, 0x00080000,
-       0x00082000, 0x00084000, 0x00086000, 0x00088000, 0x0008a000, 0x0008c000,
-       0x0008e000, 0x00090000, 0x00092000, 0x00094000, 0x00096000, 0x00098000,
-       0x0009a000, 0x0009c000, 0x0009e000, 0x000a0000, 0x000a2000, 0x000a4000,
-       0x000a6000, 0x000a8000, 0x000aa000, 0x000ac000, 0x000ae000, 0x000b0000,
-       0x000b2000, 0x000b4000, 0x000b6000, 0x000b8000, 0x000ba000, 0x000bc000,
-       0x000be000, 0x000c0000, 0x000c2000, 0x000c4000, 0x000c6000, 0x000c8000,
-       0x000ca000, 0x000cc000, 0x000ce000, 0x000d0000, 0x000d2000, 0x000d4000,
-       0x000d6000, 0x000d8000, 0x000da000, 0x000dc000, 0x000de000, 0x000e0000,
-       0x000e2000, 0x000e4000, 0x000e6000, 0x000e8000, 0x000ea000, 0x000ec000,
-       0x000ee000, 0x000f0000, 0x000f2000, 0x000f4000, 0x000f6000, 0x000f8000,
-       0x000fa000, 0x000fc000, 0x000fe000, 0x00100000, 0x00102000, 0x00104000,
-       0x00106000, 0x00108000, 0x0010a000, 0x0010c000, 0x0010e000, 0x00110000,
-       0x00112000, 0x00114000, 0x00116000, 0x00118000, 0x0011a000, 0x0011c000,
-       0x0011e000, 0x00120000, 0x00122000, 0x00124000, 0x00126000, 0x00128000,
-       0x0012a000, 0x0012c000, 0x0012e000, 0x00130000, 0x00132000, 0x00134000,
-       0x00136000, 0x00138000, 0x0013a000, 0x0013c000, 0x0013e000, 0x00140000,
-       0x00142000, 0x00144000, 0x00146000, 0x00148000, 0x0014a000, 0x0014c000,
-       0x0014e000, 0x00150000, 0x00152000, 0x00154000, 0x00156000, 0x00158000,
-       0x0015a000, 0x0015c000, 0x0015e000, 0x00160000, 0x00162000, 0x00164000,
-       0x00166000, 0x00168000, 0x0016a000, 0x0016c000, 0x0016e000, 0x00170000,
-       0x00172000, 0x00174000, 0x00176000, 0x00178000, 0x0017a000, 0x0017c000,
-       0x0017e000, 0x00180000, 0x00182000, 0x00184000, 0x00186000, 0x00188000,
-       0x0018a000, 0x0018c000, 0x0018e000, 0x00190000, 0x00192000, 0x00194000,
-       0x00196000, 0x00198000, 0x0019a000, 0x0019c000, 0x0019e000, 0x001a0000,
-       0x001a2000, 0x001a4000, 0x001a6000, 0x001a8000, 0x001aa000, 0x001ac000,
-       0x001ae000, 0x001b0000, 0x001b2000, 0x001b4000, 0x001b6000, 0x001b8000,
-       0x001ba000, 0x001bc000, 0x001be000, 0x001c0000, 0x001c2000, 0x001c4000,
-       0x001c6000, 0x001c8000, 0x001ca000, 0x001cc000, 0x001ce000, 0x001d0000,
-       0x001d2000, 0x001d4000, 0x001d6000, 0x001d8000, 0x001da000, 0x001dc000,
-       0x001de000, 0x001e0000, 0x001e2000, 0x001e4000, 0x001e6000, 0x001e8000,
-       0x001ea000, 0x001ec000, 0x001ee000, 0x001f0000, 0x001f2000, 0x001f4000,
-       0x001f6000, 0x001f8000, 0x001fa000, 0x001fc000, 0x001fe000, 0x00200000,
-       0x00202000, 0x00204000, 0x00206000, 0x00208000, 0x0020a000, 0x0020c000,
-       0x0020e000, 0x00210000, 0x00212000, 0x00214000, 0x00216000, 0x00218000,
-       0x0021a000, 0x0021c000, 0x0021e000, 0x00220000, 0x00222000, 0x00224000,
-       0x00226000, 0x00228000, 0x0022a000, 0x0022c000, 0x0022e000, 0x00230000,
-       0x00232000, 0x00234000, 0x00236000, 0x00238000, 0x0023a000, 0x0023c000,
-       0x0023e000, 0x00240000, 0x00242000, 0x00244000, 0x00246000, 0x00248000,
-       0x0024a000, 0x0024c000, 0x0024e000, 0x00250000, 0x00252000, 0x00254000,
-       0x00256000, 0x00258000, 0x0025a000, 0x0025c000, 0x0025e000, 0x00260000,
-       0x00262000, 0x00264000, 0x00266000, 0x00268000, 0x0026a000, 0x0026c000,
-       0x0026e000, 0x00270000, 0x00272000, 0x00274000, 0x00276000, 0x00278000,
-       0x0027a000, 0x0027c000, 0x0027e000, 0x00280000, 0x00282000, 0x00284000,
-       0x00286000, 0x00288000, 0x0028a000, 0x0028c000, 0x0028e000, 0x00290000,
-       0x00292000, 0x00294000, 0x00296000, 0x00298000, 0x0029a000, 0x0029c000,
-       0x0029e000, 0x002a0000, 0x002a2000, 0x002a4000, 0x002a6000, 0x002a8000,
-       0x002aa000, 0x002ac000, 0x002ae000, 0x002b0000, 0x002b2000, 0x002b4000,
-       0x002b6000, 0x002b8000, 0x002ba000, 0x002bc000, 0x002be000, 0x002c0000,
-       0x002c2000, 0x002c4000, 0x002c6000, 0x002c8000, 0x002ca000, 0x002cc000,
-       0x002ce000, 0x002d0000, 0x002d2000, 0x002d4000, 0x002d6000, 0x002d8000,
-       0x002da000, 0x002dc000, 0x002de000, 0x002e0000, 0x002e2000, 0x002e4000,
-       0x002e6000, 0x002e8000, 0x002ea000, 0x002ec000, 0x002ee000, 0x002f0000,
-       0x002f2000, 0x002f4000, 0x002f6000, 0x002f8000, 0x002fa000, 0x002fc000,
-       0x002fe000, 0x00300000, 0x00302000, 0x00304000, 0x00306000, 0x00308000,
-       0x0030a000, 0x0030c000, 0x0030e000, 0x00310000, 0x00312000, 0x00314000,
-       0x00316000, 0x00318000, 0x0031a000, 0x0031c000, 0x0031e000, 0x00320000,
-       0x00322000, 0x00324000, 0x00326000, 0x00328000, 0x0032a000, 0x0032c000,
-       0x0032e000, 0x00330000, 0x00332000, 0x00334000, 0x00336000, 0x00338000,
-       0x0033a000, 0x0033c000, 0x0033e000, 0x00340000, 0x00342000, 0x00344000,
-       0x00346000, 0x00348000, 0x0034a000, 0x0034c000, 0x0034e000, 0x00350000,
-       0x00352000, 0x00354000, 0x00356000, 0x00358000, 0x0035a000, 0x0035c000,
-       0x0035e000, 0x00360000, 0x00362000, 0x00364000, 0x00366000, 0x00368000,
-       0x0036a000, 0x0036c000, 0x0036e000, 0x00370000, 0x00372000, 0x00374000,
-       0x00376000, 0x00378000, 0x0037a000, 0x0037c000, 0x0037e000, 0x00380000,
-       0x00382000, 0x00384000, 0x00386000, 0x00388000, 0x0038a000, 0x0038c000,
-       0x0038e000, 0x00390000, 0x00392000, 0x00394000, 0x00396000, 0x00398000,
-       0x0039a000, 0x0039c000, 0x0039e000, 0x003a0000, 0x003a2000, 0x003a4000,
-       0x003a6000, 0x003a8000, 0x003aa000, 0x003ac000, 0x003ae000, 0x003b0000,
-       0x003b2000, 0x003b4000, 0x003b6000, 0x003b8000, 0x003ba000, 0x003bc000,
-       0x003be000, 0x003c0000, 0x003c2000, 0x003c4000, 0x003c6000, 0x003c8000,
-       0x003ca000, 0x003cc000, 0x003ce000, 0x003d0000, 0x003d2000, 0x003d4000,
-       0x003d6000, 0x003d8000, 0x003da000, 0x003dc000, 0x003de000, 0x003e0000,
-       0x003e2000, 0x003e4000, 0x003e6000, 0x003e8000, 0x003ea000, 0x003ec000,
-       0x003ee000, 0x003f0000, 0x003f2000, 0x003f4000, 0x003f6000, 0x003f8000,
-       0x003fa000, 0x003fc000, 0x003fe000, 0x003fe001, 0x00000000, 0x000001ff,
-       0x00000200, 0x00000001, 0x00000003, 0x00bebc20, 0x00000003, 0x00bebc20,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-       0xffffffff, 0xffffffff, 0x00000000, 0x00007ff8, 0x00000000, 0x00003500,
-       0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000003,
-       0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
-       0x00000003, 0x00bebc20, 0x00002000, 0x000040c0, 0x00006180, 0x00008240,
-       0x0000a300, 0x0000c3c0, 0x0000e480, 0x00010540, 0x00012600, 0x000146c0,
-       0x00016780, 0x00018840, 0x0001a900, 0x0001c9c0, 0x0001ea80, 0x00020b40,
-       0x00022c00, 0x00024cc0, 0x00026d80, 0x00028e40, 0x0002af00, 0x0002cfc0,
-       0x0002f080, 0x00031140, 0x00033200, 0x000352c0, 0x00037380, 0x00039440,
-       0x0003b500, 0x0003d5c0, 0x0003f680, 0x00041740, 0x00043800, 0x000458c0,
-       0x00047980, 0x00049a40, 0x00008000, 0x00010380, 0x00018700, 0x00020a80,
-       0x00028e00, 0x00031180, 0x00039500, 0x00041880, 0x00049c00, 0x00051f80,
-       0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80, 0x0007b100, 0x00083480,
-       0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280, 0x000ac600, 0x000b4980,
-       0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780, 0x000ddb00, 0x00001900,
-       0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8,
-       0x00000000, 0x00001500, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x00000000, 0x00007ff8, 0x00000000, 0x00001500, 0x00001000, 0x00002080,
-       0x00003100, 0x00004180, 0x00005200, 0x00006280, 0x00007300, 0x00008380,
-       0x00009400, 0x0000a480, 0x0000b500, 0x0000c580, 0x0000d600, 0x0000e680,
-       0x0000f700, 0x00010780, 0x00011800, 0x00012880, 0x00013900, 0x00014980,
-       0x00015a00, 0x00016a80, 0x00017b00, 0x00018b80, 0x00019c00, 0x0001ac80,
-       0x0001bd00, 0x0001cd80, 0x0001de00, 0x0001ee80, 0x0001ff00, 0x10000000,
-       0x000028ad, 0x00000000, 0x00010001, 0x00350804, 0xccccccc1, 0xffffffff,
-       0xffffffff, 0x7058103c, 0x00000000, 0xcccc0201, 0xcccccccc, 0x00000000,
-       0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, 0x00000000,
-       0x00003500, 0x000e01b7, 0x011600d6, 0x0000ffff, 0x00000000, 0x0000ffff,
-       0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
-       0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
-       0x00000000, 0x00100000, 0x00000000, 0x007201bb, 0x012300f3, 0x0000ffff,
-       0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
-       0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
-       0x00000000, 0x0000ffff, 0x00000000, 0x00100000, 0x00000000, 0xfffffff3,
-       0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c,
-       0xcdcdcdcd, 0xfffffff1, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406,
-       0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c,
-       0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7,
-       0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c,
-       0xcdcdcdcd, 0xfffffff5, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x310fffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1,
-       0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
-       0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
-       0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
-       0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
-       0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x30efffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
-       0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
-       0xcdcdcdcd, 0xfffffff3, 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6,
-       0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c,
-       0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014,
-       0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa,
-       0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c,
-       0xcdcdcdcd, 0xffffff97, 0x056fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000,
-       0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3,
-       0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c,
-       0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406,
-       0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c,
-       0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffff8a, 0x042fffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97,
-       0x05cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c,
-       0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x300fffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1,
-       0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
-       0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
-       0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
-       0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
-       0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x040fffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
-       0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
-       0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
-       0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff,
-       0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c,
-       0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
-       0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff,
-       0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c,
-       0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
-       0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff,
-       0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c,
-       0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
-       0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff,
-       0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c,
-       0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
-       0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff,
-       0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c,
-       0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
-       0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff,
-       0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c,
-       0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
-       0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff,
-       0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c,
-       0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
-       0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff,
-       0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c,
-       0xcdcdcdcd, 0x00100000, 0x00070100, 0x00028170, 0x000b8198, 0x00020250,
-       0x00010270, 0x000f0280, 0x00010370, 0x00080000, 0x00080080, 0x00028100,
-       0x000b8128, 0x000201e0, 0x00010200, 0x00070210, 0x00020280, 0x000f0000,
-       0x000800f0, 0x00028170, 0x000b8198, 0x00020250, 0x00010270, 0x000b8280,
-       0x00080338, 0x00100000, 0x00080100, 0x00028180, 0x000b81a8, 0x00020260,
-       0x00018280, 0x000e8298, 0x00080380, 0x00028000, 0x000b8028, 0x000200e0,
-       0x00010100, 0x00008110, 0x00000118, 0xcccccccc, 0xcccccccc, 0xcccccccc,
-       0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc,
-       0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000
-};
-
-static const u32 init_data_e1h[] = {
-       0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0,
-       0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440,
-       0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0,
-       0x00135580, 0x00145a40, 0x00155f00, 0x001663c0, 0x00176880, 0x00186d40,
-       0x00197200, 0x001a76c0, 0x001b7b80, 0x001c8040, 0x001d8500, 0x001e89c0,
-       0x001f8e80, 0x00209340, 0x00002000, 0x00004000, 0x00006000, 0x00008000,
-       0x0000a000, 0x0000c000, 0x0000e000, 0x00010000, 0x00012000, 0x00014000,
-       0x00016000, 0x00018000, 0x0001a000, 0x0001c000, 0x0001e000, 0x00020000,
-       0x00022000, 0x00024000, 0x00026000, 0x00028000, 0x0002a000, 0x0002c000,
-       0x0002e000, 0x00030000, 0x00032000, 0x00034000, 0x00036000, 0x00038000,
-       0x0003a000, 0x0003c000, 0x0003e000, 0x00040000, 0x00042000, 0x00044000,
-       0x00046000, 0x00048000, 0x0004a000, 0x0004c000, 0x0004e000, 0x00050000,
-       0x00052000, 0x00054000, 0x00056000, 0x00058000, 0x0005a000, 0x0005c000,
-       0x0005e000, 0x00060000, 0x00062000, 0x00064000, 0x00066000, 0x00068000,
-       0x0006a000, 0x0006c000, 0x0006e000, 0x00070000, 0x00072000, 0x00074000,
-       0x00076000, 0x00078000, 0x0007a000, 0x0007c000, 0x0007e000, 0x00080000,
-       0x00082000, 0x00084000, 0x00086000, 0x00088000, 0x0008a000, 0x0008c000,
-       0x0008e000, 0x00090000, 0x00092000, 0x00094000, 0x00096000, 0x00098000,
-       0x0009a000, 0x0009c000, 0x0009e000, 0x000a0000, 0x000a2000, 0x000a4000,
-       0x000a6000, 0x000a8000, 0x000aa000, 0x000ac000, 0x000ae000, 0x000b0000,
-       0x000b2000, 0x000b4000, 0x000b6000, 0x000b8000, 0x000ba000, 0x000bc000,
-       0x000be000, 0x000c0000, 0x000c2000, 0x000c4000, 0x000c6000, 0x000c8000,
-       0x000ca000, 0x000cc000, 0x000ce000, 0x000d0000, 0x000d2000, 0x000d4000,
-       0x000d6000, 0x000d8000, 0x000da000, 0x000dc000, 0x000de000, 0x000e0000,
-       0x000e2000, 0x000e4000, 0x000e6000, 0x000e8000, 0x000ea000, 0x000ec000,
-       0x000ee000, 0x000f0000, 0x000f2000, 0x000f4000, 0x000f6000, 0x000f8000,
-       0x000fa000, 0x000fc000, 0x000fe000, 0x00100000, 0x00102000, 0x00104000,
-       0x00106000, 0x00108000, 0x0010a000, 0x0010c000, 0x0010e000, 0x00110000,
-       0x00112000, 0x00114000, 0x00116000, 0x00118000, 0x0011a000, 0x0011c000,
-       0x0011e000, 0x00120000, 0x00122000, 0x00124000, 0x00126000, 0x00128000,
-       0x0012a000, 0x0012c000, 0x0012e000, 0x00130000, 0x00132000, 0x00134000,
-       0x00136000, 0x00138000, 0x0013a000, 0x0013c000, 0x0013e000, 0x00140000,
-       0x00142000, 0x00144000, 0x00146000, 0x00148000, 0x0014a000, 0x0014c000,
-       0x0014e000, 0x00150000, 0x00152000, 0x00154000, 0x00156000, 0x00158000,
-       0x0015a000, 0x0015c000, 0x0015e000, 0x00160000, 0x00162000, 0x00164000,
-       0x00166000, 0x00168000, 0x0016a000, 0x0016c000, 0x0016e000, 0x00170000,
-       0x00172000, 0x00174000, 0x00176000, 0x00178000, 0x0017a000, 0x0017c000,
-       0x0017e000, 0x00180000, 0x00182000, 0x00184000, 0x00186000, 0x00188000,
-       0x0018a000, 0x0018c000, 0x0018e000, 0x00190000, 0x00192000, 0x00194000,
-       0x00196000, 0x00198000, 0x0019a000, 0x0019c000, 0x0019e000, 0x001a0000,
-       0x001a2000, 0x001a4000, 0x001a6000, 0x001a8000, 0x001aa000, 0x001ac000,
-       0x001ae000, 0x001b0000, 0x001b2000, 0x001b4000, 0x001b6000, 0x001b8000,
-       0x001ba000, 0x001bc000, 0x001be000, 0x001c0000, 0x001c2000, 0x001c4000,
-       0x001c6000, 0x001c8000, 0x001ca000, 0x001cc000, 0x001ce000, 0x001d0000,
-       0x001d2000, 0x001d4000, 0x001d6000, 0x001d8000, 0x001da000, 0x001dc000,
-       0x001de000, 0x001e0000, 0x001e2000, 0x001e4000, 0x001e6000, 0x001e8000,
-       0x001ea000, 0x001ec000, 0x001ee000, 0x001f0000, 0x001f2000, 0x001f4000,
-       0x001f6000, 0x001f8000, 0x001fa000, 0x001fc000, 0x001fe000, 0x00200000,
-       0x00202000, 0x00204000, 0x00206000, 0x00208000, 0x0020a000, 0x0020c000,
-       0x0020e000, 0x00210000, 0x00212000, 0x00214000, 0x00216000, 0x00218000,
-       0x0021a000, 0x0021c000, 0x0021e000, 0x00220000, 0x00222000, 0x00224000,
-       0x00226000, 0x00228000, 0x0022a000, 0x0022c000, 0x0022e000, 0x00230000,
-       0x00232000, 0x00234000, 0x00236000, 0x00238000, 0x0023a000, 0x0023c000,
-       0x0023e000, 0x00240000, 0x00242000, 0x00244000, 0x00246000, 0x00248000,
-       0x0024a000, 0x0024c000, 0x0024e000, 0x00250000, 0x00252000, 0x00254000,
-       0x00256000, 0x00258000, 0x0025a000, 0x0025c000, 0x0025e000, 0x00260000,
-       0x00262000, 0x00264000, 0x00266000, 0x00268000, 0x0026a000, 0x0026c000,
-       0x0026e000, 0x00270000, 0x00272000, 0x00274000, 0x00276000, 0x00278000,
-       0x0027a000, 0x0027c000, 0x0027e000, 0x00280000, 0x00282000, 0x00284000,
-       0x00286000, 0x00288000, 0x0028a000, 0x0028c000, 0x0028e000, 0x00290000,
-       0x00292000, 0x00294000, 0x00296000, 0x00298000, 0x0029a000, 0x0029c000,
-       0x0029e000, 0x002a0000, 0x002a2000, 0x002a4000, 0x002a6000, 0x002a8000,
-       0x002aa000, 0x002ac000, 0x002ae000, 0x002b0000, 0x002b2000, 0x002b4000,
-       0x002b6000, 0x002b8000, 0x002ba000, 0x002bc000, 0x002be000, 0x002c0000,
-       0x002c2000, 0x002c4000, 0x002c6000, 0x002c8000, 0x002ca000, 0x002cc000,
-       0x002ce000, 0x002d0000, 0x002d2000, 0x002d4000, 0x002d6000, 0x002d8000,
-       0x002da000, 0x002dc000, 0x002de000, 0x002e0000, 0x002e2000, 0x002e4000,
-       0x002e6000, 0x002e8000, 0x002ea000, 0x002ec000, 0x002ee000, 0x002f0000,
-       0x002f2000, 0x002f4000, 0x002f6000, 0x002f8000, 0x002fa000, 0x002fc000,
-       0x002fe000, 0x00300000, 0x00302000, 0x00304000, 0x00306000, 0x00308000,
-       0x0030a000, 0x0030c000, 0x0030e000, 0x00310000, 0x00312000, 0x00314000,
-       0x00316000, 0x00318000, 0x0031a000, 0x0031c000, 0x0031e000, 0x00320000,
-       0x00322000, 0x00324000, 0x00326000, 0x00328000, 0x0032a000, 0x0032c000,
-       0x0032e000, 0x00330000, 0x00332000, 0x00334000, 0x00336000, 0x00338000,
-       0x0033a000, 0x0033c000, 0x0033e000, 0x00340000, 0x00342000, 0x00344000,
-       0x00346000, 0x00348000, 0x0034a000, 0x0034c000, 0x0034e000, 0x00350000,
-       0x00352000, 0x00354000, 0x00356000, 0x00358000, 0x0035a000, 0x0035c000,
-       0x0035e000, 0x00360000, 0x00362000, 0x00364000, 0x00366000, 0x00368000,
-       0x0036a000, 0x0036c000, 0x0036e000, 0x00370000, 0x00372000, 0x00374000,
-       0x00376000, 0x00378000, 0x0037a000, 0x0037c000, 0x0037e000, 0x00380000,
-       0x00382000, 0x00384000, 0x00386000, 0x00388000, 0x0038a000, 0x0038c000,
-       0x0038e000, 0x00390000, 0x00392000, 0x00394000, 0x00396000, 0x00398000,
-       0x0039a000, 0x0039c000, 0x0039e000, 0x003a0000, 0x003a2000, 0x003a4000,
-       0x003a6000, 0x003a8000, 0x003aa000, 0x003ac000, 0x003ae000, 0x003b0000,
-       0x003b2000, 0x003b4000, 0x003b6000, 0x003b8000, 0x003ba000, 0x003bc000,
-       0x003be000, 0x003c0000, 0x003c2000, 0x003c4000, 0x003c6000, 0x003c8000,
-       0x003ca000, 0x003cc000, 0x003ce000, 0x003d0000, 0x003d2000, 0x003d4000,
-       0x003d6000, 0x003d8000, 0x003da000, 0x003dc000, 0x003de000, 0x003e0000,
-       0x003e2000, 0x003e4000, 0x003e6000, 0x003e8000, 0x003ea000, 0x003ec000,
-       0x003ee000, 0x003f0000, 0x003f2000, 0x003f4000, 0x003f6000, 0x003f8000,
-       0x003fa000, 0x003fc000, 0x003fe000, 0x003fe001, 0x00000000, 0x000001ff,
-       0x00000200, 0x00000001, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, 0x00007ff8,
-       0x00000000, 0x00003500, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
-       0xffffffff, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
-       0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000003,
-       0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
-       0x00000003, 0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
-       0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff,
-       0x00000000, 0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff, 0x00000000,
-       0xffffffff, 0x00000000, 0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff,
-       0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000003, 0x00bebc20,
-       0x00002000, 0x000040c0, 0x00006180, 0x00008240, 0x0000a300, 0x0000c3c0,
-       0x0000e480, 0x00010540, 0x00012600, 0x000146c0, 0x00016780, 0x00018840,
-       0x0001a900, 0x0001c9c0, 0x0001ea80, 0x00020b40, 0x00022c00, 0x00024cc0,
-       0x00026d80, 0x00028e40, 0x0002af00, 0x0002cfc0, 0x0002f080, 0x00031140,
-       0x00033200, 0x000352c0, 0x00037380, 0x00039440, 0x0003b500, 0x0003d5c0,
-       0x0003f680, 0x00041740, 0x00043800, 0x000458c0, 0x00047980, 0x00049a40,
-       0x00008000, 0x00010380, 0x00018700, 0x00020a80, 0x00028e00, 0x00031180,
-       0x00039500, 0x00041880, 0x00049c00, 0x00051f80, 0x0005a300, 0x00062680,
-       0x0006aa00, 0x00072d80, 0x0007b100, 0x00083480, 0x0008b800, 0x00093b80,
-       0x0009bf00, 0x000a4280, 0x000ac600, 0x000b4980, 0x000bcd00, 0x000c5080,
-       0x000cd400, 0x000d5780, 0x000ddb00, 0x00001900, 0x00000028, 0x00100000,
-       0x00000000, 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000,
-       0x00007ff8, 0x00000000, 0x00001500, 0xffffffff, 0xffffffff, 0xffffffff,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x00000000, 0x00007ff8, 0x00000000, 0x00001500, 0x00001000,
-       0x00002080, 0x00003100, 0x00004180, 0x00005200, 0x00006280, 0x00007300,
-       0x00008380, 0x00009400, 0x0000a480, 0x0000b500, 0x0000c580, 0x0000d600,
-       0x0000e680, 0x0000f700, 0x00010780, 0x00011800, 0x00012880, 0x00013900,
-       0x00014980, 0x00015a00, 0x00016a80, 0x00017b00, 0x00018b80, 0x00019c00,
-       0x0001ac80, 0x0001bd00, 0x0001cd80, 0x0001de00, 0x0001ee80, 0x0001ff00,
-       0x10000000, 0x000028ad, 0x00000000, 0x00010001, 0x00350804, 0xccccccc5,
-       0xffffffff, 0xffffffff, 0x7058103c, 0x00000000, 0xcccc0201, 0xcccccccc,
-       0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc,
-       0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc,
-       0xcccc0201, 0xcccccccc, 0x00000000, 0xffffffff, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x00000000, 0x00007ff8, 0x00000000, 0x00003500, 0x000e0232, 0x011600d6,
-       0x00100000, 0x00000000, 0x00720236, 0x012300f3, 0x00100000, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
-       0x0000ffff, 0x00000000, 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x30efffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd,
-       0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
-       0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3,
-       0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd,
-       0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
-       0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x302fffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd,
-       0xfffffff3, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
-       0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd,
-       0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3,
-       0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd,
-       0xfffffff7, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
-       0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x31efffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd,
-       0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
-       0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff,
-       0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd,
-       0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
-       0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x056fffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd,
-       0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
-       0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd,
-       0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
-       0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3,
-       0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd,
-       0xffffff8a, 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3,
-       0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd,
-       0xfffffff3, 0x316fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
-       0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x302fffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd,
-       0xfffffff6, 0x30bfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf314, 0xf3cf3cf3,
-       0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd,
-       0xfffffff7, 0x31cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
-       0x0020cf3c, 0xcdcdcdcd, 0xfffffff0, 0x307fffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd,
-       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
-       0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd,
-       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
-       0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd,
-       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
-       0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd,
-       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
-       0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd,
-       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
-       0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd,
-       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
-       0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd,
-       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
-       0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
-       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd,
-       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
-       0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
-       0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x00100000, 0x00070100,
-       0x00028170, 0x000b8198, 0x00020250, 0x00010270, 0x000f0280, 0x00010370,
-       0x00080000, 0x00080080, 0x00028100, 0x000b8128, 0x000201e0, 0x00010200,
-       0x00070210, 0x00020280, 0x000f0000, 0x000800f0, 0x00028170, 0x000b8198,
-       0x00020250, 0x00010270, 0x000b8280, 0x00080338, 0x00100000, 0x00080100,
-       0x00028180, 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298, 0x00080380,
-       0x000b0000, 0x000100b0, 0x000280c0, 0x000580e8, 0x00020140, 0x00010160,
-       0x000e0170, 0x00038250, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc,
-       0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000,
-       0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x04002000
-};
-
-static const u32 tsem_int_table_data_e1[] = {
-       0x00088b1f, 0x00000000, 0x51fbff00, 0x03f0c0cf, 0x19d9458a, 0x1138fc18,
-       0x5980a1fc, 0xd8181998, 0x88039880, 0x81b8803d, 0x91a18191, 0xdafd7891,
-       0xbf760862, 0x6ec30330, 0x0211e620, 0x1082239a, 0xf354029f, 0x0f5fc806,
-       0x6512b315, 0x3a263860, 0x06a77ef0, 0x298d2ade, 0xc1124536, 0x1e4586de,
-       0x93476f19, 0xca8922ff, 0xff4041df, 0x65296340, 0x229dbe54, 0x04a65e84,
-       0xe4d1a5a1, 0xd7f2a1ed, 0x5192fea1, 0x0dee6ec6, 0xf8003ca8, 0x6065495c,
-       0x00606549
-};
-
-static const u32 tsem_pram_data_e1[] = {
-       0x00088b1f, 0x00000000, 0x7dedff00, 0xd554780b, 0x733ef0b5, 0x49999cce,
-       0x424e4cce, 0x4c22f212, 0x21a08812, 0x8a80af0c, 0x2201277f, 0x282039f5,
-       0x4201d458, 0xd4837908, 0xcdedaf4b, 0x11102484, 0x0547f435, 0x5088768b,
-       0x340da2d1, 0x0ec160d2, 0x6d7b1420, 0xc0faf06f, 0x480bf5ea, 0xb12f3141,
-       0xcbc57e20, 0xe7dad6bf, 0x264ce664, 0xafdbd880, 0xb4fdffff, 0xece7d9b8,
-       0xebdaf7b3, 0x7b5ad7b5, 0x75923ded, 0xc7bf9302, 0x03fc45d8, 0x8c4d4fe5,
-       0xf2c109b1, 0x80f66667, 0xc9b18727, 0x473afebd, 0x6d55633c, 0x9da23b19,
-       0x99ec258c, 0x50281421, 0x2c23d5fe, 0xbfdf8250, 0xf097c365, 0x4219b6ff,
-       0xd0977c3e, 0xc3e611e9, 0x02d5e4fb, 0x933a876b, 0xea0c319c, 0x4b19b98c,
-       0x126b2c64, 0x4b223fa3, 0xe0ff828d, 0x8f392573, 0x27fc34b1, 0x61467574,
-       0xc678c0ae, 0x5c531e32, 0x38a9d0d4, 0x843f7815, 0xbcd2c67f, 0x0731b725,
-       0xbc03cf63, 0xbcf071c9, 0x61de3a5a, 0xc22eefe5, 0x3af3a1df, 0xae58cd6a,
-       0x32773e30, 0x416589a7, 0xf3e33ebf, 0x3d6346ac, 0x4fe3d99b, 0xec3fc346,
-       0x8c517ecc, 0xb1138f30, 0xcb3c018c, 0x632f0e54, 0x5467b2bd, 0x6a9b1f10,
-       0x2c32a258, 0x852f0f58, 0x56338765, 0xed975e03, 0xf8165c16, 0x2f6c39fe,
-       0xbed7e631, 0x15ead66b, 0xa362593e, 0xb50404a1, 0x67eff4e4, 0x11bfcb11,
-       0x2b30fef1, 0xea4ab2a0, 0xaf805595, 0xfb765aaa, 0x67edfe95, 0x54e88933,
-       0x5bf6b929, 0x5adefc61, 0xf1866ae6, 0x02d59997, 0x91fb2fac, 0x7a83e5d3,
-       0x21476366, 0x36d0fa83, 0xc1198981, 0x9e00afef, 0x007f91db, 0xa52b2a1e,
-       0x740642de, 0xb02bddec, 0x871c0ce6, 0x776cbbf7, 0x0c65f306, 0x6658e70c,
-       0x32e73826, 0x74893a41, 0xd2073071, 0xf324bcc1, 0xcea84289, 0xb0f3dc54,
-       0x9de29f7f, 0xe7f4ed87, 0x38e60b49, 0xf25700bd, 0x57a06650, 0x9d3ab5b1,
-       0xea563265, 0xbe442969, 0x8decb538, 0x9e025855, 0xf7c02413, 0x08a78b7c,
-       0x5798a9fb, 0xa780cd9d, 0x8d1859e6, 0xff2db43f, 0x0cf80933, 0xc4c5f3ba,
-       0x76313f21, 0xf04f843c, 0x5a11f1cf, 0xde981c5d, 0xb08b2b97, 0x05f1091f,
-       0x1f011772, 0x26a0423f, 0x544d28e0, 0x29fc573a, 0xd0a0d86b, 0xc3595bfa,
-       0xe50069c6, 0x3f0cbc11, 0x0843ac61, 0x1cbd4be5, 0xb0ff3bba, 0x3c303b94,
-       0x04f3d3ff, 0xab7e1274, 0x1fc8b700, 0xbfd97615, 0xca61f812, 0xf7c0e6ab,
-       0x362a3f80, 0xd40b7e0b, 0xe8dbaf4d, 0x5e26f77d, 0x3765d80f, 0x16d74ff2,
-       0xbdf00ba8, 0x1bf1fda5, 0x155ebf91, 0x3b763359, 0xfa84ca22, 0x3b06a4e5,
-       0xc0750f1b, 0x578db147, 0xbbef362b, 0x692fbf1f, 0xf41b30b3, 0xf17bb157,
-       0x7d42371d, 0xc33361f1, 0x6b5b1526, 0x2fa814e5, 0x582d0bf1, 0xf0e029ef,
-       0xfe8976f9, 0xc7bed0ad, 0x1b389ed1, 0xc6ba73e8, 0x63329cca, 0xc4f6f675,
-       0xa567c059, 0xf8851dfe, 0xc176e95d, 0xf29f6885, 0xc943d6ea, 0xb917af38,
-       0x8b6d977c, 0x7f1d4e66, 0xab64f7f0, 0xbc1ef818, 0x64f3065f, 0xd662efd0,
-       0xb07a8854, 0xd93aeb62, 0xebe20f69, 0xe34a8d74, 0x8bdfc9f4, 0x577c0e30,
-       0xc2e08af9, 0x989a5629, 0x7bb0e517, 0xf3ce6db7, 0x56afce0a, 0xbce3b6ce,
-       0x6ed8cb56, 0x2efe7fb1, 0xfea5cd54, 0xbc2172cd, 0x59b4dd2f, 0xdb910e2e,
-       0x8c836db2, 0x1ac86d70, 0xd7208dec, 0xd7807841, 0x52f583b2, 0x0fa803d4,
-       0x233cbf25, 0x852acf84, 0xb2cbe258, 0x1a73226d, 0xddd388f8, 0x13fc2ef7,
-       0x6bdbe5f0, 0x74eabc27, 0x1aa7d3eb, 0x1aa8cedd, 0xbcdea51d, 0xf8f81119,
-       0xc003a471, 0x827884d3, 0x9f06ad72, 0x97cb3263, 0x9b877fa0, 0x3cbb02a9,
-       0xd999365f, 0xf563067c, 0xd2dd07b0, 0xd99750f5, 0xf582e652, 0x7bb1fa50,
-       0x0493d42a, 0x9f3867ef, 0xc25bc17a, 0x2496abd7, 0x9579e00f, 0xfce0e6c0,
-       0x30d0218f, 0xc0c955af, 0xa6f7809f, 0x8bcf7969, 0x3c7b0682, 0xb17f8bd6,
-       0x39fa8326, 0xa198fd43, 0xf7cbac9f, 0x324e16a3, 0x9616a3f4, 0x8dfcfde8,
-       0x595db1fa, 0x37854d3f, 0x2c29e118, 0x0491fbd5, 0xbf6f5768, 0x37a979b2,
-       0x73c2364f, 0x13f53973, 0xbcc5d53b, 0x1ae7ae0a, 0xb776b03f, 0xed95ef08,
-       0xb0d763b1, 0x5028be50, 0x0edb8005, 0x17ca1252, 0x0ca29331, 0x8eeb187c,
-       0x27a1d433, 0x4175e4f5, 0x958813fd, 0x45397c69, 0x9f90bd26, 0x43faa562,
-       0x85e90a29, 0x5ef06e87, 0x8e20eb83, 0x2ea192cd, 0x11ab477b, 0x14e01af8,
-       0x60961258, 0x7ff52417, 0xf1ccdabf, 0x217a9050, 0x5f7c18fb, 0x8ecdea65,
-       0xa635fa85, 0x6f116bfc, 0xe5eb812e, 0x63559128, 0x230b28bb, 0x233ab4fd,
-       0x085f79ef, 0x00871a9e, 0xbf6085fd, 0x126f668d, 0xdaf8d7f2, 0xc0127c67,
-       0xcc086ab7, 0x12ba0527, 0x60f8099e, 0xa43d5a3d, 0x69f10938, 0x43be4191,
-       0xfc6197c7, 0x06ff1a1c, 0xc71ba3c4, 0xbe3fe84f, 0x61927325, 0x897a6b7c,
-       0x0cab7c61, 0x4fbf03e3, 0xc6d66dad, 0xc0ddfc07, 0x99a134d8, 0x97a4b7c6,
-       0x65abf8d0, 0x3f186256, 0x5bfc6faa, 0x819efe70, 0x83799fe6, 0xa5e9fe71,
-       0x7ccbf9c6, 0x5f6ab3fe, 0xa28fc6d2, 0x5e16cff9, 0x2f4ff3e2, 0xf0b7f3e5,
-       0x77c6fb7e, 0x5effe1f4, 0x8077bf9c, 0x93592df1, 0x5a1ff38d, 0x85bf9c6e,
-       0xbb545f8f, 0xa15f1b53, 0x3b0917f1, 0x9687fcf9, 0xc5b2f8d3, 0x923e42eb,
-       0xfdaaa353, 0x81a44f68, 0x1d260c40, 0x0472a6e5, 0x1fa00518, 0x04990a86,
-       0x9c5143c7, 0x0145ceef, 0x7d4129bf, 0x5120fcc7, 0x352acfa0, 0x9edb2f9e,
-       0xa59ea32f, 0x376889f7, 0x6d453ff1, 0x6c37ad22, 0x1c3fc5bd, 0x136eede0,
-       0x5a2f587d, 0xa45f937f, 0xe5db8ef5, 0xf005c660, 0x1c9e5ff9, 0xaf3a1cd5,
-       0x935172f0, 0x418764f9, 0xbe3c388e, 0x1aa23602, 0x26476be0, 0x9fac1098,
-       0xc60a3d04, 0x7a0e3b2f, 0x6653cb14, 0x009c8f6e, 0x50e4cb3d, 0xf6e5a9b9,
-       0x93bd8f88, 0x5bbaf303, 0xc4a4ff83, 0xb9727df1, 0x9ffc47e0, 0x4654b75b,
-       0x09a8b4fd, 0x7910e98c, 0xd4e8d2af, 0x6fe2dbbb, 0x4e9f0816, 0x243dcfc4,
-       0x97fd8c8a, 0xde2fd766, 0xddf0c830, 0x486fe63c, 0xd70bf682, 0xc2a21fce,
-       0xc7307ffc, 0x53ed1632, 0x13548490, 0x354b31c9, 0xa7316f81, 0x15399d75,
-       0x31ccf72a, 0xb9faec1b, 0x07fd635e, 0xb77ac625, 0xa1366fd9, 0x6044b1bd,
-       0xfbdfa19b, 0xf5ef8daa, 0x71093671, 0x78daae9c, 0x78722777, 0x2c72c3ef,
-       0xae89563e, 0x5bfcabf7, 0x87aa9e1d, 0xeb402ccd, 0x43024765, 0xc812fa3a,
-       0x7caaf35e, 0xdef0e1de, 0x3dbab66f, 0x3ffdcf00, 0xe19f0912, 0x1ebc77f0,
-       0x1d8136ed, 0x4be1b1d7, 0xe1b7da33, 0xff8709f3, 0xf3e11581, 0xf7d46551,
-       0xcfe17df3, 0xf3849f39, 0xfe5b5553, 0xed2113a0, 0x3fbe5a2a, 0x7f0844e8,
-       0x619b6d95, 0xcff12fa8, 0xbc5fb435, 0xfde1be61, 0x8625a6a2, 0x971b0bf7,
-       0x7df3ea1a, 0x7fb4323f, 0xe1ad4560, 0x8fd57dfd, 0xa0ffde18, 0x3ea19d64,
-       0xd0d1bbd7, 0x9b399efe, 0xaf4def0d, 0xe513bc8f, 0x915deea8, 0x5671bae1,
-       0xda38f939, 0xc9156783, 0xb4f8f485, 0xe0e48926, 0xca938d74, 0x5671b6ee,
-       0xc583d72f, 0x5e9c4c0c, 0x71af9ce1, 0x4665ea32, 0xc2aff3fa, 0xea0f9f05,
-       0x849c137f, 0xcc83713f, 0x02c2c002, 0xe3e3eb8b, 0x7de4315e, 0x6fde65c7,
-       0xd71f4100, 0x11d8bdff, 0xf35579f9, 0x046aa1fc, 0xb72821ff, 0xb9d7152c,
-       0x0f7d6d1e, 0x302e5f7f, 0xc673e84f, 0xd79c9256, 0xb94ceb69, 0xf941f5cc,
-       0xf402e4ce, 0x40e5cbbf, 0xc6a5f576, 0xa2a4016b, 0x3ceb449e, 0xa401f901,
-       0x592fc0c0, 0xdceef906, 0x955c1227, 0xaf4013a8, 0xc19e63ae, 0x8133d426,
-       0x8d77e903, 0x49dc3842, 0xa04b6f54, 0x66b3bd75, 0x1213a0fa, 0xe543c7d2,
-       0xa87335a7, 0xa5e3593c, 0x094d44f2, 0xaa6bc795, 0x59a8eca9, 0x35c7e541,
-       0xaa3f2a3e, 0xcff2a469, 0x1e544d35, 0xe540d9ad, 0x2a7e357b, 0x54dc6bbb,
-       0xba2bf9f6, 0xecd78dfe, 0x80afcd55, 0x67ea8795, 0x43d4b9b4, 0x739276db,
-       0xf9ca1257, 0x365ce519, 0x8e67e3da, 0x31996382, 0xf9c2be30, 0xba3a606d,
-       0xf6295ec9, 0xf5c7fd03, 0xe28b6f7f, 0xd899b274, 0xd9a67074, 0xe17fc323,
-       0x7543905a, 0x16065909, 0x7b0cd724, 0xed617e84, 0x8e5d7a43, 0x9bddcc4e,
-       0x71e8133b, 0xe5bf99f2, 0xda75bf61, 0x407517fa, 0x059875a4, 0xbd21779e,
-       0xeb46f042, 0x9aabef5a, 0xfe0cbfbe, 0xd7f0faba, 0xfbfe8e9e, 0xfea54141,
-       0x985ab4cf, 0x13dc7884, 0x67e607ed, 0xef3f0e67, 0x965c7940, 0x444f5264,
-       0x565e83c0, 0x4aa864b4, 0x66d3fae8, 0x12699fac, 0x7ad0b7a6, 0x35998cec,
-       0x554af90a, 0xfa430c4f, 0xf7a95127, 0x56492cb3, 0x9ebc804f, 0xc31596de,
-       0x5f3f6fd7, 0x12c7b707, 0x485f82bf, 0xf0deffed, 0x0e8fd40c, 0xecad630f,
-       0x03ea2b13, 0xedf59778, 0xfd2672fd, 0x6c57e295, 0xda1cf98f, 0x7bf8160b,
-       0x1207e291, 0xab7ef5d5, 0x659f445a, 0x6edf3e34, 0x73be0f18, 0xc5f73eea,
-       0xadf14bcc, 0xc4864ec4, 0xf169d611, 0x366db2c6, 0xc4aeb8d5, 0x6d55ea1a,
-       0x9d61aac9, 0xfc807fc1, 0x42416ab3, 0xb8d729be, 0x1a5247a8, 0xdcaf8005,
-       0xab7ea4e4, 0xc2aede04, 0xe17b21da, 0xa72b5751, 0x9df040db, 0x94ec39ae,
-       0xac4bde40, 0x7c0201e0, 0xa7232d25, 0x6aeb9ea2, 0x7b444bad, 0xf33c4cb0,
-       0xf7c22790, 0x8d024d3b, 0xee6fc4b7, 0x1aa3ae35, 0x57e8307f, 0x167e4e7f,
-       0xd4864e53, 0xcedc4d3b, 0x80f7ef0e, 0xf0e5efd6, 0x48fdb953, 0xfece8de1,
-       0xfb6caa78, 0x1c92f642, 0x82f2ffc1, 0x57f1d278, 0x401cf26e, 0xedba5a7d,
-       0x9fa3d918, 0x0fd97d9a, 0xf53f425f, 0x44929f9f, 0x5e7d5271, 0x6129303e,
-       0x7c5a059c, 0x9ef7f817, 0xfd3d610f, 0x6ccddfec, 0x2ec7c00d, 0x6f782b40,
-       0x13335fd6, 0xa17d4133, 0x5ad05b56, 0xcfdd7146, 0x2a8edc4c, 0xd1071e62,
-       0xa1e53581, 0x4cc5d91d, 0x5d4f11d3, 0xb8c76dec, 0x329c3a10, 0x1667a4c9,
-       0x18ed1a36, 0xf50d7fb0, 0xf58c1bc5, 0x11333662, 0x7af149f5, 0x340bf333,
-       0xf7fbc33f, 0x7fe12a4d, 0x855eab31, 0xf9a4aaeb, 0x26540b23, 0x157c02a5,
-       0x6f3679bf, 0x4c5fc63e, 0xe3d10fdc, 0x38e24b23, 0x7ef1a5fc, 0x3fef0dd9,
-       0xf7771d69, 0x8b06488d, 0x89c6157f, 0x6d730c58, 0xfbf1fd65, 0x870fe16d,
-       0xfbaf5f57, 0x383469c5, 0xdb826dc4, 0x2f7f811f, 0xeba67c68, 0xd5445beb,
-       0x8ddc17e0, 0x21bf10f5, 0xb2e2d446, 0xee911322, 0x67d5aa5d, 0x14f7a18a,
-       0xb4edf7b7, 0xde80eab8, 0x0679373f, 0x4ec81389, 0xed2165c8, 0xd2f26e7e,
-       0xade14ef3, 0x995bb462, 0x3b45c814, 0xe218d614, 0x07e35953, 0x8b91ca31,
-       0x833b66f1, 0x6fe81475, 0x9fa0f841, 0xdb92f655, 0xbbc62e58, 0xbfa1de41,
-       0x87851cc7, 0x94dba805, 0x59fd8656, 0x7cf18c92, 0xaf58d39b, 0x1d207fc2,
-       0x3f8a3046, 0xc2908f45, 0xa86018f0, 0xe32eed0f, 0x84e851f3, 0x201fdd91,
-       0x8b10763e, 0x02556943, 0x26cf8c22, 0xfe7d9d49, 0x7bfa2656, 0x2f8a7e1c,
-       0x2ae5fb40, 0xc5a95f6f, 0x507f97cf, 0x12ee3830, 0x3ceaa8fa, 0x21419068,
-       0x7fbe3d75, 0x71fe625e, 0x3a6f41df, 0xd10d5561, 0xde4d739b, 0xd40f4869,
-       0x009f0893, 0x760d78e3, 0x2a1a9a60, 0xf8c20be7, 0x88e1aae3, 0x5dfd0667,
-       0x2ddef26e, 0xe387f426, 0xea4ffbaa, 0x4882ffd7, 0xfeeabcf3, 0xbfebf587,
-       0x15ff5232, 0x977979bf, 0xf4a9f80f, 0x803a4f57, 0x5267d999, 0xe80ba253,
-       0xc1b5be5e, 0xa9f97281, 0x5d2073e4, 0xd38bf33f, 0x16e7c923, 0xb74f9751,
-       0xff11e422, 0x7e9d1f10, 0xd03bd1e9, 0xd5b73aae, 0x607c52ac, 0x0160259b,
-       0x5d6caca6, 0x9b63e5c2, 0xafaf18e5, 0xb3f902fe, 0x2fa8cdaa, 0x32785f4a,
-       0x40cde311, 0x0e7fcd49, 0xb9507f90, 0x68852fe5, 0x5eb15577, 0xdfe17bd2,
-       0xe3e7f8e1, 0x2f981ec8, 0xaf7ff4c7, 0x6955f3ef, 0x7d6aa978, 0x84910bf4,
-       0xcdfc83a5, 0x9a25f6f0, 0x68a4ffbd, 0xdf38a78f, 0xf9113644, 0xf307c74c,
-       0xeebf7b73, 0x8f73a7c5, 0x5b9d3c01, 0xe421ddfe, 0xd727f284, 0x165a677b,
-       0xe735fcfe, 0x0dd4f2c0, 0xaed4317a, 0x6767d7d6, 0xeca7e69b, 0x39b965e1,
-       0xb03f40e0, 0xe5d9b37c, 0xfcbeba43, 0xc19e2ffc, 0x1607ccb8, 0xbfe870d7,
-       0xef83e5ec, 0xb2f500dd, 0xdbf8e61d, 0x211434f8, 0x2a974831, 0x6c62bbf8,
-       0xbfa50e90, 0x473b283e, 0x8e3fe7f1, 0x6ca3d20b, 0x8d993ec7, 0x298f8fea,
-       0x0ee4fb2d, 0x5a5d0225, 0x3fa2158e, 0x57e2f751, 0xcfafea32, 0xe0d8175e,
-       0xdcf8088c, 0x62ec907c, 0x51d113c4, 0xdd1f53a3, 0x0157dac2, 0xeabf505d,
-       0xff7f0a74, 0xc7fe9a2f, 0xc4399cfe, 0x86bcafcf, 0xb67f28fb, 0x25fe70b8,
-       0xc0e83caf, 0xaa929c79, 0xdb3f5f39, 0x7186e890, 0x44becc4b, 0xbcfe4a95,
-       0x121fb9e4, 0xf23e2dbf, 0x7f8a44c3, 0x89b27730, 0x325f056c, 0xa6d16fce,
-       0x62bf34d9, 0x2bbe25e6, 0xe0f45679, 0x8959e0fe, 0x4111df4d, 0xae24522e,
-       0x5b354f8f, 0xa7654d70, 0x7dc0e170, 0xff45b785, 0x2dff8a56, 0x0fcaf8a5,
-       0xb620fdf5, 0xad67ea8c, 0x885f4e9c, 0xac1abefa, 0xbafca13c, 0xd23b7565,
-       0xf710f4e7, 0x571b8c60, 0xe1a7c931, 0xfd08b843, 0x0da6478a, 0x4e61f4e6,
-       0x0efb4f29, 0x7c14fdf4, 0xcddbed8e, 0xe1ae5b6e, 0x2331763b, 0x6d72fe38,
-       0x0a3b807c, 0x8953d5ed, 0x9845ff60, 0xafa4a15f, 0x85576037, 0x7c8857f0,
-       0xf2df7973, 0x5d6f9708, 0xa633fdde, 0xbebffbe3, 0xbf07e5c3, 0xe0057b43,
-       0xf7a60c0a, 0xa40966fb, 0x102c2c0f, 0x98b7ae49, 0xbe36b935, 0xe004f9d7,
-       0xeddd7096, 0x3fec17e3, 0x764ff08e, 0xf87af16c, 0x565f442e, 0xfe8e78e1,
-       0xbb72e9fd, 0x04ff9358, 0x6cff28c9, 0x81fb9713, 0x8f1f09fd, 0xbffd984b,
-       0x15e50678, 0xaff713e4, 0x7b365fcb, 0x6f9fde70, 0xbddef03f, 0xb79fa720,
-       0xd46a72e8, 0x5a72e19f, 0x8b0273b2, 0x639fa724, 0x3924421a, 0xe511e785,
-       0x3e20e954, 0x4fe947fe, 0x85377f1d, 0x87d74fe1, 0x5c31e103, 0x7459fe1f,
-       0xf087d446, 0xd7961de7, 0xbe74ff9f, 0xf4adf9d3, 0x29431597, 0xa5f3a63e,
-       0x7c7d77ce, 0xbf5df3a9, 0x7f01a378, 0x182defe1, 0x3cb80183, 0x4714cdbb,
-       0xf7c3df28, 0x43bbe17f, 0x4f09e3a9, 0x58c65a6e, 0xf8d4a1d3, 0xac3fbad0,
-       0xded612de, 0x84f7561d, 0xd586f7b5, 0xcbed0dab, 0x3cc80edb, 0x686025af,
-       0x8678ae27, 0x1228327d, 0x5fb9fabf, 0xec85fada, 0x7a50be43, 0x4af37be9,
-       0x3c63b3e6, 0xf148af7c, 0xf1c01e91, 0x67a7182a, 0xf31f867b, 0x3c6c1a24,
-       0xf6a3d4ee, 0x6c5ed03a, 0xdef5e588, 0xea157904, 0xaf79fd3d, 0x7af5c78d,
-       0xd88ebd3c, 0xd8edfb10, 0x76f4911e, 0x8f4d9f87, 0x8ac267e4, 0xc1d47242,
-       0xe3cf7a06, 0x2544d3fd, 0x5fc6057d, 0x8617449a, 0xef6a8a74, 0x419e6071,
-       0x3bac9ecf, 0x45f3c0e7, 0x8db48a6f, 0x7b7683d8, 0x2dc7920c, 0x77f88725,
-       0x53df329f, 0xbf7e3193, 0x4579fb87, 0x11ecc36b, 0xa9f896b6, 0xa32e5958,
-       0xecbf053e, 0x82ff71b8, 0xd6a945cb, 0xe326c95f, 0xdc7bfd7b, 0xbdfb45c1,
-       0xbdf18b74, 0x34078b57, 0x863272eb, 0x71fcd18d, 0xf4d28f1e, 0xe73134f2,
-       0x8f4039ce, 0xc322c39e, 0x7b33fbfd, 0x99c7a244, 0x9ebf7ced, 0x23d7f6e2,
-       0x3e92f77f, 0x89d4f1d4, 0xac0f24f2, 0xfd5f3aaf, 0x9187bcaf, 0x987d766f,
-       0x3b2833fb, 0xfd907d77, 0xe6ffac5b, 0x590ff4fd, 0x5e53f6ff, 0x493ed1b7,
-       0xe276ebcf, 0x7fbd9ef7, 0xeb187f4c, 0x9f142dbb, 0xabfd79ee, 0x9e9fe45c,
-       0xd4129695, 0x80433d77, 0xec1f68fe, 0x83b72afd, 0xa27ad7d6, 0x99251fdb,
-       0xfe7b47db, 0x8f10b1f6, 0xed0acc25, 0x49a3d786, 0xb35eaa9e, 0x67ad3c51,
-       0xa17957ef, 0x9d77ff76, 0x7fb6a54f, 0x736763d9, 0xb17c2276, 0xeaa7df7c,
-       0x5f3fd7b7, 0xad17f98b, 0xf085e4fb, 0xbeefca7e, 0xda3d45c9, 0x43db93b3,
-       0xe78ee6dd, 0x68ee7f70, 0x6695dcfd, 0x0a3773c0, 0x9bac0a55, 0xa014cf0d,
-       0xcbc7f4dc, 0xbc271437, 0xfcf47c52, 0xc10f835f, 0xdd9df5cd, 0xde70156f,
-       0x21fc7f5f, 0x2dd785ea, 0x7cfa97c4, 0x25a96f3f, 0xf372e57b, 0x9c799876,
-       0x799dffe4, 0x992b810b, 0x3ff328f7, 0x2d7fbd37, 0xe12e8939, 0xcf9fd072,
-       0xf5443ef7, 0x822eed97, 0xfdf90af7, 0xf9f27ff6, 0xefba6b7f, 0x2e3bba04,
-       0x7ff2ef3f, 0x4c0f79f2, 0xd7ef37f7, 0x7e62aee8, 0xbeefd54b, 0xadbef821,
-       0x4ffb5b9e, 0xcd03ef2e, 0xd7ebb75f, 0x994d5c98, 0xaf439f18, 0xc569d601,
-       0xc311b33e, 0xcc466b85, 0x14ced154, 0xf52bf6c3, 0xfb99af72, 0x5bee224d,
-       0x086f9c62, 0xcd31f38f, 0x3d2da28f, 0x8a525a18, 0x94958ec9, 0x96bedc55,
-       0xc06eed5c, 0x176b9acb, 0x887728b8, 0xc5ea3d8d, 0x1764da7a, 0xfcc3afc5,
-       0xb9817ac9, 0xa56fb005, 0x8c396f6b, 0x84798dfe, 0xa5c96029, 0xab9618f2,
-       0x59a4b8b5, 0x8f7e0d95, 0xdbac6392, 0x45bac69c, 0x38cacfeb, 0xe624d6fc,
-       0x38b4f8c7, 0x798abf72, 0x8918e26d, 0xb1b75009, 0x17fa1f26, 0xf7e32496,
-       0x1ec0311b, 0x5abdcf12, 0xe1f6f63c, 0x1bbb6c71, 0x44d238f1, 0x2e4a6b71,
-       0xfcb8bc25, 0x8d9e786b, 0x55d788d5, 0x094f88ed, 0x7f6e5ffd, 0x34ccdf91,
-       0xbad2597f, 0xdc984690, 0xcd3b6336, 0x9d2cbe4f, 0xcbd25d38, 0x332d3a35,
-       0x43a745d0, 0xe818fa04, 0xdbf9e3a2, 0x2e9c27d2, 0x6fdff8e1, 0x07fe1276,
-       0x974e97a2, 0x50cdc534, 0xbf9acd5e, 0x49fd1530, 0x1879a7ac, 0xfe6b33ed,
-       0x66ef1482, 0xea93a43e, 0xf42f4862, 0xb7e002db, 0xf3fb7efd, 0x7aea2714,
-       0x081dd8e9, 0x456fd94f, 0x75fc0566, 0x00b3b76f, 0x65f92f7e, 0x5b4b43f4,
-       0x33fb8a45, 0x57779029, 0x6eafbec8, 0xcafd97f7, 0xdd29f34e, 0x06dff169,
-       0xfaee97df, 0xb0ec9724, 0xd7e4bd95, 0x38125ef8, 0xb91d7ddd, 0x2a5bafb8,
-       0x9c23ff71, 0x9e65625f, 0x3bb9d027, 0x6dc60e7a, 0xdf3c6d84, 0x1ee5b4b6,
-       0x7f90c5b3, 0x91dbd666, 0x28bdf05e, 0xc213be50, 0xa9e79a17, 0x2f9d1dfb,
-       0x36be1c0a, 0x76f31fb3, 0xe8edb74b, 0xe953f8c6, 0xc30b8b51, 0xbedb55d2,
-       0x298dfda0, 0xd1d97abf, 0x68b6fe41, 0xf3f43f88, 0xc489b7fb, 0x15ad951f,
-       0x9d4087e4, 0x25b2a2f8, 0x72ebfc72, 0xafd969fe, 0x01f2eef6, 0xfd7ecb0a,
-       0x5be30382, 0x3ab7dba7, 0x76dfffc8, 0x3f5bb8e9, 0x91e5bf3f, 0xa7f9fa4b,
-       0xbfe01ff1, 0xc58720dc, 0x220db649, 0xcbe0047f, 0xadef948b, 0xcbd95bf3,
-       0x38c39f67, 0xcfcee774, 0xcb78439f, 0xe7cbfbff, 0xaf609fd0, 0x88add4db,
-       0xa5de9797, 0xddfe9e38, 0x9dc7992c, 0x817c5fbb, 0x1fdd9fe2, 0x7f01df80,
-       0x4a9ef7ba, 0x7bb27f47, 0x1889d7c7, 0x77be592f, 0xef9c60da, 0x0ca757f2,
-       0x88f41166, 0xfadf225e, 0x1afe20af, 0xad03af4e, 0xe9efc807, 0xdfa37a02,
-       0x69b717d9, 0x3071e0a9, 0xd9af16a7, 0xddce391e, 0x7ad33e2f, 0x8d379dd7,
-       0x72ecd2c7, 0xd3882bb2, 0x1c7403bc, 0xdbf4057d, 0x7fe688fe, 0x175fa646,
-       0xb4e803fe, 0x677e8c2c, 0xfcfd175b, 0x3ad77c19, 0x4d38c068, 0xa6f00ae0,
-       0x27bfd1c7, 0xa3227fbb, 0x25fced7c, 0x6e90c5c5, 0xbb44c1b7, 0x8e9b3e5f,
-       0x9a9f0ffb, 0xe7e7ef7b, 0xc62a2c32, 0xbef74a1b, 0xfdd3f24f, 0x538a11ea,
-       0xdd9e2d33, 0xf0fefacd, 0x5396a3f8, 0xcec5b559, 0xfe1a3be3, 0x74e3fe31,
-       0xce2d73d0, 0x8f58f9c3, 0xf7140cff, 0xde799569, 0xafdf1e88, 0x16a1f2d8,
-       0x4bd2094f, 0x3a748498, 0x08fdc976, 0xe22a0f1d, 0x1c686261, 0xad7c7233,
-       0xd1adde2f, 0xf187e90b, 0x2538becb, 0x6e30d3d4, 0x67de17e5, 0xf741f411,
-       0xecff1e66, 0xa3ce4736, 0xbf9ae3d2, 0xff53970a, 0x2f33c595, 0xc5b7ff07,
-       0x52765f8f, 0xea78e1bf, 0x8f5910bc, 0x75f32dbf, 0xc5f7aaff, 0xbe4305ca,
-       0x7bc9b941, 0xa2b1f904, 0xcfcc98f5, 0x52f3f0a5, 0xb53b7cfa, 0x97ced1bc,
-       0xad778a44, 0x7a40396a, 0xe85f5c3c, 0xf0e1a6fb, 0xade0d09e, 0x44ebe36c,
-       0x5fbb4ee7, 0xf73a7e81, 0xae7e26ef, 0xe28c7edc, 0xfdb6876d, 0x5908ee5a,
-       0xf09d7157, 0xf9dfc087, 0x1e5cbeca, 0xec79e5b7, 0xd19ce3e1, 0x9ed561f4,
-       0x6d54e3c8, 0x4e30c2ff, 0xe645af99, 0xc7a5fdeb, 0xefb92d3b, 0xb74efec1,
-       0x79e6199b, 0xa7116e9e, 0xf5173a47, 0xea6eb6ae, 0xbd707ee7, 0x23fd7ca4,
-       0xf8cc5cfc, 0x1f28a3b7, 0xe991f97e, 0x63c4c61f, 0xfe878409, 0x9f396b5a,
-       0x9dc4feb6, 0x3d6ef48a, 0xeb88af72, 0x6fc42ed4, 0xf79f9d88, 0x3b14f54e,
-       0x8fbc85e8, 0x5d91e33c, 0xc4cdf5c3, 0xfc0326a3, 0x5c60ce30, 0x1fa1ea07,
-       0xf982a73c, 0xe88f086e, 0xf08e9c28, 0xb549aa88, 0x61e7fd09, 0x5e743c56,
-       0xacd7ef40, 0xb003cf1a, 0xd89ce30b, 0x1e4cd24f, 0x8bbe4c47, 0x3cfd3e97,
-       0xbf94714e, 0xa059e60e, 0xf02cd378, 0x7d7d927d, 0xe78641c6, 0xde5126bf,
-       0x78c59676, 0x554bac6e, 0xdfd0267c, 0x596ce4cf, 0xf949d937, 0x4258d707,
-       0x20580ff3, 0x6f51f917, 0x587defd7, 0x7e1a427e, 0x1a88fd02, 0x7e5a597c,
-       0x21d610c2, 0xc9bd7da0, 0x0e27cfce, 0xf84de255, 0xbd9af3fd, 0xec3f9fa9,
-       0xec315e77, 0xcee5e29c, 0xc94fc627, 0x05d43a5f, 0xcf7ab4fc, 0x8f5fcc14,
-       0x477f27bf, 0x12798aaa, 0xe7829e7f, 0xc85fe257, 0xf50c931f, 0x9c1fab13,
-       0xc8fff54a, 0xf50e931f, 0x8dff1a6f, 0xca04cbd7, 0x3d582d57, 0xebf22a7a,
-       0x2cf9cb55, 0xce5188c0, 0x75bc40ef, 0x7bba3e79, 0x1ff31391, 0x5f8e657a,
-       0x4376c1e6, 0xa5bc7126, 0x40ed1f29, 0x75350d3c, 0xfe7f22d4, 0xb157ef7c,
-       0x4c9c17a8, 0xaca8fc25, 0xc1fa455e, 0x2f1749a3, 0x9e174791, 0x93eba64f,
-       0x01f78acd, 0xf991e384, 0xe05ce823, 0xad332533, 0x98cf5f3c, 0x78d4c0c7,
-       0x469167a2, 0x1ad3844f, 0x58bf8f92, 0x5cfcc9f4, 0xafa6934c, 0x9e38aaa6,
-       0x2f172be0, 0xe1edf75e, 0x4be7507a, 0xc8695ced, 0x1087c679, 0x7de29f5e,
-       0xffd092c8, 0x161de33c, 0x9f7c0acf, 0x1d3e7c5c, 0x9f3f5bf9, 0x91ce7e18,
-       0x48a6bd49, 0x76b35ff6, 0x782071ce, 0x2aef563d, 0x77f3371c, 0x41879dce,
-       0xc91746be, 0x1ccd4c2e, 0x827c62bd, 0x5215cfc4, 0x4695439e, 0x971324bf,
-       0xa310f643, 0x8b1ed67d, 0xb9bf46e0, 0xf49541e7, 0x6dd15a77, 0x44f557e4,
-       0x3e60b467, 0xfcc3cf50, 0x4c66295c, 0xd90d1ca3, 0xbf401313, 0x5ce0e40f,
-       0x339c1c98, 0x71c673ae, 0xdb3a2e7b, 0x553fa83a, 0xb00c0feb, 0xe0b9e0c4,
-       0xe5eb911e, 0xc1271a9e, 0xf6f98431, 0xa57efae1, 0x18b56de3, 0xde02fdcf,
-       0xe8bc405f, 0xc0e5ff78, 0xa3457bf4, 0xe8912bdf, 0x74fe7e17, 0x6bfbc5be,
-       0xf8aa7f6c, 0x15742ad0, 0x869dcfc3, 0x6a4ab5d3, 0x78ae88da, 0x682f9ee2,
-       0x36e9d19d, 0x412b857a, 0xe3a0641a, 0xe8efd8eb, 0x10985f3d, 0x4f7e9d5e,
-       0xfdef900f, 0xcf5f0b07, 0x9c4bc7c2, 0x8de291d3, 0x1060feb4, 0xcf58212e,
-       0xf8d1e6b5, 0xde3c4d83, 0x10bdbfd3, 0x7fd03e71, 0x30f2a5e6, 0x2fde5573,
-       0x50fdffe0, 0xf110ffbe, 0xfe22223f, 0x03bc463f, 0xf6c63ffe, 0x4fff8057,
-       0xdd7f852e, 0xf4d32fae, 0x2bee1942, 0xc5fcff01, 0x13313339, 0x15142dc6,
-       0x5b25ffe2, 0xd21f6d45, 0x62725b7d, 0xb92c8f50, 0x199f7abe, 0xb3c970f8,
-       0x9169f102, 0x73fd5e76, 0x784b5ced, 0x1cf15f5e, 0xcbc9e91f, 0x49f9f7e7,
-       0x336d950f, 0xe410bf3e, 0xc7ca74db, 0x93f3f1f5, 0xe11726a2, 0x68a33ff8,
-       0xd628a2fa, 0x0e9c2ed0, 0x864daa43, 0x29e4f03c, 0x9f90fd7d, 0xbe726497,
-       0x3fb5f14f, 0x07c61998, 0xf8fc52dc, 0xbc63e200, 0xcdfb1530, 0xef56e4d7,
-       0xe30ae86f, 0x33e19f3a, 0x6acbfb9e, 0x1bfb9e34, 0x686294de, 0x4c86cd7f,
-       0xfe91fbc3, 0xafef0d6b, 0x50d636db, 0x8372d51f, 0xb6e8fda1, 0x4c7d4302,
-       0xfb4316e0, 0x1a678771, 0xefda13ea, 0x789fb435, 0xfde18174, 0x86a51df5,
-       0xba7e37f7, 0xa9bf50cc, 0xed0d5ff7, 0x5eb88b03, 0x94935fdc, 0x740ae786,
-       0x2a5fecbc, 0xbe7c549b, 0xe6a4db34, 0x744f3e86, 0xccb1733b, 0x357fa373,
-       0xb14cbc90, 0xae85a726, 0x6cccf9cf, 0xac536bd0, 0x55817ac6, 0xe07497e3,
-       0xcdfe2017, 0xa55ca356, 0x026bcf56, 0x2ca59bb3, 0xd2f94619, 0x58b75f20,
-       0xc5bb7eb9, 0xedfa657a, 0xaa7f6c4e, 0xece74032, 0x444be5c3, 0xd2a2caf9,
-       0xcca9fb47, 0x1b96f945, 0x4d3e466d, 0xccaf401a, 0xc3cf1ab3, 0x9b61ea8b,
-       0xfd139064, 0xd0a8f9f9, 0xdbe2c2e7, 0xa0676f28, 0x05a4e57e, 0x7d016eb7,
-       0xa97b2729, 0x9aaf9fd4, 0x97988a63, 0x3bf590f7, 0xfa1b49fa, 0x210f4fd9,
-       0xde92bb7e, 0xccf30a7e, 0x92f5e72a, 0x316c94bf, 0x775825e2, 0x5479e60d,
-       0x508e7e4e, 0x54dcffe5, 0xae2b78d3, 0x173cfaf7, 0x1133307d, 0x06d203f3,
-       0xd55e9ff0, 0x4d5cf1e6, 0xc345adc9, 0x14d53fb0, 0x7a45bf7a, 0xfd10aaa0,
-       0x1e5aa198, 0xc8a653f4, 0xd53f4af9, 0x0a8c19fa, 0x5503ed14, 0xaba0fb21,
-       0x048723f8, 0x9377f8f3, 0x17c8a7f7, 0xe7b7460b, 0x6ecb73f1, 0xabb24cd7,
-       0xd75f8254, 0xe78ae943, 0xe92bd429, 0x66731249, 0xf06787f4, 0x06636f3c,
-       0x338fafbc, 0xf7aa14b9, 0xe59e380a, 0x820d8cc7, 0x5bffeaf1, 0xf7eaf824,
-       0x3cf94f5f, 0xe29aa516, 0x993cfaa7, 0xc7afdfb6, 0xcd26cf8b, 0xd63c418a,
-       0x6e77db5f, 0xacfd6187, 0x7ec76de2, 0xd337aecf, 0x8205f5b8, 0x6f3ebde1,
-       0x741dc369, 0xe15d2b1e, 0x79862ef3, 0x3496dc23, 0x73fd570e, 0xb8234b02,
-       0x43d2f7fe, 0x8aecbfe8, 0x0dbc6176, 0xe889b1f0, 0x6738ceed, 0xf30f27d2,
-       0x34a418aa, 0x25fb21af, 0x96fa1fb2, 0x4cdbaf95, 0xf688959d, 0x4635f254,
-       0x66f5c5b8, 0xc51707f2, 0xe0af942a, 0xd1a159af, 0x55ef38d5, 0x9cef3349,
-       0xbdd4f00b, 0xfd4c3223, 0x2d347671, 0x15df043d, 0xfcbb46b7, 0xef78fece,
-       0x01387272, 0x6e10b7ee, 0xcd214371, 0xdc21da9b, 0x33d8173f, 0xde77c819,
-       0x14ff44e9, 0x977dc313, 0xd3fff870, 0xefc4e3ca, 0x879a5558, 0xeb7c549c,
-       0x16584196, 0xb51ddc91, 0x7fceb80e, 0xfcebe568, 0xeb08d687, 0xfdeee5fc,
-       0x7ed39f28, 0x6dd14b08, 0xeadaecd2, 0x197b50ec, 0xec49d6f4, 0x318baf57,
-       0x7ec5ce3f, 0x3ccbb607, 0x9719d94d, 0x1ed0cbb7, 0xedd3fe43, 0x8d5abfb1,
-       0x9e886476, 0xb3d34afd, 0x9ea15d5f, 0x4eed80bd, 0x68881bdd, 0x91c824c7,
-       0x1b38dcf5,&n