PCIE: tegra: limit mselect clk to 102Mhz
Bibek Basu [Thu, 20 Mar 2014 10:52:15 +0000 (15:52 +0530)]
This will put cap on power consumption in idle
If someone one to bup the clock, it can be done from
debugfs

Bug 1483563

Change-Id: I668193864fa26b108bec1c1f953f275847ee293c
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/384367
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

drivers/pci/host/pci-tegra.c

index 5269308..1fa0038 100644 (file)
@@ -1106,7 +1106,7 @@ static int tegra_pcie_power_ungate(void)
                pr_err("PCIE: mselect clk enable failed: %d\n", err);
                return err;
        }
-       clk_set_rate(tegra_pcie.pcie_mselect, 408000000);
+       clk_set_rate(tegra_pcie.pcie_mselect, 102000000);
        /* pciex is reset only but need to be enabled for dvfs support */
        err = clk_enable(tegra_pcie.pcie_xclk);
        if (err) {